CN114721891A - Method and device for writing data in buffer area in memory management unit - Google Patents
Method and device for writing data in buffer area in memory management unit Download PDFInfo
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Abstract
The embodiment of the application discloses a method and a device for writing data into a buffer area in a memory management unit, relates to the technical field of chip verification, and aims to shorten verification time and improve verification efficiency. The method comprises the following steps: traversing a page table to obtain a mapping relation between a virtual address and a physical address recorded in the page table; screening the mapping relation according to a preset strategy to obtain a target mapping relation; carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format; and writing the target mapping relation with the preset format into a substitution bypass buffer area in the memory management unit through a back door access function. The present application is applicable to authentication associated with replacing a bypass buffer.
Description
Technical Field
The present disclosure relates to the field of chip verification technologies, and in particular, to a method and an apparatus for writing data into a buffer in a memory management unit, an electronic device, and a readable storage medium.
Background
In order to increase the processing speed of a processor, in the design of a modern high-performance processor, a Translation Lookaside Buffer (TLB) is often arranged in a Memory Management Unit (MMU) for improving the Translation speed from a virtual address to a physical address, and in order to balance the relationship between speed and capacity, two levels of TLB, i.e., a L1TLB (Level 1Translation Look-side Buffer) and a L2TLB (Level 2Translation Look-side Buffer), are generally arranged, where the L1TLB has a fast access speed but a small capacity, and the L2TLB has a large capacity but a slow access speed.
When verifying related to the TLB, in the prior art, when the MMU performs a virtual address to physical address translation, the MMU searches the L1TLB first, if a related address mapping (TLB miss) is not found, then searches the L2TLB, if none of the TLB is found, then performs translation by using other modules, and then writes a mapping relationship into the two stages of DTLBs.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a method and an apparatus for writing data into a buffer in a memory management unit, an electronic device, and a readable storage medium, which can shorten verification time and improve verification efficiency.
In a first aspect, an embodiment of the present application provides a method for writing data in a buffer area in a memory management unit, including: traversing a page table to obtain a mapping relation between a virtual address and a physical address recorded in the page table; screening the mapping relation according to a preset strategy to obtain a target mapping relation; carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format; and writing the target mapping relation with the preset format into a substitution bypass buffer area in the memory management unit through a back door access function.
According to a specific implementation manner of the embodiment of the present application, the screening the mapping relationship according to a predetermined policy to obtain a target mapping relationship includes: and screening the mapping relation according to a preset test strategy to obtain a target mapping relation matched with the test strategy.
According to a specific implementation manner of the embodiment of the present application, the screening the mapping relationship according to a predetermined test policy to obtain a target mapping relationship matched with the test policy includes: screening the mapping relation according to a preset test strategy to obtain different types of target mapping relations matched with the test strategy; the different types of target mapping relationships include a first type of target mapping relationship and a second type of target mapping relationship, wherein the number of the first type of target mapping relationships accounts for a first predetermined proportion in the total number of all the different types of target mapping relationships, and the number of the second type of target mapping relationships accounts for a second predetermined proportion in the total number of all the different types of target mapping relationships.
According to a specific implementation manner of the embodiment of the application, the target mapping relationship comprises a mapping relationship between identification information and physical address information; the format conversion of the target mapping relationship to obtain the target mapping relationship with the predetermined format includes:
and splicing the identification information and the physical address information to obtain a target mapping relation in a preset format.
According to a specific implementation manner of the embodiment of the application, the substitution bypass buffer area in the memory management unit comprises a first-stage substitution bypass buffer area and a second-stage substitution bypass buffer area; wherein, the writing the target mapping relationship of the predetermined format into a substitute bypass buffer in a memory management unit through a back door access function includes: and writing the target mapping relation with the preset format into the specified entry in the first-level substitution bypass buffer area and/or the specified entry in the second-level substitution bypass buffer area through a back door access function.
According to a specific implementation manner of the embodiment of the present application, after writing the target mapping relationship with the predetermined format into the specified entry in the first-level substitution bypass buffer and/or the specified entry in the second-level substitution bypass buffer, the method further includes: and recording the position and the writing state of the entry written into the target mapping relation.
According to a specific implementation manner of the embodiment of the application, after performing format conversion on the target mapping relationship to obtain a target mapping relationship with a predetermined format, the method further includes: modifying the target mapping relation in the preset format; the writing the target mapping relation with the preset format into a substitution bypass buffer area in a memory management unit through a back door access function comprises: writing the modified target mapping relation in the preset format into a substitution bypass buffer area in a memory management unit through a back door access function; or, after writing the target mapping relationship with the predetermined format into a replacement bypass buffer in the memory management unit through a back-door access function, the method further includes: modifying at least one target mapping relationship written into the replacement bypass buffer to inject error data.
In a second aspect, an embodiment of the present application provides a device for writing data into a buffer in a memory management unit, including: the traversal module is used for traversing the page table to obtain the mapping relation between the virtual address and the physical address recorded in the page table; the screening module is used for screening the mapping relation according to a preset strategy to obtain a target mapping relation; the conversion module is used for carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format; and the writing module is used for writing the target mapping relation with the preset format into a substitution bypass buffer area in the memory management unit through a back door access function.
According to a specific implementation manner of the embodiment of the present application, the screening module includes: and the screening submodule is used for screening the mapping relation according to a preset test strategy to obtain a target mapping relation matched with the test strategy.
According to a specific implementation manner of the embodiment of the present application, the screening submodule is specifically configured to: screening the mapping relation according to a preset test strategy to obtain different types of target mapping relations matched with the test strategy; the different types of target mapping relations comprise a first type of target mapping relation and a second type of target mapping relation, wherein the number of the first type of target mapping relation accounts for a first predetermined proportion in the total number of all the different types of target mapping relations, and the number of the second type of target mapping relation accounts for a second predetermined proportion in the total number of all the different types of target mapping relations.
According to a specific implementation manner of the embodiment of the application, the target mapping relationship comprises a mapping relationship between identification information and physical address information; the conversion module is specifically configured to: and splicing the identification information and the physical address information to obtain a target mapping relation in a preset format.
According to a specific implementation manner of the embodiment of the application, the replacement bypass buffer area in the memory management unit comprises a first-level replacement bypass buffer area and a second-level replacement bypass buffer area; wherein the write module comprises: and the writing sub-module is used for writing the target mapping relation with the preset format into the specified entry in the first-stage substitution bypass buffer area and/or the specified entry in the second-stage substitution bypass buffer area through a back door access function.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: and the recording module is used for recording the position and the writing state of the item written in the target mapping relation after the writing sub-module writes the target mapping relation in the preset format into the specified item in the first-level substitution bypass buffer area and/or the specified item in the second-level substitution bypass buffer area.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: the modification module is used for modifying the target mapping relation in the preset format after the conversion module carries out format conversion on the target mapping relation to obtain the target mapping relation in the preset format; the write module is specifically configured to: writing the modified target mapping relation in the preset format into a substitution bypass buffer area in a memory management unit through a back door access function; or, the apparatus further comprises: a modification module, configured to modify at least one target mapping relationship written in a replacement bypass buffer area after the write module writes the target mapping relationship in the predetermined format into the replacement bypass buffer area in the memory management unit through a back-gate access function, so as to inject error data
In a third aspect, an embodiment of the present application provides an electronic device, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is configured to execute the method for writing the buffer data in the memory management unit according to any of the foregoing implementation manners.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where one or more programs are stored, and the one or more programs are executable by one or more processors to implement the method for writing the buffer data in the memory management unit according to any of the foregoing implementation manners.
In the method, the apparatus, the electronic device, and the readable storage medium for writing the data in the buffer area in the memory management unit according to the present embodiment, because the mapping relationship can be screened according to the predetermined policy to obtain the target mapping relationship, and then the target mapping relationship in the predetermined format is written into the substitute bypass buffer area in the memory management unit through the back gate access function, when performing the verification related to the substitute bypass buffer area, the target mapping relationship can be written into the substitute bypass buffer area in the memory management unit through the back gate function by using the writing method of the data in the buffer area in the memory management unit according to the present embodiment, so that when the MMU performs the substitution from the virtual address to the physical address, the target mapping relationship can be found in the substitute bypass buffer area, the verification time is shortened, and the verification efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart illustrating a method for writing data into a buffer in a memory management unit according to an embodiment of the present application;
fig. 2 is a flowchart illustrating a method for writing data into a buffer area in a memory management unit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a device for writing data into a buffer in a memory management unit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make those skilled in the art better understand the technical concepts, embodiments and advantages of the examples of the present application, the following detailed description is given by way of specific examples.
An embodiment of the present application provides a method for writing data into a buffer in a memory management unit, including: traversing a page table to obtain a mapping relation between a virtual address and a physical address recorded in the page table; screening the mapping relation according to a preset strategy to obtain a target mapping relation; carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format; and writing the target mapping relation in the preset format into a substitute bypass buffer area in the memory management unit through a back door access function, so that the verification efficiency is improved conveniently.
Fig. 1 is a flowchart illustrating a method for writing buffer data in a memory management unit according to an embodiment of the present application, where as shown in fig. 1, the method for writing buffer data in a memory management unit according to the present embodiment may include:
s101, traversing the page table to obtain the mapping relation between the virtual address and the physical address recorded in the page table.
A Memory Management Unit (MMU), which may be a Unit responsible for replacing a virtual address with a physical address for a Central Processing Unit (CPU).
The page table is a special data structure, generally having a multi-level structure, and is placed in a page table area of a system space, and a data structure for storing a mapping relationship between a virtual address and a physical address and attributes of the physical address.
Virtual addresses (Virtual addresses) may refer to physical addresses that identify a Virtual (non-physical) address, addresses that may be used by software running on the CPU to access physical memory using an indirect address access method. In this way, the memory address accessed in the program is no longer an actual physical memory address, but a virtual address, which is then mapped to the appropriate physical memory address. Therefore, the memory addresses finally accessed by different programs are ensured to be positioned in different areas and are not overlapped with each other, and the effect of memory address space isolation is achieved.
The physical address may be an address placed on an addressing bus. And if the address is read, the circuit puts the data in the physical memory of the corresponding address into the data bus for transmission according to the value of each bit of the address. If it is a write, the circuit puts the contents of the data bus into the physical memory of the corresponding address based on the value of each bit of the address.
Through the mapping relationship between the virtual address and the physical address, a virtual address can obtain a corresponding physical address.
S102, screening the mapping relation according to a preset strategy to obtain a target mapping relation.
According to a predetermined strategy, the required mapping relation, namely the target mapping relation, can be determined from the mapping relation between the virtual address and the physical address.
S103, carrying out format conversion on the target mapping relation to obtain the target mapping relation with a preset format.
The format of the target mapping relationship is translated from the format in the page table to the format adapted in the TLB.
And S104, writing the target mapping relation in the preset format into a substitution bypass buffer area in the memory management unit through a back door access function.
The back door access may be an operation opposite to the front door access, and in a broad sense, all operations that do not access a register or a memory inside the unit under test through the bus of the unit under test are back door accesses. In some examples, back-gate access functions such as UVM _ hdl _ read () and UVM _ hdl _ destination () of UVM DPI may be used, and these back-gate functions are not accessed through a physical bus, so that simulation or verification time is not consumed, and the operation efficiency of simulation or verification can be improved.
The substitute bypass buffer can be used for interaction between the virtual address and the real address, and a buffer for searching the real address is provided, so that the time consumed for searching the physical address can be effectively reduced.
In this embodiment, because the mapping relationship may be screened according to a predetermined policy to obtain a target mapping relationship, and then the target mapping relationship in a predetermined format is written into the substitute bypass buffer in the memory management unit through the back-gate access function, when performing verification related to the substitute bypass buffer, the target mapping relationship may be written into the substitute bypass buffer in the memory management unit through the back-gate function by using the writing method of the buffer data in the memory management unit of this embodiment, so that when the MMU performs substitution of a virtual address into a physical address, the target mapping relationship may be found in the substitute bypass buffer, thereby shortening verification time and improving verification efficiency.
In order to further shorten the verification time and improve the verification efficiency, another embodiment of the present application is substantially the same as the above embodiment, except that the screening of the mapping relationship according to the predetermined policy to obtain the target mapping relationship (S102) may include:
s102a, screening the mapping relation according to the preset test strategy to obtain the target mapping relation matched with the test strategy.
In this embodiment, the predetermined test policy may include a test item, a test target, and a test method.
The target mapping relation adaptive to the test strategy can be obtained from a plurality of mapping relations according to the preset test strategy, so that the target mapping relation matched with the test strategy is stored in the substitution bypass buffer when the MMU performs substitution from the virtual address to the physical address during testing, the hit rate of the substitution bypass buffer can be further increased, the verification time is further shortened, and the verification efficiency is improved.
The present application further embodiment is substantially the same as the above embodiments, except that the screening of the mapping relationship according to the predetermined test policy in this embodiment to obtain the target mapping relationship matching the test policy (S102a) may include:
and screening the mapping relation according to a preset test strategy to obtain different types of target mapping relations matched with the test strategy.
In this embodiment, the different types of target mapping relationships include a first type of target mapping relationship and a second type of target mapping relationship. The number of the first type of target mapping relations accounts for a first preset proportion in the total number of all different types of target mapping relations; the number of the second type of target mapping relationships accounts for a second predetermined proportion of the total number of all the different types of target mapping relationships.
The first type of target mapping relationship may be a mapping relationship corresponding to a larger physical space, and the second type of target mapping relationship may be a mapping relationship corresponding to a smaller physical space.
The first predetermined ratio may be 0.7 and the second predetermined ratio may be 0.3; the first predetermined ratio may be 0.43, the second predetermined ratio may be 0.5, and so on.
In the case where the first predetermined ratio and the second predetermined ratio are expressed by a decimal number, the sum of the first predetermined ratio and the second predetermined ratio may be 1 or may be less than 1.
The mapping relations are screened according to the preset test strategy to obtain different types of target mapping relations matched with the test strategy, so that different types of mapping relations with mixed proportions can be formed, and the test scene that different types of items are refreshed or covered at different storage positions is facilitated.
In some examples, the target mapping may include a mapping of identification information to physical address information; the converting the format of the target mapping relationship to obtain a target mapping relationship with a predetermined format (S103) may include:
s103a, splicing the identification information and the physical address information to obtain a target mapping relation in a preset format.
The identification information may be information to be compared in the search, and whether the entry is hit may be determined according to whether the tag of the request is consistent with the tag of the entry. The general identification information may include: a virtual Address, a hardware thread number, an Address Space Identifier (ASID), a Process Identifier (PCID), and/or a size of a mapping range (i.e., a page size).
The physical address information may be information related to a physical address, and may include: a physical address, an access right of the physical address (whether the physical address is writable, belongs to a user or a system), an address attribute (whether the physical address accesses a cache, is located in an IO space or a memory space), and the like. Wherein, according to the difference of the register configuration situation of the current CPU, the address attribute may need to be modified.
Due to the storage mode of the target TLB, namely the characteristic of the placement sequence of the identification information and the physical address information, the identification information and the physical address information can be spliced, and then the identification information and the physical address information can be placed at the corresponding positions of the respective corresponding arrays, for example, the identification information can be placed in a CAM array for searching; the physical address information is placed into the RAM array for storage.
Due to the characteristics of the encoding mode of the target TLB, in some examples, some or all of the information in the target mapping relationship may be encoded in a modified manner.
A further embodiment of the present application is substantially the same as the above embodiments, except that the replacement bypass buffer in the memory management unit of this embodiment includes a first-level replacement bypass buffer and a second-level replacement bypass buffer; in this embodiment, writing the target mapping relationship in the predetermined format into the replacement bypass buffer in the memory management unit through the back-door access function (S104), which may include:
s104a, writing the target mapping relation with the preset format into the appointed item in the first-stage substitution bypass buffer area through a back door access function, and/or writing the appointed item in the second-stage substitution bypass buffer area.
The memory management unit of this embodiment is provided with a first-level replacement bypass buffer and a second-level replacement bypass buffer, and may write a target mapping relationship in a predetermined format into a specified entry in the first-level replacement bypass buffer and/or a specified entry in the second-level replacement bypass buffer through a back-gate access function.
The first-Level Translation lookaside Buffer (L1TLB, Level 1Translation Look-side Buffer) may include a first-Level Data Translation lookaside Buffer (L1DTLB, Level 1Data Translation Look-side Buffer) and a first-Level Instruction Translation lookaside Buffer (L1ITLB, Level 1Instruction Translation Look-side Buffer); the second-Level substitution bypass Buffer may include a second-Level Data substitution bypass Buffer (L2DTLB, Level 2Data transformation Look-side Buffer) and a second-Level Instruction substitution bypass Buffer (L2ITLB, Level 2Instruction transformation Look-side Buffer).
The entry may be the smallest storage location in the first-level replacement bypass buffer and/or the second-level replacement bypass buffer, capable of storing the target mapping relationship.
According to the embodiment, the target mapping relation in the predetermined format can be written into the specified entry in the first-stage substitution bypass buffer and/or the specified entry in the second-stage substitution bypass buffer through the back-door access function as required, so that the target mapping relation in the predetermined format can be more flexibly written into the substitution bypass buffers in different stages, and in addition, the capacity and the verification speed of the buffers can be considered at the same time.
To avoid duplication or guarantee of filling the first-level replacement bypass buffer and/or the second-level replacement bypass buffer, in some examples, after writing the target mapping relationship in the predetermined format to the specified entry in the first-level replacement bypass buffer and/or the specified entry of the second-level replacement bypass buffer (S104a), the method may further include:
and S105, recording the position and the writing state of the entry of the writing target mapping relation.
The position of the item can be determined by the group number and the way number of the item; the write status includes written.
By recording the written entry position and the written state, repeated writing can be avoided or the whole first-level replacement bypass buffer area and/or second-level replacement bypass buffer area can be ensured to be filled, and a special entry effective state can be constructed according to the selection of the group number and the way number, so that the filling and elimination of entries in the first-level replacement bypass buffer area and/or the second-level replacement bypass buffer area can be conveniently tested.
In order to facilitate testing of a fault, such as a page fault or a data fault, before writing into the cache area, the target data may be modified, which is basically the same as the foregoing embodiment, except that in this embodiment, after performing format conversion on the target mapping relationship to obtain a target mapping relationship with a predetermined format (S103), the method may further include:
s106, modifying the target mapping relation in the preset format.
Writing the target mapping relationship with the predetermined format into a replacement bypass buffer in the memory management unit through a back-door access function (S104), which may include:
and writing the modified target mapping relation with the preset format into a substitution bypass buffer area in the memory management unit through a back door access function.
As an alternative embodiment, the target data may also be modified after the target relationship is written into the buffer area, and after the target mapping relationship with the predetermined format is written into the substitute bypass buffer area in the memory management unit through the back-gate access function (S104), the method may further include:
s106, modifying at least one target mapping relation written into the replacement bypass buffer area to inject error data.
When the condition of page fault or data fault is verified, the target mapping relation written into the substitution bypass buffer area can be modified, so that error data can be injected.
The page fault may refer to a fault occurring in the process of replacing a virtual address with a physical address using a page table, and includes types of an override and a page fault.
In this embodiment, a page fault test scenario is constructed by modifying at least one target mapping relationship written into the replacement bypass buffer, a processing flow of the page fault test scenario is tested, and data fault injection can test functions such as data verification and error correction.
It is understood that the method of the above embodiment can be used in the verification of TLB, the module-level verification environment and the Core verification environment, and in addition, different test scenarios can be conveniently constructed by the method of the above embodiment.
Verification of L2DTLB is more difficult than L1DTLB in existing verification work for reasons: 1, only L1DTLB miss, L2DTLB will be accessed; 2, the L2DTLB has large capacity, and a large amount of simulation time is needed when the L2DTLB is required to be filled and traversed for one-time access; 3, in order to improve the utilization efficiency, the implementation of the L2DTLB is generally complex, and there are a plurality of different storage structures, special association methods (such as skew association), and the like, which cause complex and various verification scenarios; 4, considering the time and efficiency of the verification of the whole, it is not cost-effective to independently build the verification environment for the L2 DTLB.
In order to increase the rate of L2DTLB validation, the following takes L2DTLB as an example, and the scheme of the present application is described in detail.
Referring to fig. 2, the method for writing data into a buffer area in a memory management unit according to this embodiment may include:
1. and traversing the generated page table to select the mapping relation which can be stored in the L2 DTLB.
2. And selecting a target mapping relation according to a preset strategy, and converting the target mapping relation into a format of an entry in the L2 DTLB.
3. And writing the target mapping relation into the entry at the specified position in the L2DTLB through a back door access function, and recording the filling state and the position (the group number and the way number) of each entry.
The two DPIs uvm _ HDL _ read and uvm _ HDL _ destination are used to implement a back-gate access function (read or write) to each entry in the L2DTLB, and the reason for selecting the two DPIs is that the HDL path can be treated as a character string, which is convenient to implement and has good maintainability, especially the regular path naming mode of the L2 DTLB.
In the case that an error, such as a page fault or a data fault, needs to be injected, before step 3, the method may further include:
4. and modifying the target mapping relation.
Through the process, the verification rate of the L2DTLB can be improved, all items of the whole L2DTLB can be tested easily, the verification quality of the L2DTLB can be improved, and various special test scenes can be constructed conveniently; for example, different types of entries are refreshed or overwritten in different storage locations, injecting page faults in the DTLB facilitates testing of the processing flow thereof, and data error making to test functions such as data verification and error correction.
It should be noted that the writing method according to the embodiment of the present application may be performed, that is, pre-loaded, after the L2DTLB is reset and before the formal test is started, and may also perform the foregoing process during the test.
An embodiment of the present application provides a device for writing data into a buffer in a memory management unit, including: the traversal module is used for traversing the page table to obtain the mapping relation between the virtual address and the physical address recorded in the page table; the screening module is used for screening the mapping relation according to a preset strategy to obtain a target mapping relation; the conversion module is used for carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format; and the writing module is used for writing the target mapping relation in the preset format into a substitution bypass buffer area in the memory management unit through a back door access function, so that the verification time can be shortened, and the verification efficiency can be improved.
Fig. 3 is a schematic structural diagram of a buffer data writing device in a memory management unit according to an embodiment of the present application, and as shown in fig. 3, the buffer data writing device in the memory management unit according to the embodiment may include: a traversal module 11, configured to traverse a page table to obtain a mapping relationship between a virtual address and a physical address recorded in the page table; the screening module 12 is configured to screen the mapping relationship according to a predetermined policy to obtain a target mapping relationship; the conversion module 13 is configured to perform format conversion on the target mapping relationship to obtain a target mapping relationship in a predetermined format; and a writing module 14, configured to write the target mapping relationship in the predetermined format into a replacement bypass buffer in the memory management unit through a back-door access function.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again.
The device of this embodiment can filter the mapping relationship according to the predetermined policy to obtain the target mapping relationship, and then write the target mapping relationship of the predetermined format into the substitution bypass buffer in the memory management unit through the back gate access function, and when performing the verification related to the substitution bypass buffer, the target mapping relationship can be written into the substitution bypass buffer in the memory management unit through the back gate function by using the writing method of the buffer data in the memory management unit of this embodiment, so that when the MMU performs the substitution from the virtual address to the physical address, the target mapping relationship can be found in the substitution bypass buffer, thereby shortening the verification time and improving the verification efficiency.
As an optional implementation, the screening module includes: and the screening submodule is used for screening the mapping relation according to a preset test strategy to obtain a target mapping relation matched with the test strategy.
As an optional implementation manner, the screening submodule is specifically configured to: screening the mapping relation according to a preset test strategy to obtain different types of target mapping relations matched with the test strategy; the different types of target mapping relationships include a first type of target mapping relationship and a second type of target mapping relationship, wherein the number of the first type of target mapping relationships accounts for a first predetermined proportion in the total number of all the different types of target mapping relationships, and the number of the second type of target mapping relationships accounts for a second predetermined proportion in the total number of all the different types of target mapping relationships.
As an optional implementation, the target mapping relationship includes a mapping relationship between identification information and physical address information; the conversion module is specifically configured to: and splicing the identification information and the physical address information to obtain a target mapping relation in a preset format.
As an optional implementation manner, the replacement bypass buffer in the memory management unit includes a first-level replacement bypass buffer and a second-level replacement bypass buffer; wherein the write module includes: and the writing submodule is used for writing the target mapping relation with the preset format into the specified entry in the first-level substitution bypass buffer area and/or the specified entry in the second-level substitution bypass buffer area through a back door access function.
As an optional embodiment, the apparatus further comprises: and the recording module is used for recording the position and the writing state of the item written in the target mapping relation after the writing sub-module writes the target mapping relation in the preset format into the specified item in the first-level substitution bypass buffer area and/or the specified item in the second-level substitution bypass buffer area.
As an optional embodiment, the apparatus further comprises: the modification module is used for modifying the target mapping relation in the preset format after the conversion module converts the format of the target mapping relation to obtain the target mapping relation in the preset format; the write module is specifically configured to: writing the modified target mapping relation in the preset format into a substitution bypass buffer area in a memory management unit through a back door access function; or, the apparatus further comprises: and the modifying module is used for modifying at least one target mapping relation written into the substitution bypass buffer area after the writing module writes the target mapping relation in the preset format into the substitution bypass buffer area in the memory management unit through a back door access function so as to inject error data.
The apparatus of the foregoing embodiment may be configured to implement the technical solution of the foregoing method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 4, the electronic device may include: the electronic device comprises a shell 61, a processor 62, a memory 63, a circuit board 64 and a power circuit 65, wherein the circuit board 64 is arranged inside a space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; a power supply circuit 65 for supplying power to each circuit or device of the electronic apparatus; the memory 63 is used to store executable program code; the processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, and is configured to execute any one of the methods for writing data in the buffer area in the memory management unit provided in the foregoing embodiments, so that corresponding advantageous technical effects can also be achieved.
The above electronic devices exist in a variety of forms, including but not limited to:
(1) a mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(3) A portable entertainment device: such devices can display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
(4) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.
(5) And other electronic equipment with data interaction function.
Accordingly, an embodiment of the present application further provides a computer-readable storage medium, where one or more programs are stored, and the one or more programs can be executed by one or more processors to implement the method for writing data in a buffer area in any memory management unit provided in the foregoing embodiments, so that corresponding technical effects can also be achieved, which has been described in detail above and is not described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
For convenience of description, the above devices are described as being respectively described in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations when the present application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (16)
1. A method for writing data into a buffer area in a memory management unit is characterized by comprising the following steps:
traversing a page table to obtain a mapping relation between a virtual address and a physical address recorded in the page table;
screening the mapping relation according to a preset strategy to obtain a target mapping relation;
carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format;
and writing the target mapping relation with the preset format into a substitution bypass buffer area in the memory management unit through a back door access function.
2. The method according to claim 1, wherein the screening the mapping relationship according to a predetermined policy to obtain a target mapping relationship comprises:
and screening the mapping relation according to a preset test strategy to obtain a target mapping relation matched with the test strategy.
3. The method of claim 2, wherein the screening the mapping relationship according to a predetermined test policy to obtain a target mapping relationship matching the test policy comprises:
screening the mapping relation according to a preset test strategy to obtain different types of target mapping relations matched with the test strategy; the different types of target mapping relationships include a first type of target mapping relationship and a second type of target mapping relationship, wherein the number of the first type of target mapping relationships accounts for a first predetermined proportion in the total number of all the different types of target mapping relationships, and the number of the second type of target mapping relationships accounts for a second predetermined proportion in the total number of all the different types of target mapping relationships.
4. The method of claim 1, wherein the target mapping relationship comprises a mapping relationship of identification information and physical address information; the format conversion of the target mapping relationship to obtain the target mapping relationship with the predetermined format includes:
and splicing the identification information and the physical address information to obtain a target mapping relation in a preset format.
5. The method of claim 1, wherein the replacement bypass buffer in the memory management unit comprises a first level replacement bypass buffer and a second level replacement bypass buffer;
wherein, the writing the target mapping relationship of the predetermined format into a substitute bypass buffer in a memory management unit through a back door access function includes:
and writing the target mapping relation with the preset format into the specified entry in the first-level substitution bypass buffer area and/or the specified entry in the second-level substitution bypass buffer area through a back door access function.
6. The method of claim 5, wherein after writing the predetermined format of target map to the specified entry in the first-level replacement bypass buffer and/or the specified entry in the second-level replacement bypass buffer, the method further comprises:
and recording the position and the writing state of the entry written into the target mapping relation.
7. The method according to claim 1, wherein after performing format conversion on the target mapping relationship to obtain a target mapping relationship with a predetermined format, the method further comprises:
modifying the target mapping relation of the preset format;
the writing the target mapping relation with the preset format into a substitution bypass buffer area in a memory management unit through a back door access function comprises:
writing the modified target mapping relation in the preset format into a substitution bypass buffer area in a memory management unit through a back door access function; or the like, or, alternatively,
after writing the target mapping relationship in the predetermined format into a replacement bypass buffer in the memory management unit through a back-door access function, the method further includes:
modifying at least one target mapping relationship written into the replacement bypass buffer to inject error data.
8. A device for writing data into a buffer in a memory management unit, comprising:
the traversal module is used for traversing the page table to obtain the mapping relation between the virtual address and the physical address recorded in the page table;
the screening module is used for screening the mapping relation according to a preset strategy to obtain a target mapping relation;
the conversion module is used for carrying out format conversion on the target mapping relation to obtain a target mapping relation with a preset format;
and the writing module is used for writing the target mapping relation with the preset format into a substitution bypass buffer area in the memory management unit through a back door access function.
9. The apparatus of claim 8, wherein the screening module comprises:
and the screening submodule is used for screening the mapping relation according to a preset test strategy to obtain a target mapping relation matched with the test strategy.
10. The apparatus of claim 9, wherein the screening submodule is specifically configured to:
screening the mapping relation according to a preset test strategy to obtain different types of target mapping relations matched with the test strategy; the different types of target mapping relations comprise a first type of target mapping relation and a second type of target mapping relation, wherein the number of the first type of target mapping relation accounts for a first predetermined proportion in the total number of all the different types of target mapping relations, and the number of the second type of target mapping relation accounts for a second predetermined proportion in the total number of all the different types of target mapping relations.
11. The apparatus of claim 8, wherein the target mapping relationship comprises a mapping relationship between identification information and physical address information; the conversion module is specifically configured to:
and splicing the identification information and the physical address information to obtain a target mapping relation in a preset format.
12. The apparatus of claim 8, wherein the replacement bypass buffer in the memory management unit comprises a first level replacement bypass buffer and a second level replacement bypass buffer;
wherein the write module comprises:
and the writing submodule is used for writing the target mapping relation with the preset format into the specified entry in the first-level substitution bypass buffer area and/or the specified entry in the second-level substitution bypass buffer area through a back door access function.
13. The apparatus of claim 12, further comprising:
and the recording module is used for recording the position and the writing state of the item written in the target mapping relation after the writing sub-module writes the target mapping relation in the preset format into the specified item in the first-level substitution bypass buffer area and/or the specified item in the second-level substitution bypass buffer area.
14. The apparatus of claim 8, further comprising:
the modification module is used for modifying the target mapping relation in the preset format after the conversion module carries out format conversion on the target mapping relation to obtain the target mapping relation in the preset format;
the write module is specifically configured to: writing the modified target mapping relation in the preset format into a substitution bypass buffer area in a memory management unit through a back door access function; or the like, or, alternatively,
the device further comprises:
and the modifying module is used for modifying at least one target mapping relation written into the substitution bypass buffer area after the writing module writes the target mapping relation in the preset format into the substitution bypass buffer area in the memory management unit through a back door access function so as to inject error data.
15. An electronic device, characterized in that the electronic device comprises: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing the method for writing the buffer data in the memory management unit according to any one of the preceding claims 1 to 7.
16. A computer-readable storage medium, storing one or more programs, which are executable by one or more processors, to implement the method for writing buffer data in a memory management unit according to any one of claims 1 to 7.
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| CN115543876A (en) * | 2022-11-24 | 2022-12-30 | 北京紫光芯能科技有限公司 | Method and device for verifying address decoding function, electronic equipment and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115543876A (en) * | 2022-11-24 | 2022-12-30 | 北京紫光芯能科技有限公司 | Method and device for verifying address decoding function, electronic equipment and medium |
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