CN114667681A

CN114667681A - Gate drive circuit

Info

Publication number: CN114667681A
Application number: CN202080078521.2A
Authority: CN
Inventors: 柴田比佐志
Original assignee: Tamura Corp
Current assignee: Tamura Corp
Priority date: 2019-12-20
Filing date: 2020-09-30
Publication date: 2022-06-24
Also published as: JP2021100331A; JP7037538B2; WO2021124644A1

Abstract

The invention provides a gate drive circuit, which can improve the precision of the shielding time and the tolerance of misoperation. The gate drive circuit of the present invention drives a power semiconductor switch, and is characterized by comprising: a comparison circuit for comparing a collector-emitter voltage of the power semiconductor switch with a predetermined threshold voltage; and a time measurement circuit that starts measuring time after the comparison circuit detects that the collector-emitter voltage exceeds the threshold voltage, and the gate drive circuit includes: and an output circuit that outputs an abnormal signal indicating that the power semiconductor switch is in an abnormal state after the time measurement circuit measures the standby retention time (shielding time).

Description

Gate drive circuit

Technical Field

The present invention relates to a Gate drive circuit including a short circuit detection function (circuit) of a semiconductor device, which detects a short circuit of the semiconductor device such as an Insulated Gate Bipolar Transistor (IGBT). Further, the present invention relates to a gate driver circuit including a function (circuit) of detecting an overcurrent of a semiconductor device.

Background

When the IGBT for switching high voltage and large current is destroyed, it causes a large obstacle to peripheral devices, and it is necessary to avoid the destruction as much as possible. Therefore, it is important for a gate drive circuit that drives an IGBT to protect the IGBT from such a situation. The invention relates to the following functions, namely: when the load of the IGBT is in a short-circuit state or a state close to the short-circuit state, the IGBT is protected.

Generally, as a method for detecting an abnormality such as a short circuit of a load, the following method is adopted: the rise value of Vce (collector voltage) in the ON (ON) state of the IGBT is detected.

In the conventional method, a certain time may be set after the abnormality is detected until the abnormality signal is sent out. This fixed time is a time for which the transmission of the abnormal signal is held on standby, and is sometimes referred to as a blocking time. This shielding time requires a certain accuracy in terms of preventing malfunction and preventing overload of the IGBT.

Details of the previous mode

< problem 1 > of the conventional method

Fig. 17 is a circuit diagram of a conventional method. Fig. 17 shows a circuit in which the gate driver 10 drives the IGBT 12. The gate driver 10 is in the form of a Drive Integrated Circuit (IC), and is referred to as a Drive IC in fig. 17.

The operation when the IGBT12 normally repeats an ON (ON) operation and an OFF (OFF) operation will be described. While the IGBT12 is performing the OFF (OFF) operation, the value of the output of the OUT terminal 14 of the gate driver 10(Drive IC) is LOW (LOW), and the transistor Q1 of the gate driver 10 performs the ON (ON) operation to discharge the charge of the capacitor Cdesat to 0.

When the IGBT12 is turned ON (ON), the value of the OUT terminal 14 is High (High), and a Low (Low) signal is input to the base of the transistor Q1 via the inverter 16. As a result, although the transistor Q1 is turned OFF (OFF), the collector-emitter voltage of the IGBT12 becomes a saturation voltage, and the current of the current source Idesat flows to the collector terminal of the IGBT12 via the diode Ddesat.

As a result, the capacitor Cdesat is charged to a voltage equal to the sum of the forward voltage of the diode Ddesat obtained by the current source Idesat and the saturation voltage between the collector and the emitter of the IGBT 12. That is, the inter-terminal voltage of the capacitor Cdesat becomes the saturation voltage + forward voltage of the diode Ddesat.

Since the voltage at the DESAT terminal of the gate driver 10 is maintained at a voltage lower than the reference voltage Vdesat, the comparator 18 in the gate driver 10 does not output an abnormal signal because the value of the output signal is not inverted. The voltage between terminals of the capacitor Cdesat is expressed by the following expression (1).

[ number 1]

V_Cdesat(0)＝VF_Ddesat+VCE_sat (1)

Here, VCdesat (0) is the voltage between terminals of capacitor Cdesat when IGBT12 normally operates. VFDdesat is the forward voltage of diode Ddesat. VCEsat is a saturation voltage between the collector and the emitter when the IGBT12 normally performs an ON (ON) operation.

In this state, when the load of IGBT12 is abnormal and collector-emitter voltage VCE of IGBT12 rises to reach the level of positive power supply VCC, diode Ddesat is turned off, a current of current source Idesat flows into capacitor Cdesat, and the voltage between terminals of capacitor Cdesat rises to reach reference voltage Vdesat built in gate driver 10. As a result, the comparator 18 in the gate driver 10 inverts and sends an abnormal signal.

When the voltage between terminals of capacitor Cdesat is higher than reference voltage Vdesat, the output signal of comparator 18 becomes High (High), which indicates an abnormal signal.

At this time, a mask time Tmask is set until the gate driver 10 sends out an abnormality signal after the load of the IGBT12 has abnormal, and this mask time Tmask is expressed by equation (2).

[ number 2]

Here, VCdesat (0) is the initial voltage of the capacitor Cdesat.

Cdesat represents the capacitance of the capacitor Cdesat, and Idesat represents the current value of the current Idesat.

ON the other hand, when an abnormality occurs in the IGBT12 immediately after the IGBT12 transitions from the OFF (OFF) operation to the ON (ON) operation, the capacitor Cdesat does not have the time to be charged by the Idesat current, and thus VCdesat (0) becomes 0. In this case, the occlusion time Tmask is expressed by equation (3).

[ number 3]

In this way, the masking time Tmask varies by Δ t given by equation (4) in accordance with the timing at which the IGBT12 is abnormal.

[ number 4]

Thus, there is a problem that the mask time Tmask varies depending on the timing of occurrence of the abnormality.

< problem 2 of the conventional mode

In addition, since the reference voltage Vdesat shown in fig. 17 is low, it is less tolerant to malfunction, and it is necessary to increase the voltage value of the reference voltage Vdesat as necessary. However, since the voltage is built in the gate driver 10, there is a problem that it is generally difficult to change the voltage value.

Prior art of the patent

For example, patent document 1 (japanese patent laid-open No. 2004-140891) described later discloses a power converter capable of reliably detecting the occurrence of a failure in a part of elements constituting an overvoltage protection circuit. Specifically, the following circuit is described: when the time exceeds a set time, it is determined that a part of the elements constituting the overvoltage protection circuit is in a failure.

Documents of the prior art

Patent literature

Patent document 1: japanese patent laid-open No. 2004-140891

Disclosure of Invention

Problems to be solved by the invention

Thus, the conventional method has the following problems.

Problem 1: variation of the shade time due to conditions at short circuit

As described above, when the load of the IGBT is in the short-circuit state, a large current flows, and the Vce of the IGBT rises and is broken, but a blocking time is required to delay detection in a period of several microseconds. The shielding time needs to be accurate, and particularly needs to be as constant as possible even when the load short-circuit condition varies.

Here, the change in the condition of the load short circuit includes, for example: the magnitude of the inductance connected to the IGBT changes during a short circuit. For example, it is desirable that the shielding time is not changed in a case where the inductance of the load is very small (e.g., 200nH) and a case where the inductance of the load is relatively large (e.g., 2 μ H).

However, when a general-purpose control IC is used as a gate driver to drive an IGBT, the blocking time varies mainly due to the change in the load short-circuit condition as described above.

Problem 2: tolerance to malfunction

Further, the gate driver disposed in the vicinity of the IGBT under a large current and a high voltage requires a large margin for malfunction. However, a gate driver using a general-purpose control IC may have a low threshold voltage and may not have a sufficient margin for malfunction.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a gate drive circuit that improves the accuracy of a blocking time and the tolerance for a malfunction.

Means for solving the problems

First, as for the improvement of the accuracy of the occlusion time, the following method is adopted: the initial charge of the capacitor determining the time constant is controlled to reduce the variation of the shielding time. The present inventors have made extensive studies on a method of controlling the initial charge of a capacitor to 0 or a constant value, for example, and have completed the present invention.

Further, as for improvement of tolerance against malfunction, a method of configuring a circuit so that a threshold voltage can be set separately is adopted. The present inventors have conducted various studies on a circuit for separately setting a threshold voltage, and as a result, have completed the present invention.

Specifically, the present invention adopts the following means.

(1) In order to solve the above problems, the present invention provides a gate driving circuit for driving a power semiconductor switch, including: a comparison circuit for comparing a collector-emitter voltage of the power semiconductor switch with a predetermined threshold voltage; and a time measurement circuit that starts measuring time after the comparison circuit detects that the collector-emitter voltage exceeds the threshold voltage, and the gate drive circuit includes: and an output circuit that outputs an abnormal signal indicating that the power semiconductor switch is in an abnormal state after the time measurement circuit measures the standby retention time.

(2) The present invention is the gate drive circuit described in (1), wherein the comparison circuit compares the collector-emitter voltage with the predetermined threshold voltage when the collector current increases due to a predetermined obstacle or abnormality and the power semiconductor switch is in a desaturated state immediately after the power semiconductor switch is turned from an OFF (OFF) operation to an ON (ON) operation or in a state where the power semiconductor switch is in a saturated (saturation) state.

(3) The present invention is the gate drive circuit according to (1) or (2), wherein the abnormality signal is a signal that changes to a predetermined value in response to a predetermined output signal and means that the power semiconductor switch is in a desaturated state.

(4) The gate driving circuit according to any one of (1) to (3), wherein the time measuring circuit includes: a charging capacitor to which a charging current of a constant current value is applied, the charging capacitor being configured to set a standby retention time to a time until an inter-terminal voltage of the capacitor increases to a predetermined voltage value in association with charging; and a charging current bypass circuit that bypasses a current of the constant charging current value when the power semiconductor switch is in a saturated state and the collector-emitter voltage is equal to or less than the threshold voltage of the comparator, and sets the initial charge of the charging capacitor to 0 without causing the charging current to flow into the charging capacitor, wherein the comparison circuit interrupts the charging current bypass circuit and causes the constant charging current value to flow into the capacitor from a state in which the initial charge of the capacitor is 0 when the power semiconductor switch is in a desaturated state and it is detected that the collector-emitter voltage exceeds the threshold voltage of the comparison circuit.

(5) The gate driving circuit according to the present invention is the gate driving circuit according to (4), including: and a first initial charge charging circuit that, when a delay time is generated until the power semiconductor switch actually turns ON (ON) after outputting a signal for causing the power semiconductor switch to transition from an OFF (OFF) state to an ON (ON) state, which is a driving target, causes initial charge to remain in the charging capacitor, and generates the standby retention time that is short by the charging time of the initial charge, and the output circuit outputs an abnormal signal indicating that the power semiconductor switch is in a desaturated state after the time measurement circuit measures the short standby retention time.

(6) The gate drive circuit according to the present invention as set forth in (4) is characterized in that, when a delay time is generated until the power semiconductor switch actually turns ON (ON) after a signal for switching the power semiconductor switch as a drive target from an OFF (OFF) state to an ON (ON) state is output, the charging current bypass circuit includes a bypass switch for bypassing the charging current and a series circuit of a resistor directly connected to the bypass switch, and even when the charging current is bypassed by the charging current bypass circuit, the output circuit causes the initial charge to remain in the charging capacitor to the extent of the initial charge resistance and generates the standby retention time to the extent of shortening the charging time of the initial charge, and after the time measurement circuit measures the short standby retention time, the output means an abnormal signal that the power semiconductor switch is in a desaturated state.

(7) The gate driver circuit according to any one of (1) to (6) of the present invention includes: a diode having a cathode terminal connected to the comparison circuit and an anode terminal connected to a collector terminal of the power semiconductor switch, wherein the comparison circuit detects a collector voltage of the power semiconductor switch via the diode.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, it is possible to provide a gate drive circuit that drives a power semiconductor switch and that improves the accuracy of standby retention time (blocking time) and the tolerance for malfunction.

Drawings

Fig. 1 is a circuit diagram of a gate driver circuit 100 according to embodiment 1.

Fig. 2 is a functional block diagram of the circuit shown in fig. 1.

Fig. 3 is a circuit diagram of a gate driver circuit 200 according to embodiment 2.

Fig. 4 is a circuit diagram of an equivalent circuit in a transition state of the IGBT from an OFF (OFF) operation to an ON (ON) operation.

Fig. 5 is a graph showing a voltage waveform of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode D1 is not provided.

Fig. 6 is a graph showing a voltage waveform of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode D1 is inserted.

Fig. 7 is a time chart showing a state of the blocking time fluctuation when a load abnormality occurs after the completion of the ON (ON) operation of the IGBT12 in the case where the transient operation of the IGBT12 to the ON (ON) operation is delayed.

Fig. 8 is a time chart showing a state of the blocking time fluctuation when a load abnormality occurs before the completion of the ON (ON) operation of the IGBT12 in the case where the transient operation of the IGBT12 to the ON (ON) operation is delayed.

Fig. 9 is a circuit diagram of a gate drive circuit 300 according to embodiment 3.

Fig. 10 is a timing chart showing a state of the blocking time fluctuation when a load abnormality occurs after the IGBT12 completes the ON (ON) operation in the circuit shown in embodiment 3.

Fig. 11 is a diagram showing an example of another structural circuit for making an initial charge, and is a circuit diagram of the gate driver circuit 400.

Fig. 12 is a circuit diagram of a gate driving circuit 500 according to one embodiment.

Fig. 13 is a graph showing the blocking time when an abnormality occurs after 20 μ sec after the IGBT12 performs the ON (ON) operation.

Fig. 14 is a graph showing the blocking time when an abnormality occurs immediately after the IGBT12 performs the ON (ON) operation.

Fig. 15 is a circuit diagram of a gate driving circuit 600 according to a second embodiment.

Fig. 16 is a circuit diagram of a gate driving circuit 700 according to a third embodiment.

Fig. 17 is a circuit diagram showing a circuit configuration in a case where the conventional gate driver 10 drives the IGBT 12.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

1. Embodiment mode 1

Fig. 1 shows a circuit diagram illustrating a gate driver circuit 100 according to the present embodiment. In fig. 1, the portion other than the IGBT12 becomes a characteristic portion of the gate drive circuit 100.

As shown in fig. 1, the gate driver 110 is used in the same manner as the conventional circuit shown in fig. 17, and the structure and operation of this gate driver 110 are the same as those of the gate driver 10 shown in fig. 17. The gate driver 110 may include a predetermined IC or the like, as in the gate driver 10 shown in fig. 17.

The OUT terminal 114 of the gate driver 110 is connected to the gate terminal of the IGBT12 via the buffer 120, and drives the IGBT 12. A capacitor Cdesat is connected between the GND terminal and the DESAT terminal of the gate driver 110. As will be described later, this capacitor Cdesat is an element that plays an important role in determining the shielding time by the charging operation.

Here, the IGBT12 corresponds to a suitable example of the claimed power semiconductor switch. The gate driver circuit 100 corresponds to a suitable example of the claimed gate driver circuit. The

gate driver circuits

200, 300, 400, 500, 600, and 700 described later also correspond to suitable examples of the gate driver circuits in the claims.

The transistor Q2 has a collector terminal connected to the desata terminal and an emitter terminal connected to the GND terminal. The base terminal of the transistor Q2 is connected to the output terminal of the comparator CMP 2. As will be described later, the transistor Q2 functions to discharge the charge of the capacitor Cdesat. The inverting input terminal of the comparator CMP2 is connected to the positive-side power supply VCC via a resistor Rdesat. The inverting input terminal is connected to the anode terminal of the diode Ddesat.

The anode terminal of the diode Ddesat is connected to the inverting input terminal of the comparator CMP2, and the cathode terminal is connected to the collector terminal of the IGBT 12.

The non-inverting input terminal of the comparator CMP2 is connected to the positive terminal of the second reference voltage Vdesat-2. The other (negative side) terminal of the second reference voltage Vdedsat-2 is connected to the GND terminal.

The emitter terminal of the IGBT12 is connected to the GND terminal.

The transistor Q2 corresponds to a suitable example of the claimed charging current bypass circuit.

When the IGBT12 is in an OFF (OFF) operating state, the collector voltage of the IGBT12 becomes high, and the positive power supply VCC is applied to the inverting input terminal of the comparator CMP 2. The output signal of the comparator CMP2 becomes Low (Low), and the transistor Q2 becomes OFF (OFF).

At this time, the output signal of the OUT terminal of the gate driver 110 (applied to the gate terminal of the IGBT 12) is Low (Low), and this output signal is inverted to High (High) by the inverter 116 and applied to the base terminal of the transistor Q1. Therefore, transistor Q1 of gate driver 110 maintains the ON (ON) operation state, and discharges the electric charge of capacitor Cdesat. Therefore, the initial voltage of the capacitor Cdesat becomes 0V.

The capacitor Cdesat corresponds to a suitable example of the claimed charging capacitor. Note that the capacitor C3 shown in fig. 12 and the like described later also corresponds to a suitable example of the claimed charging capacitor.

When the output signal of the OUT terminal 114 becomes High (High), the IGBT12 is turned ON (ON). At this time, the output signal of the OUT terminal 114 is inverted by the inverter 116 and applied to the base terminal of the transistor a1, and thus the transistor Q1 is turned OFF (OFF).

Since the collector-emitter voltage (collector voltage) of the IGBT12 becomes a saturation voltage, the voltage applied to the inverting input terminal of the comparator CMP2 becomes the sum of the forward voltage of the diode Ddesat and the collector-emitter saturation voltage of the IGBT12, i.e., VFDdesat + VCEsat, lower than the second reference voltage Vdesat-2, and the transistor Q2 becomes an ON (ON) state.

In the present embodiment, even when IGBT12 is turned ON (ON), transistor Q2 turns ON (ON) so that capacitor Cdesat is not charged with electric charge. As a result, the inter-terminal voltage of the capacitor Cdesat can be maintained at 0V. That is, the initial voltage of the capacitor Cdesat may be fixed to 0.

Here, when the load of the IGBT12 becomes abnormal and the collector-emitter voltage of the IGBT12 rises to exceed the second reference voltage Vdesat-2-VFDdesat, the voltage at the inverting input terminal of the comparator CMP2 exceeds the second reference voltage Vdesat-2. Therefore, the output signal of the comparator CMP2 goes Low (Low), the transistor Q2 turns OFF (OFF), and the current source Idesat in the gate driver 110 starts charging the capacitor Cdesat.

When the inter-terminal voltage VCdesat of the capacitor Cdesat exceeds the first reference voltage Vdesat-1 due to the charging, the output signal of the comparator CMP1 in the gate driver 110 is inverted to become High (High), and an abnormal signal is transmitted.

The shielding time until the abnormal signal is sent after the IGBT12 becomes abnormal and the collector-emitter voltage of the IGBT12 exceeds Vdesat-2-VFDdesat is expressed by the following expression (5).

[ number 5]

As described above, in the formula (5), the VCdesat (0) term associated with the initial charge of the capacitor Cdesat is not related as in the formula (2) in the case of the conventional art, and therefore, a certain shielding time can be always achieved without depending on the timing of occurrence of an abnormality.

Since the second reference voltage Vdesat-2 can be arbitrarily selected as long as it is equal to or lower than the positive side voltage VCC, it is possible to further increase the tolerance against malfunction such as noise. Therefore, the disadvantage of the conventional method that it is difficult to secure a margin against noise can be eliminated. The second reference voltage Vdesat-2 corresponds to a suitable example of the threshold voltage defined in the claims.

Functional block diagram

Fig. 2 shows a functional block diagram of the circuit of fig. 1 according to embodiment 1.

In the functional block diagram of fig. 2, a time measurement circuit 130 and a comparison circuit 132 are shown in addition to the gate driver 110.

The comparator 132 is a circuit corresponding to the comparator CMP2 and the second reference voltage Vdesat-2 in fig. 1, and corresponds to a suitable example of the comparator of the claims. Therefore, the comparison circuit 132 compares the collector-emitter voltage of the IGBT12 with the second reference voltage Vdesat-2, and outputs the comparison result.

The second reference voltage corresponds to a suitable example of the threshold voltage defined in the claims.

The time measurement circuit 130 is a circuit corresponding to the capacitor Cdesat and the transistor Q2 in fig. 1, and corresponds to a suitable example of the claimed time measurement circuit.

The transistor Q2 constitutes the claimed charge current bypass circuit, and can perform an operation of charging the capacitor Cdesat while bypassing or not bypassing the charge current of the capacitor Cdesat based on the output signal of the comparison circuit 132.

One of the characteristic matters in the present embodiment is that a charging current open circuit (transistor Q2) is provided. This can set the charge of the capacitor Cdesat at the charge start time to 0 in advance, and can measure the shading time more accurately.

The gate driver 110 corresponds to a suitable example of the claimed output circuit. In particular, the output signal of the comparator CMP1 corresponds to a suitable example of the claimed abnormality signal.

2. Embodiment mode 2

Fig. 3 shows a circuit diagram of a gate driver circuit 200 according to embodiment 2. Fig. 3 is a circuit in which a diode D1 is inserted between the inverting input terminal of the comparator CMP2 and the anode of the diode Ddesat in fig. 1, and a capacitor C1 is added. The capacitor C1 represents a capacitor inserted to absorb parasitic capacitance of the inverting input terminal of the comparator CMP2 or noise causing malfunction. The configuration other than these additional configurations is the same as that of fig. 1.

The diode D1 corresponds to a suitable example of the claimed diode.

In this way, when the capacitor C1 is present, the capacitor C1 may be charged with the charge of the capacitance present between the terminals of the diode Ddesat in the negative direction due to the transition phenomenon in which the IGBT12 transitions from the OFF (OFF) operation to the ON (ON) operation, thereby blocking the time variation. The diode D1 is a diode for preventing this phenomenon.

When the IGBT12 is in the OFF (OFF) operation state, the diode Ddesat is reversely biased and thus can be equivalently regarded as a capacitor. A voltage close to the collector voltage when the IGBT12 is in the OFF (OFF) state is applied to the equivalent capacitor, and when the IGBT12 shifts from the OFF (OFF) state to the ON (ON) state, immediately thereafter, as shown in the equivalent circuit of fig. 4, the capacitor C1 is charged in the negative direction, and the time until the detection operation of the comparator CMP2 is resumed is delayed. Fig. 4 shows an equivalent circuit in a transition state of the IGBT12 from an OFF (OFF) operation to an ON (ON) operation.

In fig. 4, Vhi is a collector voltage when IGBT12 performs an OFF (OFF) operation, and is a sufficiently high voltage with respect to positive power supply VCC. Therefore, the transient waveform of the voltage between the terminals of the capacitor C1 when the IGBT12 is regarded as Vhi-VCC ≈ Vhi and turned ON (ON) from the OFF (OFF) operation can be expressed by equation (6).

[ number 6]

According to the above equation (6), at the moment when the IGBT12 performs the ON (ON) operation, the inter-terminal voltage of the capacitor C1 is charged to a negative voltage of-Vhi × (CDdesat/(C1+ CDdesat)). Then, return to 0V with a time constant Rdesat (C1+ CDdesat). This recovery time causes the blocking time to be different between the case where a load abnormality occurs immediately after the IGBT12 performs the ON (ON) operation and the case where a load abnormality occurs after the recovery time ends.

CDdesat represents the capacitance of the equivalent capacitor of the diode Ddesat, C1 represents the capacitance of the capacitor C1, and Rdesat1 represents the resistance value of the resistor Rdesat.

That is, when the load becomes abnormal immediately after the IGBT12 performs the ON (ON) operation, the detection of the rise of the collector-emitter voltage Vce of the IGBT12 is delayed by the recovery time, and the final shielding time becomes longer by the recovery time. Therefore, as shown in fig. 3 of embodiment 2, the diode D1 is inserted to suppress the phenomenon.

The graphs of fig. 5 and 6 show voltage waveforms at the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode D1 is not included and in the case where the diode D1 is inserted. In each graph, the horizontal axis represents the passage of time, and the vertical axis represents the voltage waveform of the non-inverting input terminal and other various signal waveforms.

In the case where the diode D1 is not provided (fig. 5), the non-inverting input terminal of the comparator CMP1 of the gate driver 110 decreases in potential in the negative direction at the moment when the IGBT12 turns ON (ON), and then the value of the potential gradually recovers. In the example of fig. 5, a time of approximately 1 μ sec bit is required, and a label of "increased time" is attached in fig. 4. Therefore, the shielding time becomes long to the extent described above, resulting in variation in the shielding time. That is, although the time until the charging voltage of the capacitor Cdesat exceeds the first reference voltage Vdesat-1 becomes the shielding time, as shown in fig. 5, the shielding time becomes longer (varies) to the extent of the "increased time".

On the other hand, when the diode D1 is inserted, the voltage change at the non-inverting input terminal of the comparator CMP1 of the gate driver 110 is canceled, indicating that there is no cause of the variation in the masking time (see fig. 6).

As described above, according to the present embodiment, it is possible to effectively remove noise that causes malfunction and suppress variation in the masking time.

3. Embodiment 3

Depending ON the characteristics of the IGBT12 or the demand of the installation side for power control by the IGBT12, there is a case where a delay time is long until the actual IGBT12 turns ON (ON) after an ON (ON) signal is generated from a control circuit that outputs a control signal for the IGBT 12. The characteristics of the IGBT12 include, for example, a very large gate resistance.

In such a situation, the load circuit shown in embodiment 1 (fig. 1) may have a variation in the blocking time depending on the occurrence timing of the abnormality.

Fig. 7 and 8 show timing charts showing the following states: in a circuit including the gate drive circuit 100 described with reference to fig. 1, when the switching operation of the IGBT12 to the ON (ON) operation is delayed, the blocking time varies depending ON the occurrence timing of the load abnormality.

Fig. 7 shows an example of occurrence of a load abnormality after the IGBT12 completes the ON (ON) operation. In other words, it is a time chart of a case where a load abnormality occurs after a delay time of an ON (ON) operation of the IGBT 12. In fig. 7, the horizontal axis represents the passage of time, and the vertical axis represents various signals. Specifically, the voltage across the capacitor Cdesat, the ON (ON)/OFF (OFF) state of the IGBT12, the gate-source voltage of the IGBT12, and a control signal from a control circuit that controls the IGBT12 are shown.

First, when the control signal from the control circuit reaches a value at which the IGBT12 is turned ON (ON), the gate-source voltage of the IGBT12 starts to rise, and the voltage across the capacitor Cdesat also starts to rise.

In the example of fig. 7, the response speed of the IGBT12 is slow, and the IGBT12 turns to an ON (ON) operation after the delay time td elapses. Then, the both-end voltage of the capacitor Cdesat is reset to 0. However, when a failure occurs, for example, a short-circuit failure of the load, the charging of the capacitor Cdesat is started, and the timing of the shielding time is started.

The shielding time at this time is t1 (see fig. 7), the charging capacitor Cdesat is charged from the initial charge of 0, and the charging time until the voltage across the capacitor Cdesat reaches Vdesat from 0V becomes the shielding time.

ON the other hand, fig. 8 shows an example in which a load abnormality occurs before the IGBT12 performs an ON (ON) operation. In other words, the timing chart is a timing chart of a case where a load abnormality occurs within the ON (ON) operation delay time of the IGBT 12.

In fig. 8, the horizontal axis represents the passage of time, and the vertical axis depicts the same kind of signals as in fig. 6, as in fig. 7.

When the control circuit defined as a normal operation of the gate driver 110 sets the value of the control signal to a value for turning ON (ON) the IGBT12 (when an ON (ON) operation command is generated), the bypass circuit of the charging current in the gate driver 110 is substantially simultaneously turned OFF (the transistor Q1 performs an OFF (OFF) operation).

That is, the output signal of the OUT terminal in fig. 1 becomes High (High), and this signal is applied to the base terminal of the transistor Q1 via the inverter 116, so that the transistor Q1 as a bypass circuit of the charging current is turned OFF (OFF).

In the example of fig. 8, the ON (ON) operation of the IGBT12 is delayed, and thus the voltage at the inverting input terminal of the comparator CMP2 of fig. 1 is higher than Vdesat-2, and therefore the transistor Q2 also maintains the OFF (OFF) state. Therefore, substantially simultaneously with the control signal instructing to turn ON (ON) the IGBT12, the charging of the charging capacitor Cdesat is started. This situation is shown in the timing diagram of fig. 8. At this time, the gate-source voltage of the IGBT12 also gradually increases, but the ON (ON) operation of the IGBT12 is delayed, and therefore the OFF (OFF) state of the IGBT12 continues for a certain period of time (see fig. 8).

Specifically, the OFF state of the IGBT12 continues for a delay time td.

In the example illustrated in fig. 8, an obstacle such as a short circuit occurs before the IGBT12 performs an ON (ON) operation.

After the delay time td in fig. 8, the IGBT12 is delayed to turn ON (ON). However, since the load abnormality has occurred when the IGBT12 is turned ON (ON) (at the time point when the delay time td elapses), even if the IGBT12 is turned ON (ON), the voltage of the inverting input terminal of the comparator CMP2 continues to be maintained at a voltage higher than Vdesat-2, and the transistor Q2 continues to be maintained in the OFF (OFF) state, and the capacitor Cdesat continues to be charged. Therefore, the time until the inter-terminal voltage of capacitor Cdesat reaches Vdesat-1 from 0V becomes t2 (see fig. 8).

This time t2 is the same time as the occlusion time t1 of FIG. 7. However, the time measurement of the unsaturated state (Desaturation state) (hereinafter referred to as Desat state) must be started after the IGBT12 actually enters the Desat state. That is, in this case, immediately after the IGBT12 turns ON (ON) (at the time when the delay time td in fig. 8 elapses), this time must be the starting point of time measurement. This is because protection by Desat detection (detection of an unsaturated state) must protect the IGBT12 and determine the shielding time from the viewpoint of preventing malfunction of the protection circuit, and therefore, the balance between them must be considered as much as possible.

When the shielding time is defined in this way, the shielding time in the situation described in fig. 8 is t3 shown in fig. 8, and there is a problem that the delay time td of the IGBT12 is shorter than the shielding time t1 shown in fig. 7.

In this case, as shown in fig. 9, it is preferable to adopt the following method for discharging the capacitor Cdesat by the transistor Q2: at the beginning of the discharge of the capacitor Cdesat, the initial charge is barely given to the capacitor Cdesat. Vb of FIG. 9 plays the following role: when IGBT12 has completed the ON (ON) operation transition, transistor Q2 discharges capacitor Cdesat, but the charge of capacitor Cdesat is not completely discharged, and Vb of the inter-terminal voltage of capacitor Cdesat remains. That is, even when the transistor Q2 is turned ON (ON), the voltage between terminals of the capacitor Cdesat does not become 0V but becomes Vb. Vb is set to a value equal to the voltage Vd between the terminals of capacitor Cdesat shown in fig. 7 when IGBT12 turns ON (ON) with its own delay time.

As a result of setting Vb to Vd (fig. 7) as Vb (fig. 9), the blocking time can be set constant regardless of the occurrence timing of the load abnormality as shown in fig. 9.

The circuit shown in fig. 9 is the same as that shown in fig. 1 except that a new voltage source Vb is provided. That is, the gate driving circuit 300 shown in fig. 9 is the same circuit as the gate driving circuit 100 of fig. 1 except for the voltage source Vb.

Vb corresponds to a suitable example of the first initial charge charging circuit.

Fig. 10 is a timing chart for explaining the operation of the circuit (gate driver circuit 300) shown in fig. 9. Fig. 10 shows substantially the same timing chart as fig. 7 and 8, in which the horizontal axis represents the passage of time and the vertical axis shows the same kind of signals as fig. 7 and 8. When the timing charts of fig. 10 and 7 are compared, the same signal waveform is obtained until the time point when the IGBT12 starts the ON (ON) operation.

At the time point when the IGBT12 starts the ON (ON) operation, the voltage across the terminals of the capacitor Cdesat is reset to 0 in fig. 7, but the voltage Vd at this time point is maintained in the time chart of fig. 10. This is caused by the voltage source Vb having the new configuration shown in fig. 9, and Vb is set to Vd, which is a time chart of this kind.

Fig. 10 illustrates an example in which a short-circuit fault occurs after the IGBT12 turns ON (ON) as in fig. 7. Fig. 10 is also the same as fig. 7 in that the charging of the capacitor Cdesat is started after the occurrence of the short-circuit failure. However, in the example shown in fig. 10, the capacitor Cdesat is charged to the voltage Vb (═ Vd) at the charging start time point, and thus the initial voltage at the charging start time point is different. As a result, the occlusion time of the example of fig. 10 becomes t4, and as described above, this time is the same time as the occlusion time t3 of fig. 8.

Another example of setting of the initial charge value

Another circuit configuration for creating the initial charge is shown in fig. 11. As shown in this figure, a resistor Rb is inserted in series to the collector of the transistor Q2. At this time, the initial charge Vd becomes Vd ═ IdesatRb. In this equation, Rb is a resistance value of the resistor Rb, and a voltage generated in the resistor Rb by a current of the current source Idesat is used.

Therefore, Rb corresponds to a suitable example of the claimed initial charge resistance. The transistor Q2 corresponds to a suitable example of the bypass switch of the claims.

As described above, according to embodiment 2, since the voltage value at the start time point of starting charging of capacitor Cdesat is set to a predetermined value, the shielding time can be maintained at a constant value regardless of whether the time point of occurrence of the load abnormality is before the ON (ON) operation of IGBT12 or after the ON (ON) operation.

4. Detailed description of the preferred embodiments

4.1 first embodiment

A circuit diagram of a gate driver circuit 500 as a specific embodiment of the invention is shown in fig. 12. The gate driver 110 is a gate driver for driving the IGBT used in fig. 1, 2, 8, and 10, and may include an IC or the like. The comparator IC1 is a comparator whose output is an open collector (open collector) output. The second reference voltage Vdesat-2 in fig. 1, 3, 9, and 11 is formed by the divided voltage value of VCC obtained by the resistors R1 and R2 and the capacitor C2. The resistor R4 and the capacitor C1 increase the margin of malfunction, and are resistors and capacitors for reducing the impedance of the input terminal of the comparator IC 1. The capacitor C3 is a capacitor for charging the shading time. The diode D1 corresponds to the diode D1 of fig. 3. R5 is a resistance corresponding to Rb in fig. 11 of embodiment 3.

The comparator IC1 has a structure corresponding to the comparator CMP2 and the transistor Q2 in fig. 1 and the like. That is, the output transistor of the comparator IC1 is open-collector, and functions as the transistor Q2 shown in fig. 1 and the like. Therefore, the structure corresponding to the transistor Q2 is not directly depicted in fig. 12.

The diodes D2, D3, D4 correspond to the diodes Ddesat in fig. 1, 3, 9, 11. Here, the second reference voltage Vdesat-2 in fig. 1, 3, 9, and 11 is represented by the following formula (7) in fig. 12.

[ number 7]

Here, when the maximum value of the voltage at the non-inverting input terminal of the comparator IC1 is VSON when the IGBT12 performs the ON (ON) operation in the normal range, Vdesat-2 is set higher than VSON. VSON and Vaest-2 are in the relationship of the following formula (8).

VFD1 is the forward voltage drop of diode D1, and VFD2-4 is the sum of the forward voltage drops of diodes D2, D3, and D4. The maximum value of the collector-emitter voltage when the IGBT12 performs an ON (ON) operation in the normal range is VCESAT.

[ number 8]

V_SON＝VCE_SAT+VF_D2-4-VF_D1<V_desat-2 (8)

When the output signal of the OUT terminal 114 of the gate driver 110 is Low (Low), the IGBT12 performs an OFF Operation (OFF). At this time, the diodes D2, D3, and D4 are reverse biased and turned off. Therefore, the diode D1 is in a forward bias state, and the voltage at the non-inverting input terminal of the comparator IC1 becomes higher than the second reference voltage Vdesat-2.

Therefore, although the output transistor of the comparator IC1 is turned OFF (OFF), the transistor Q1 of the gate driver 110 is turned ON (ON), and thus the current source Idesat does not charge the capacitor C3 but flows to VEE via the transistor Q1. As a result, in this state, the DESAT terminal voltage of the gate driver 110 does not rise, and the voltage is kept lower than the first reference voltage Vdesat-1, so that the comparator CMP1 does not output an abnormal signal (the output signal does not become High).

When the IGBT12 is turned ON (ON) and continues operating normally, the collector-emitter voltage of the IGBT12 is maintained at the saturation voltage VSAT or below. Therefore, the voltage at the non-inverting input terminal of the comparator IC1 becomes lower than VSON given by the above equation (8), and the output transistor of the comparator IC1 turns ON (ON). Therefore, the current source Idesat of the gate driver 110 flows to VEE via the output transistor of the comparator IC1 without charging the capacitor C3. Therefore, when the IGBT12 maintains this state (ON state), no abnormal signal is output (the output signal does not become High).

When a load abnormality occurs and the IGBT12 is in a Desat state (Desat state) in a state where the IGBT12 is in an ON (ON) operation, the collector-emitter voltage of the IGBT12 increases. When the collector-emitter voltage of the IGBT12 at this time is denoted as VCEDESAT, the voltage VSONDESAT at the non-inverting input terminal of the comparator IC1 is given by the following expression (9).

[ number 9]

V_SONDESAT＝VCE_DESAT+VF_D2-4-VF_D1 (9)

When VSONDESAT exceeds the second reference voltage Vdesat-2, the output transistor of the comparator IC1 turns OFF (OFF), and the current source Idesat flows to the capacitor C3, thereby starting charging the capacitor C3. When the voltage between the terminals of the capacitor C3 reaches the first reference voltage Vdesat-1 due to the charging, the comparator CMP1 inverts to send an abnormal signal (the output signal becomes High).

Therefore, collector-emitter voltage VCEDET determined that IGBT12 has entered the Desat state due to the load abnormality can be expressed by the following expression (10). The shielding time Tmask from when the IGBT12 is determined to be in the Desat state due to the load abnormality until the abnormality signal is transmitted is expressed by the above-described expression (5).

[ number 10]

VCE_DET＝V_desat-2-VF_D2-4+VF_D1 (10)

When the collector-emitter voltage of the IGBT12 reaches VCEDET of the above expression (10) due to a load abnormality or the like immediately after the IGBT12 is turned from the OFF (OFF) operation to the ON (ON) operation, the capacitor C1 is charged in the negative direction by the high voltage (Vhi of fig. 4) charged to the equivalent capacitor (Ddesat of fig. 4) between the terminals of the diodes D2 to D4, but the diode D1 is reversely biased, and the charging in the negative direction is prevented.

Therefore, the circuit of fig. 12, which is a suitable embodiment of the present invention, can keep the delay time, i.e., the shielding time, from the detection of the Desat state of the IGBT12 until the abnormal signal is sent, constant.

Fig. 13 and 14 show experimental data of the shielding time in the case where the IGBT12 is in the Desat state after about 20 μ sec after the ON (ON) operation and the shielding time in the case where the IGBT12 is in the Desat state immediately after the ON (ON) operation. It was confirmed that the occlusion time was about 4.6 μ sec, and a difference between the two was hardly observed, and a certain occlusion time was obtained. In both fig. 13 and 14, the horizontal axis represents the passage of time, and the vertical axis represents a voltage value or a current value.

In fig. 13, a graph is plotted with respective signals of the gate voltage, the collector current, and the collector-emitter voltage, and at the time point when the IGBT12 is turned ON (ON), the gate voltage instantaneously rises and the collector-emitter voltage instantaneously falls. Then, the collector current gradually increases from the time point when the IGBT12 transitions to the ON (ON) state.

In the graph of fig. 13, an abnormality occurs after 20 μ sec after the IGBT12 is turned ON (ON), and an abnormality signal starts to be sent after the blocking time 4.7 μ sec.

The graph of fig. 14 is a graph of the same kind as the graph of fig. 13, although the time scale is different, and the kind of the signal shown is also the same.

In the case where the delay time from when the IGBT12 receives the ON (ON) signal to when the IGBT12 is actually turned ON (ON) is long, the blocking time can be kept constant by inserting the resistor Rd into the output of the comparator IC1 in fig. 12 in accordance with the delay time.

4.2 detailed description of the invention

Fig. 15 shows a circuit diagram of a gate driver circuit 600 according to a second embodiment of the present invention. The difference from the gate driving circuit 500 of fig. 14 is the connection position of the resistor R3.

In the gate drive circuit 500 of fig. 14, the resistor R3 is provided to connect the positive power supply VCC to the anode side of the diode D1. In contrast, in the gate driver circuit 600 of fig. 15, the resistor R3 is provided so as to connect the output signal of the OUT terminal 114 to the anode side of the diode D1. Actually, as shown in fig. 15, the output signal is not directly connected to the output signal of the OUT terminal 114, but is connected to the output signal of the buffer 120. This is because the output signal of the buffer 120 has a large output current, and it is considered that the connection resistance R3 hardly affects the driving of the IGBT 12.

With such a connection, when the IGBT12 is in an OFF (OFF) state, it is considered that the non-inverting input terminal of the comparator IC1 can be maintained at a Low (Low) level, and a circuit having high resistance to noise can be configured.

4.3 detailed description of the invention

Fig. 16 shows a circuit diagram of a gate driver circuit 700 as a third embodiment of the invention. A different aspect from the gate driver circuit 600 of fig. 15 is an aspect in which the resistor R6 is provided. The resistance R6 can provide a circuit with further improved resistance to noise.

5. Effects, modifications and others

As described above, according to the present embodiment, the following gate driver circuit can be provided: the shielding time after occurrence of an abnormality can be maintained at a constant value, and the resistance to noise is improved, thereby enabling stable detection of the occurrence of an obstacle.

The embodiments described above are examples of means for implementing the present invention, and the present invention should be appropriately modified or changed depending on the configuration of an apparatus to which the present invention is applied and various conditions, and the present invention is not limited to the embodiments of the present invention. For example, although the IGBT has been mainly described as the power Semiconductor switch to be driven in the above embodiment, the present invention is also applicable to a gate drive circuit for driving another power Semiconductor switch (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)). In the embodiments and examples described above, the gate driver 110 and its accompanying individual elements and circuit configurations have been described, but an IC, a Large-Scale integrated circuit (LSI), or the like may be used.

Industrial applicability

Description of the symbols

10. 110: gate driver

12：IGBT

14. 114: OUT terminal

16. 116: inverter with a voltage regulator

18. 118: comparator with a comparator circuit

100. 200, 300, 400, 500, 600, 700: gate drive circuit

120: buffer device

130: time measuring circuit

132: comparison circuit

C1, C2, C3: capacitor with a capacitor element

CMP1, CMP2, IC 1: comparator with a comparator circuit

D1, D2, D3, D4: diode with a high-voltage source

Rb, R1, R2, R3, R4, R5, R6: resistance (RC)

Q1, Q2: transistor with a metal gate electrode

Claims

1. A gate drive circuit for driving a power semiconductor switch, comprising:

a comparison circuit for comparing a collector-emitter voltage of the power semiconductor switch with a predetermined threshold voltage; and

a time measurement circuit that starts measuring time after the comparison circuit detects that the collector-emitter voltage exceeds the threshold voltage, and

the gate driving circuit includes:

and an output circuit that outputs an abnormal signal indicating that the power semiconductor switch is in an abnormal state after the time measurement circuit measures the standby retention time.

2. The gate drive circuit of claim 1,

the comparator circuit increases a collector current due to a predetermined fault or abnormality immediately after the power semiconductor switch is turned from an off operation to an on operation or in a state where the power semiconductor switch is in a saturated state, and compares the collector-emitter voltage with the predetermined threshold voltage when the power semiconductor switch is in a desaturated state.

3. A gate drive circuit according to claim 1 or 2,

the abnormal signal means a signal in which the power semiconductor switch is in a desaturated state when a predetermined output signal changes to a predetermined value.

4. The gate drive circuit according to any one of claims 1 to 3,

the time measurement circuit includes:

a charging capacitor to which a charging current of a constant current value is applied, the charging capacitor being configured to set a standby retention time to a time until an inter-terminal voltage of the capacitor increases to a predetermined voltage value in association with charging; and

a charging current bypass circuit configured to bypass a current of the constant charging current value when the power semiconductor switch is in a saturation state and the collector-emitter voltage is equal to or less than the threshold voltage of the comparator, and set the initial charge of the charging capacitor to 0 without causing a charging current to flow into the charging capacitor,

the comparator circuit blocks the charging current bypass circuit and causes the constant charging current value to flow into the capacitor from a state where the initial charge of the capacitor is 0, when the power semiconductor switch is in a desaturated state and it is detected that the collector-emitter voltage exceeds the threshold voltage of the comparator circuit.

5. A gate drive circuit as claimed in claim 4,

when a delay time is generated until the power semiconductor switch actually turns on after a signal for causing the power semiconductor switch to be driven to transition from an off state to an on state is output,

the method comprises the following steps: a first initial charge charging circuit for generating the standby retention time by making an initial charge remain in the charging capacitor to a degree that the charging time of the initial charge is shortened,

the output circuit outputs an abnormal signal indicating that the power semiconductor switch is in a desaturated state after the time measuring circuit measures the short standby retention time.

6. A gate drive circuit as claimed in claim 4,

the charging current bypass circuit includes:

a bypass switch for bypassing the charging current, and a series circuit of an initial charge resistor directly connected to the bypass switch,

even when the charging current is bypassed by the charging current bypass circuit, the standby retention time is shortened by the charging time of the initial charge by causing the initial charge to remain in the charging capacitor to the extent of the initial charge resistance,

7. A gate drive circuit according to any one of claims 1 to 6, comprising:

a diode having a cathode terminal connected to the comparison circuit and an anode terminal connected to a collector terminal of the power semiconductor switch,

the comparison circuit detects a collector voltage of the power semiconductor switch via the diode.