CN114650246A

CN114650246A - Detection method, device and equipment for IP core calling

Info

Publication number: CN114650246A
Application number: CN202011508063.XA
Authority: CN
Inventors: 杜玉欣; 李男; 王大鹏; 张欣旺; 黄宇红; 丁海煜; 胡臻平; 武欣
Original assignee: China Mobile Communications Group Co Ltd; China Mobile Communications Ltd Research Institute
Current assignee: China Mobile Communications Group Co Ltd; China Mobile Communications Ltd Research Institute
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2022-06-21

Abstract

The invention provides a method, a device and equipment for detecting IP core calling, belonging to the technical field of communication, wherein the method comprises the following steps: determining whether to call an IP core and/or suspected to call the IP core in a target chip and/or the information of the target chip according to the first information; and/or determining the information of the target chip and/or the target chip according to the second information, and calling and/or suspected calling IP cores; the information of the target chip is one kind of information or a plurality of kinds of information. The invention improves the accuracy and the reliability of the detection of the calling condition of the IP core.

Description

Detection method, device and equipment for IP core calling

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, and a device for detecting an IP core call.

Background

The chip design is the core and source of the chip industry chain, and the autonomous controllability of the chip design plays a significant role in the autonomous controllability of the whole chip.

With the gradual expansion of chip scale, the chip design will be assisted and integrated with some mature Intellectual Property cores (IP cores) to reduce the design time and improve the efficiency. Therefore, the autonomous condition of the IP core is an important judgment index of the autonomous controllability of the chip design.

However, the accuracy and reliability of current IP core detection methods are limited.

Disclosure of Invention

In view of this, the present invention provides a method, an apparatus, and a device for detecting an IP core call, which are used to solve the problem that the accuracy and the reliability of the current chip IP core checking method are limited.

In order to solve the above technical problem, in a first aspect, the present invention provides a method for detecting an IP core call, including:

determining whether to call an IP core and/or suspected to call the IP core in a target chip and/or the information of the target chip according to the first information; and/or the presence of a gas in the gas,

according to the second information, determining the target chip and/or the information of the target chip, and calling and/or suspected calling IP cores;

the information of the target chip is one kind of information or a plurality of kinds of information.

In a second aspect, the present invention further provides a device for detecting an IP core call, including:

the IP core calling judging module is used for determining whether to call the IP core and/or suspected to call the IP core in the target chip and/or the information of the target chip according to the first information; and/or the presence of a gas in the gas,

the IP core calling determining module is used for determining the information of the target chip and/or the target chip according to second information and calling and/or suspected calling IP cores;

Optionally, the target chip is a whole or partial chip, and the types of the chips include, but are not limited to, one or more of the following: packaged chips, unpackaged dies, modules in dies, units in dies have been completed.

Optionally, the first information is the same as or different from the second information.

Optionally, the first information includes a chip design layout and/or a design layout, and/or a chip entity and/or an entity layout;

the IP core calls the judging module, including but not limited to one or more of the following:

the first judgment submodule is used for a chip design layout and/or a design layout, and if a blank area and/or a blank area is larger than or equal to a first preset threshold and/or a blank area occupation ratio is larger than or equal to a second preset threshold and/or a blank area is a regular geometric figure, an IP core is determined to be called in the target chip and/or information of the target chip and/or the IP core is suspected to be called; the blank area occupation ratio refers to a ratio of blank areas occupying the design layout and/or design placement and/or design layout, and the regular geometric figures include, but are not limited to, one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc;

A second judgment sub-module, configured to compare the chip design layout and/or layout of a corresponding chip real object and/or layout of a real object, and if the comparison is not consistent, determine that an IP core is called and/or an IP core is suspected to be called in the target chip and/or in the information of the target chip, where the comparison is inconsistent, but not limited to, one or more of the following cases: all layers and/or a part of layers and/or a layer are not in consistent alignment; the whole area and/or a plurality of local areas and/or one local area in all layers and/or part layers and/or one layer are not consistent in comparison;

a third judgment sub-module, configured to determine that an IP core is called and/or an IP core is suspected to be called in the target chip and/or the information of the target chip if a first identifier exists in the chip design layout and/or the chip physical layout and/or the physical layout; the first mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

A fourth judging submodule, configured to determine that an IP core is called and/or an IP core is suspected to be called in the information of the target chip and/or the target chip if a second identifier exists in the chip design layout and/or the design layout pattern, and/or the chip real object and/or the real object layout pattern; the second identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

a fifth judging submodule, configured to compare the chip design layout and/or design layout with a layout and/or layout in a first preset library, and if a first region in the chip design layout and/or design layout is the same as and/or similar to and/or has a similarity greater than or equal to a third preset threshold with a second region in the layout and/or layout in the first preset library, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core; the first preset library does not contain a layout and/or a wiring layout of the design company of the target chip;

A sixth judgment sub-module, configured to compare the chip design layout and/or design layout pattern with a layout and/or layout pattern in a second preset library, and if a third region in the chip design layout and/or design layout pattern is the same as and/or similar to and/or greater than or equal to a fourth preset threshold, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core; the second preset library is a layout and/or a wiring layout pattern designed for the design company of the target chip, and/or a layout and/or a wiring layout pattern IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

a seventh judging submodule for making the chip real object and/or real object layout and/or layout and layout patterns, comparing the chip layout, the same and/or similar and/or similarity degree with the sixth area of the layout and/or place-and-route pattern in the third preset library is larger than or equal to a fifth preset threshold, determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core; the third preset library does not contain the layout and/or the wiring layout diagram designed by the design company of the target chip;

An eighth judging submodule, configured to arrange the chip in real objects and/or in real object layouts, comparing with the layout and/or layout of the chip in the seventh area of the real object and/or real object layout and/or layout of the chip in the fourth preset library, the same and/or similar and/or similarity degree with the eighth area of the layout and/or place-and-route pattern in the fourth preset library is larger than or equal to a sixth preset threshold, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip; and the fourth preset library is a layout and/or a wiring layout diagram designed for the design company of the target chip, and/or a layout and/or a wiring layout diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip.

Optionally, the first information includes a schematic diagram of the chip, and/or a chip design layout and/or a design layout;

The IP core call judging module includes, but is not limited to, one or more of the following:

a ninth determining sub-module, configured to determine that an IP core is called and/or an IP core is suspected to be called in the target chip and/or in the information of the target chip if a third identifier exists in the schematic diagram of the chip; the third mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

a tenth determining sub-module, configured to determine that an IP core and/or a suspected IP core is called in the target chip and/or in the information of the target chip if a fourth identifier exists in the schematic diagram of the chip; the fourth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

an eleventh judging sub-module, configured to compare the schematic diagram of the chip with a schematic diagram in a fifth preset library, and if a ninth area in the schematic diagram of the chip is the same as and/or similar to a tenth area in the schematic diagram in the fifth preset library and/or a similarity degree is greater than or equal to a seventh preset threshold, determine that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the fifth preset library does not contain a schematic diagram designed by a design company of the target chip;

A twelfth judgment sub-module, configured to compare the schematic diagram of the chip with a schematic diagram in a sixth preset library, and if an eleventh area in the schematic diagram of the chip is the same as and/or similar to a twelfth area in the schematic diagram in the sixth preset library and/or a similarity of the eleventh area and the twelfth area is greater than or equal to an eighth preset threshold, determine that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the sixth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

a thirteenth judging submodule, configured to perform one or more LVS verifications using one or more LVS verification software and/or tools and/or environments for the schematic diagram of the chip and the chip design layout and/or design layout diagram, and if the one or more LVS verifications fail, determine that the IP core is called by the information of the target chip and/or the IP core is suspected to be called;

and a fourteenth judging submodule, configured to modify one or a part of or all names of the modules and/or cells according to the schematic diagram of the chip and the chip design layout and/or layout diagram, perform one or more times of LVS verification using one or more types of LVS verification software and/or tools and/or environments after the modification, and if the one or more times of LVS verification fails, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core.

Optionally, the first information includes a netlist of a chip transistor level, and/or a chip design layout and/or a design place and route pattern; the transistor-level netlist includes, but is not limited to, one or more of the following: the analog-digital mixed chip is composed of a transistor-level netlist corresponding to an analog module schematic diagram and/or a transistor-level netlist corresponding to a digital module-finished gate-level netlist of the final design;

a fifteenth determining sub-module, configured to determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core if a fifth identifier exists in the chip transistor-level netlist; the fifth mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

A sixteenth judging submodule, configured to determine that the target chip and/or the information of the target chip invokes an IP core and/or is suspected to invoke an IP core if a sixth identifier exists in the netlist of the chip transistor level; the sixth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

a seventeenth judging submodule, configured to compare the netlist of the chip transistor level with the netlist of the transistor level in a seventh preset library, and if a first part of the netlist of the chip transistor level is the same as a second part of the netlist of the transistor level in the seventh preset library and/or is similar to the second part of the netlist of the transistor level in the seventh preset library and/or has a similarity greater than or equal to a ninth preset threshold, determine that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; the seventh preset library does not contain a transistor-level netlist designed by a design company of the target chip;

an eighteenth judgment sub-module, configured to compare the netlist of the chip transistor level with the netlist of the transistor level in an eighth preset library, and if a third part of the netlist of the chip transistor level is the same as and/or similar to a fourth part of the netlist of the transistor level in the eighth preset library and/or the similarity is greater than or equal to a tenth preset threshold, determine that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; a transistor-level netlist designed for a design company of the target chip, and/or a transistor-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the eighth preset library;

A nineteenth judgment sub-module, configured to perform, for the netlist of the chip transistor level and the chip design layout and/or design layout pattern, one or more LVS verifications by using one or more LVS verification software and/or tools and/or environments for one or more times, and if one or more LVS verifications fail, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

and a twentieth judgment sub-module, configured to modify one or some of the numbers or names of all of the modules and/or cells according to the netlist of the chip transistor level and the chip design layout and/or layout and to perform one or more LVS verifications in one or more LVS verification software and/or tools and/or environments after the modification, and if one or more LVS verifications fail, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core.

Optionally, the first information includes a gate-level netlist of the chip, and/or a chip design layout and/or a design place and route pattern; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip register transmission level RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process are finished; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

a twenty-first judging sub-module, configured to determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core if a seventh identifier exists in the gate-level netlist of the chip; the seventh mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

a twenty-second judgment sub-module, configured to determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core if an eighth identifier exists in the gate-level netlist of the chip; the eighth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

a twenty-third judgment sub-module, configured to compare the gate-level netlist of the chip with a gate-level netlist in a ninth preset library, and if a fifth part of the gate-level netlist of the chip is the same as and/or similar to a sixth part of the gate-level netlist in the ninth preset library and/or the similarity is greater than or equal to an eleventh preset threshold, determine that the target chip and/or the information of the target chip call an IP core and/or is suspected to call an IP core; the ninth preset library does not contain a gate-level netlist designed by a design company of the target chip;

A twenty-fourth judging sub-module, configured to compare the gate-level netlist of the chip with a gate-level netlist in a tenth preset library, and if a seventh part of the gate-level netlist of the chip is the same as an eighth part of the gate-level netlist in the tenth preset library and/or similar to the eighth part of the gate-level netlist in the tenth preset library and/or the similarity is greater than or equal to a twelfth preset threshold, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core; a gate-level netlist designed for a design company of the target chip, and/or a gate-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the tenth preset library;

a twenty-fifth judging submodule, configured to perform one or more LVS verifications for the gate-level netlist of the chip and the chip design layout and/or design layout pattern using one or more LVS verification software and/or tools and/or environments, and if one or more LVS verifications fail, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

A twenty-sixth judgment sub-module, configured to modify one or some of the numbers or names of all of the modules and/or units according to the gate-level netlist of the chip and the chip design layout and/or design layout, perform one or more LVS verifications in one or more types of LVS verification software and/or tools and/or environments after the modification, and if one or more LVS verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

a twenty-seventh judging submodule, configured to convert the gate-level netlist of the chip into a chip-transistor-level netlist, perform one or more LVS verifications for the converted chip-transistor-level netlist and the chip design layout and/or design layout pattern using one or more LVS verification software and/or tools and/or environments, and if the one or more LVS verifications fail, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

A twenty-eighth judging submodule, configured to, after converting a gate-level netlist of a chip into a chip-transistor-level netlist, modify one or a part of the number of netlist or names of all modules and/or cells with respect to the converted chip-transistor-level netlist and the chip design layout and/or layout pattern, and perform one or more LVS verifications in one or more LVS verification software and/or tools and/or environments after the modification, and if one or more LVS verifications do not pass, determine that the information of the target chip and/or the target chip calls an IP core and/or calls a suspected IP core;

a twenty-ninth judgment sub-module, configured to modify one or some number of the modules and/or names of all the modules and/or units according to the gate-level netlist of the chip and the chip design layout and/or layout, convert the modified gate-level netlist into a chip-transistor-level netlist, perform one or more LVS verifications in one or more LVS verification software and/or tools and/or environments according to the converted chip-transistor-level netlist and the modified chip design layout and/or design layout, and if one or more LVS verifications fail, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip;

A thirtieth judgment sub-module, configured to perform one or more formal verifications using one or more formal verification software and/or tools and/or environments for two gate-level netlists of a chip, and if the one or more formal verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core;

a thirty-first judging submodule, configured to modify one or a part of the numbers of the two types of gate-level netlists of the chip or names of all the modules and/or units, and perform one or more types of formal verification using one or more types of formal verification software and/or tools and/or environments after the modification, and if the one or more types of formal verification fail, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

when the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the two gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

Optionally, the first information includes a chip RTL code, and/or a gate-level netlist of the chip; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

the IP core calling judging module includes but is not limited to one or more of the following:

a thirty-second judgment sub-module, configured to determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core if a ninth identifier exists in the chip RTL code; the ninth mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

a thirty-third determining sub-module, configured to determine that the target chip and/or the information of the target chip invokes an IP core and/or is suspected to invoke an IP core if a tenth identifier exists in the chip RTL code; the tenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

A thirty-fourth judging sub-module, configured to determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core if other level descriptions except the register transfer level description exist in the chip RTL code; the other level descriptions besides register transfer level description include but are not limited to gate level descriptions; the thirty-fourth judgment sub-module is further configured to check whether there are other level descriptions besides the register transfer level description in the chip RTL code, where the thirty-fourth judgment sub-module includes, but is not limited to, one or more of the following: the first retrieval unit is used for performing keyword retrieval on the chip RTL code; the first comparison unit is used for comparing the chip RTL code with the gate-level netlist of the chip, and if the ninth part of the chip RTL code is the same as the tenth part of the gate-level netlist of the chip and/or is similar to the tenth part of the gate-level netlist of the chip and/or the similarity is greater than or equal to a thirteenth preset threshold, determining that other level descriptions except the register transmission level description exist in the chip RTL code; wherein the first retrieval unit includes, but is not limited to, one or more of the following: the first retrieval subunit is used for retrieving the RTL code by using one or more keywords representing other level descriptions except the register transmission level description, and if the one or more keywords exist in the RTL code and/or the total quantity of the one or more keywords existing in the RTL code is greater than or equal to a fourteenth preset threshold and/or the proportion of the total quantity of the one or more keywords existing in the RTL code occupying the whole RTL code word quantity is greater than or equal to a fifteenth preset threshold, determining that other level descriptions except the register transmission level description exist in the chip RTL code; the second retrieval subunit is used for retrieving the RTL code by using one or more keywords representing the register transmission level description, and if various keywords are found not to exist in the RTL code and/or one or more keywords do not exist in the RTL code, determining that other level descriptions except the register transmission level description exist in the chip RTL code; the categories of the keywords include, but are not limited to, one or more of the following: code at a representation description level, words and/or phrases at a representation description level, scripts at a representation description level, programs at a representation description level, RTL code at a representation description level, a netlist at a representation description level, wherein the netlist includes but is not limited to a gate-level netlist;

A thirty-fifth judging sub-module, configured to compare the chip RTL code with an RTL code in an eleventh preset library, and if an eleventh part of the chip RTL code is the same as a twelfth part of the RTL code in the eleventh preset library and/or is similar to the eleventh preset library and/or has a similarity greater than or equal to a sixteenth preset threshold, determine that the target chip and/or the information of the target chip has called an IP core and/or is suspected to call an IP core; the eleventh preset library does not contain RTL codes designed by a design company of the target chip;

a thirty-sixth judgment sub-module, configured to compare the chip RTL code with an RTL code in a twelfth preset library, and if a thirteenth part of the chip RTL code is the same as and/or similar to a fourteenth part of the RTL code in the twelfth preset library and/or has a similarity greater than or equal to a seventeenth preset threshold, determine that the target chip and/or the information of the target chip call an IP core and/or is suspected to call an IP core; the twelfth preset library is an RTL code designed for the design company of the target chip, and/or an RTL code IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

A thirty-seventh judging sub-module, configured to perform one or more formal verifications using one or more formal verification software and/or tools and/or environments for the RTL code of the chip and the gate-level netlist of the chip, and if the one or more formal verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

a thirty-eighth judging submodule, configured to modify one or a part of the number of the RTL codes of the chip and the gate-level netlist of the chip or names of all the modules and/or units, and perform one or more formal verifications in one or more formal verification software and/or tools and/or environments after the modification, and if any one or more formal verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core;

when formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the RTL code and the gate-level netlist, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

Optionally, the second information includes a chip design layout and/or a design layout pattern, and/or a chip entity and/or an entity layout pattern;

the IP core call determination module includes, but is not limited to, one or more of the following:

a first determining submodule, for determining blank regions in the chip design layout and/or design layout pattern, and/or blank regions with an area greater than or equal to an eighteenth preset threshold, and/or blank regions with an occupation ratio greater than or equal to a nineteenth preset threshold, and/or blank regions of regular geometric figures, and connecting the blank regions, and/or the design layout pattern corresponding to the blank area, and/or the module and/or the unit and/or the design information corresponding to the blank area are determined as the IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the occupation ratio refers to the proportion of the blank areas occupying the design layout and/or design layout, and the regular geometric figures include but are not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc; the blank area includes, but is not limited to, one or more areas;

A second determining submodule, configured to determine a mismatch between a chip design layout and/or a comparison between a chip real object and/or a real object layout and/or a comparison between the chip design layout and/or the design layout corresponding to the mismatch, and/or a chip real object and/or a real object layout and/or a layout corresponding to the mismatch, and/or a module and/or a unit and/or design information corresponding to the mismatch to call and/or suspect call the target chip and/or the target chip information An IP core for use; wherein the inconsistency includes, but is not limited to, one or more of the following: all layers and/or part of layers and/or one layer are inconsistent in comparison; all layers and/or part layers and/or one layer, wherein the whole area and/or a plurality of local areas and/or one local area are inconsistent in comparison; the inconsistency place includes but is not limited to one or more places of layout and/or place-route patterns;

A third determining submodule, configured to determine a position where an eleventh identifier is located and/or a region where the eleventh identifier is located and/or a distance between the eleventh identifier and the chip entity and/or the chip entity layout, and/or determine a module and/or a unit and/or design information corresponding to the position and/or the region and/or the eleventh identifier as an IP core for which information call and/or suspected call of the target chip and/or the target chip is/are/is/are/is configured;

a fourth determining submodule, configured to determine, after determining a position of an eleventh identifier and/or a region of the eleventh identifier and/or a distance from the eleventh identifier to a twenty-first preset threshold in a chip design layout and/or a design layout diagram, and/or a physical layout diagram, and/or determining a module and/or a cell and/or design information corresponding to the position and/or the region of one or more layers, and/or the position and/or the region of the one or more layers as the target chip and/or the unit and/or the design information corresponding to the eleventh identifier The IP core is called and/or suspected to be called by the information of the target chip; wherein the twenty-first preset threshold is the same as or different from the twentieth preset threshold;

Wherein the eleventh identifier is an identifier of a company other than the design company of the target chip and/or an identifier representing a company other than the design company of the target chip;

a fifth determining submodule, configured to determine a chip design layout and/or a design layout pattern, and/or a chip real object and/or a real object layout pattern, where a twelfth identifier is located, and/or a region where a distance from the twelfth identifier is less than or equal to a twenty-second preset threshold, and/or a module and/or a unit and/or an IP core, for which design information is called and/or suspected to be called, of the information of the target chip and/or the target chip, and/or the module and/or the unit and/or the design information corresponding to the position and/or the region and/or the twelfth identifier;

a sixth determining submodule, configured to determine, after determining a position where a twelfth tag is located and/or a region where a distance from the twelfth tag is less than or equal to a twenty-third preset threshold in a chip design layout and/or a design layout, and/or a real object of the chip and/or a real object layout, and/or determining a module and/or a cell and/or design information corresponding to the position and/or the region of one or more layers, and/or the position and/or the region of the one or more layers as the target chip and/or the unit and/or the design information corresponding to the position and/or the region of the one or more layers The IP core is called and/or suspected to be called by the information of the target chip; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold;

Wherein the twelfth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

a seventh determining submodule, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a cell and/or design information corresponding to a fourteenth region and/or a fourteenth region in the chip design layout and/or design layout, and/or design information corresponding to a thirteenth region, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-fourth preset threshold, of the layout and/or layout pattern in a thirteenth preset library; the thirteenth preset library does not contain the layout and/or layout wiring diagram designed by the design company of the target chip;

an eighth determining submodule, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a cell and/or design information corresponding to a sixteenth region and/or a sixteenth region in the chip design layout and/or design layout, where the fifteenth region is the same as, and/or similar to, and/or has a similarity greater than or equal to a twenty-fifth preset threshold with respect to the layout and/or layout in a fourteenth preset library; the fourteenth preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring and/or layout and wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

A ninth determining submodule, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to an eighteenth area and/or eighteenth area in the chip real object and/or real object layout diagram, where the module and/or unit and/or design information is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-sixth preset threshold with respect to a seventeenth area in the layout and/or layout diagram in a fifteenth preset library; the fifteenth preset library does not contain the layout and/or the wiring and/or the layout and wiring diagram designed by the design company of the target chip;

a tenth determining submodule, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to a twentieth region and/or twentieth region in the chip physical and/or physical layout and/or layout diagram, where the module and/or unit and/or design information is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-seventh preset threshold with respect to a nineteenth region in the layout and/or layout diagram in a sixteenth preset library; the sixteenth preset library is a layout and/or a wiring layout pattern designed for the design company of the target chip, and/or a layout and/or a wiring layout pattern IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

An eleventh determining submodule, configured to determine a position and/or a region of a chip real object and/or a real object layout and/or a layout of an IP core called and/or suspected to be called as the target chip and/or the target chip, and/or a module and/or a unit and/or design information corresponding to the position and/or the region, and determining the position and/or area of the corresponding chip design layout and/or design information, and/or the module and/or unit and/or design information corresponding to the position and/or area as the IP core called and/or suspected called by the information of the target chip and/or the target chip.

Optionally, the second information includes a schematic diagram of the chip, and/or a chip design layout and/or a design layout diagram;

a twelfth determining submodule, configured to determine a position where a thirteenth identifier is located in the schematic diagram of the chip and/or an area where the thirteenth identifier is located and/or an area where a distance from the thirteenth identifier to the thirteenth identifier is smaller than or equal to a twenty-eighth preset threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the area and/or the thirteenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the thirteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

A fourteenth determining sub-module, configured to determine a location of a fourteenth identifier in a schematic diagram of the chip, and/or an area where the fourteenth identifier is located, and/or an area where a distance from the fourteenth identifier to the fourteenth identifier is smaller than or equal to a twenty-ninth preset threshold, and/or a module and/or a unit and/or design information corresponding to the location and/or the area and/or the fourteenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the fourteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

a fifteenth determining sub-module, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twenty-second area and/or a twenty-second area in the schematic diagram of the chip that is the same as and/or similar to a twenty-first area of the schematic diagram in a seventeenth preset library and/or has a similarity greater than or equal to a thirty-first preset threshold; the seventeenth preset library does not contain a schematic diagram designed by a design company of the target chip;

a sixteenth determining sub-module, configured to determine, as the IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a unit and/or design information that is the same as and/or similar to a twenty-third area of a schematic diagram in an eighteenth preset library and/or has a similarity greater than or equal to a thirty-first preset threshold and corresponds to a twenty-fourth area and/or a twenty-fourth area in the schematic diagram of the chip; the eighteenth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

A seventeenth determining submodule, configured to determine, according to a schematic diagram of a chip and a chip design layout and/or a design layout diagram, a result and/or a report of failed LVS verification in one or more times of LVS verification performed by using one or more types of LVS verification software and/or tools and/or environments, an IP core for information call and/or suspected call of the target chip and/or the target chip; the seventeenth determination submodule includes, but is not limited to, one or more of: a first determining unit, configured to determine an IP core that is called and/or suspected to be called for information of the target chip and/or the target chip by a module and/or a unit and/or design information corresponding to a failed schematic area, and/or a failed chip design layout and/or design layout pattern area, and/or a failed area in verification; a second determining unit, configured to determine a difference between the devices and/or connection relationships in the schematic diagram found in the verification and the device and/or connection relationships in the chip design layout and/or design layout diagram, and/or a schematic diagram area corresponding to the difference, and/or a chip design layout and/or design layout diagram area, and/or a module, and/or a cell, and/or design information, and call and/or suspect-to-call an IP core for information of the target chip and/or the target chip;

An eighteenth determining submodule, configured to determine, according to the schematic diagram of the chip and the chip design layout and/or design layout diagram, after modifying one or a part of the number of modules and/or all of the names of the modules and/or cells, an IP core for information call and/or suspected call of the target chip and/or the target chip in one or more times of LVS verification using one or more types of LVS verification software and/or tools and/or environments, and a result and/or report of failed LVS verification; the eighteenth determining submodule includes, but is not limited to, one or more of: a third determining unit, configured to determine an IP core that is called and/or suspected to be called for the information of the target chip and/or the target chip by a module and/or a unit and/or design information corresponding to a failed schematic area, and/or a failed chip design layout and/or design layout pattern area, and/or a failed area in the verification; a fourth determining unit, configured to determine the device and/or connection relationship in the schematic diagram found in the verification, a schematic diagram region corresponding to the difference and/or the difference between the device and/or connection relationship in the chip design layout and/or design layout, and/or a chip design layout and/or design layout region, and/or a module, and/or a cell, and/or design information, and invoke and/or suspect-to-invoke IP core for the information of the target chip and/or the target chip.

Optionally, the second information includes a netlist of a chip transistor level, and/or a chip design layout and/or a design placement wiring diagram; the transistor-level netlist includes, but is not limited to, one or more of the following: the analog-digital mixed chip is composed of a transistor-level netlist corresponding to an analog module schematic diagram and/or a transistor-level netlist corresponding to a digital module-finished gate-level netlist of the final design;

a nineteenth determining sub-module, configured to determine a position where a fifteenth identifier is located in the netlist of the chip transistor level and/or a portion where the fifteenth identifier is located and/or a portion where a code length between the fifteenth identifier and the fifteenth identifier is less than or equal to a thirty-second preset threshold and/or a portion where an occupation ratio of a code length between the fifteenth identifier and the fifteenth identifier in the netlist of the chip transistor level is less than or equal to a first proportional threshold, and/or an IP core called and/or suspected to be called by the module and/or unit and/or design information corresponding to the position and/or the portion and/or the fifteenth identifier for the information of the target chip and/or the target chip; the fifteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

A twentieth determining submodule, configured to determine a position where a sixteenth identifier is located in the netlist of the chip transistor level and/or a portion where the sixteenth identifier is located and/or a portion where a code length between the sixteenth identifier and the sixteenth identifier is smaller than or equal to a thirty-third preset threshold and/or a portion where a ratio of the code length between the sixteenth identifier and the netlist of the chip transistor level is smaller than or equal to a second ratio threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the portion and/or the sixteenth identifier is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; the sixteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

a twenty-first determining sub-module, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a sixteenth part and/or a sixteenth part in the netlist of the chip transistor level, where the module and/or the unit and/or the design information are the same as and/or similar to a fifteenth part of the netlist of the transistor level in the nineteenth preset library and/or have a similarity greater than or equal to a thirty-fourth preset threshold; the nineteenth preset library does not contain a transistor-level netlist designed by a design company of the target chip;

A twenty-second determining sub-module, configured to determine, as the IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to an eighteenth part and/or an eighteenth part in the netlist of the chip transistor level, where the module and/or the unit and/or the design information are the same as and/or similar to and/or have a similarity greater than or equal to a thirty-fifth preset threshold with respect to a seventeenth part of the netlist of the transistor level in the twentieth preset library; a netlist of a transistor level designed for a design company of the target chip and/or a netlist IP core library of a transistor level of a design company of the target chip and/or an IP core library of a design company of the target chip in the twentieth preset library;

a twenty-third determining submodule, configured to determine, according to a netlist of a chip transistor level and a chip design layout and/or a design layout pattern, a result and/or a report of failed LVS verification in one or more times of LVS verification using one or more LVS verification software and/or tools and/or environments, an IP core for information call and/or suspected call of the target chip and/or the target chip; the twenty-third determination sub-module includes, but is not limited to, one or more of: a fifth determining unit, configured to determine that the IP core called and/or suspected to be called by the information of the target chip and/or the target chip is the module and/or the cell and/or the design information corresponding to the failed transistor-level netlist portion, and/or the failed chip design layout and/or the design layout pattern area, and/or the failed portion and/or the failed area in the verification; a sixth determining unit, configured to determine the device and/or connection relationship in the transistor-level netlist found in the verification, and the transistor-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or design layout, and/or the transistor-level netlist portion corresponding to the difference, and/or the IP core called and/or suspected to be called for the information of the target chip and/or the target chip;

A twenty-fourth determining submodule, configured to determine, according to the netlist of the chip transistor level and the chip design layout and/or design layout diagram, after modifying one or a part of the number of modules and/or names of all of the modules and/or cells, in one or more times of LVS verification using one or more types of LVS verification software and/or tools and/or environments, and a result and/or report of failed LVS verification, an IP core for information call and/or suspected call of the target chip and/or the target chip; the twenty-fourth determination submodule includes, but is not limited to, one or more of: a seventh determining unit, configured to determine an IP core called and/or suspected to be called for information of the target chip and/or the target chip by the module and/or cell and/or design information corresponding to the failed transistor-level netlist portion and/or the failed chip design layout and/or design layout pattern region and/or the failed portion and/or the failed region in the verification; and the eighth determining unit is used for determining the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference and/or the difference between the device and/or connection relation in the chip design layout and/or design layout-layout diagram, and/or the chip design layout and/or design layout-layout diagram area, and/or the module, and/or the cell, and/or the design information, and calling and/or suspected calling the IP core for the information of the target chip and/or the target chip.

Optionally, the second information includes a gate-level netlist of the chip, and/or a chip design layout and/or a design layout pattern; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

a twenty-fifth determining sub-module, configured to determine a position where a seventeenth identifier is located in a gate-level netlist of a chip and/or a portion where the seventeenth identifier is located and/or a portion where a code length between the seventeenth identifier and the seventeenth identifier is smaller than or equal to a thirty-sixth preset threshold and/or a portion where a ratio of the code length between the seventeenth identifier and the gate-level netlist of the chip is smaller than or equal to a third ratio threshold, and/or a module and/or a unit and/or a design information corresponding to the position and/or the portion and/or the seventeenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the seventeenth mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

A twenty-sixth determining sub-module, configured to determine a position where an eighteenth identifier is located in a gate-level netlist of a chip and/or a portion where a code length between the eighteenth identifier and the eighteenth identifier is smaller than or equal to a thirty-seventh preset threshold and/or a portion where a ratio of the code length between the eighteenth identifier and the gate-level netlist of the chip is smaller than or equal to a fourth ratio threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the portion and/or the eighteenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the eighteenth mark is a mark of a design company of the target chip and/or a mark of a design company representing the target chip;

a twenty-seventh determining sub-module, configured to determine, as the IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twentieth part and/or a twentieth part in the gate-level netlist of the chip, where the module and/or the unit and/or the design information are the same as and/or similar to and/or have a similarity greater than or equal to a thirty-eighth preset threshold with respect to a nineteenth part of the gate-level netlist in a twenty-first preset library; the twenty-first preset library does not contain a gate-level netlist designed by a design company of the target chip;

A twenty-eighth determining sub-module, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to a twenty-second part and/or a twenty-second part in the gate-level netlist of the chip, where the module and/or unit and/or design information is the same as and/or similar to a twenty-first part of the gate-level netlist in a twenty-second preset library and/or has a similarity greater than or equal to a thirty-ninth preset threshold; a gate-level netlist designed for a design company of the target chip, and/or a gate-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the twenty-second preset library;

a twenty-ninth determining submodule, configured to determine, according to a gate-level netlist of a chip and a chip design layout and/or design layout pattern, a result and/or a report of failed LVS verification in one or more LVS verifications performed using one or more LVS verification software and/or tools and/or environments, an IP core for information call and/or suspected call of the target chip and/or the target chip; the twenty-ninth determining sub-module includes, but is not limited to, one or more of: a ninth determining unit, configured to determine that the failed gate-level netlist portion in the verification, and/or the failed chip design layout and/or design layout pattern area, and/or the module and/or cell and/or design information corresponding to the failed portion and/or the failed area are/is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; a tenth determining unit, configured to determine the device and/or connection relationship in the gate-level netlist found in the verification, the gate-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or design layout, and/or the gate-level netlist portion corresponding to the difference, and/or the chip design layout and/or design placement and/or design layout area, and/or the module, and/or the cell, and/or the design information, and call and/or suspect-called IP cores for the information of the target chip and/or the target chip;

A thirtieth determining submodule, configured to determine, according to the gate-level netlist of the chip and the chip design layout and/or design layout pattern, after modifying one or a part of the number of modules and/or names of all of the modules and/or units, an IP core for information call and/or suspected call of the target chip in one or more times of LVS verification using one or more types of LVS verification software and/or tools and/or environments, and a result and/or report of failed LVS verification; the thirtieth determination sub-module includes, but is not limited to, one or more of the following: an eleventh determining unit, configured to determine an IP core called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or the cell and/or the design information corresponding to the failed gate-level netlist portion and/or the failed chip design layout and/or the design layout pattern region and/or the failed portion and/or the failed region in the verification; a twelfth determining unit, configured to determine a difference between the device and/or connection relationship in the gate-level netlist found in the verification and the device and/or connection relationship in the chip design layout and/or design placement and/or layout, and/or a gate-level netlist portion corresponding to the difference, and/or a chip design layout and/or design placement and/or layout area, and/or a module, and/or a cell, and/or design information, and call and/or suspect-to-call an IP core for information of the target chip and/or the target chip;

A thirty-first determining submodule, configured to determine, after converting the gate-level netlist of the chip into a chip-transistor-level netlist, an IP core for information call and/or suspected call of the target chip and/or the target chip in the converted chip-transistor-level netlist and the chip design layout and/or design layout pattern, in performing one or more LVS verifications using one or more LVS verification software and/or tools and/or environments, and in performing a non-passing LVS verification result and/or report; the thirty-first determination submodule includes, but is not limited to, one or more of: a thirteenth determining unit, configured to determine an IP core called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or cell and/or design information corresponding to the failed transistor-level netlist portion and/or the failed chip design layout and/or design layout area, and/or the failed portion and/or the failed area; a fourteenth determining unit, configured to determine the device and/or connection relationship in the transistor-level netlist found in the verification, the transistor-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or layout, and/or the gate-level netlist portion corresponding to the difference, and/or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and/or the corresponding chip design layout and/or design placement and layout area, and/or module, and/or cell, and/or design information, and invoke and/or suspect-to-invoke IP cores for the information of the target chip and/or the target chip;

A thirty-second determining submodule, configured to determine, after the gate-level netlist of the chip is converted into the chip-transistor-level netlist, the converted chip-transistor-level netlist, the chip design layout and/or design layout diagram, after one or a part of the number of the converted netlist and the names of all the modules and/or cells are modified, in one or more LVS verifications performed using one or more LVS verification software and/or tools and/or environments, a result and/or a report of a failed LVS verification, an IP core for information call and/or suspected call of the target chip and/or the target chip; the thirty-second determination sub-module includes, but is not limited to, one or more of: a fifteenth determining unit, configured to determine an IP core called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or cell and/or design information corresponding to the failed transistor-level netlist portion and/or the failed chip design layout and/or design layout area, and/or the failed portion and/or the failed area; a sixteenth determining unit, configured to determine the device and/or connection relationship in the transistor-level netlist found in the verification, the transistor-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or layout, and/or the gate-level netlist portion corresponding to the difference, and/or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and/or the corresponding chip design layout and/or design placement and layout area, and/or module, and/or cell, and/or design information, and call and/or suspect-called IP cores for the information of the target chip and/or the target chip;

A thirty-third determining submodule, configured to modify one or a part of the number of the modules and/or the names of all the modules and/or cells according to the gate-level netlist of the chip and the chip design layout and/or design layout-layout diagram, and then convert the modified gate-level netlist into a transistor-level netlist of the chip, determining the IP core of the target chip and/or the information calling and/or suspected calling of the target chip by using the converted netlist of the chip transistor level and the modified chip design layout and/or design layout diagram to perform one or more LVS verification in one or more LVS verification software and/or tools and/or environments and to obtain the result and/or report of the failed LVS verification; the thirty-third determination sub-module includes, but is not limited to, one or more of: a seventeenth determining unit, configured to determine an IP core called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or cell and/or design information corresponding to the failed transistor-level netlist portion and/or the failed transistor-level netlist portion in the verification, and/or the failed chip design layout and/or design layout area, and/or the failed portion and/or the failed area; an eighteenth determining unit, configured to determine the device and/or connection relationship in the transistor-level netlist found in the verification, the transistor-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or layout, and/or the gate-level netlist portion corresponding to the difference, and/or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and/or the corresponding chip design layout and/or design placement and layout area, and/or module, and/or cell, and/or design information, and call and/or suspect-called IP cores for the information of the target chip and/or the target chip;

A thirty-fourth determining submodule, configured to determine, according to two gate-level netlists of a chip, an IP core that is called and/or suspected to be called by information of the target chip and/or the target chip in one or more formal verification processes using one or more formal verification software and/or tools and/or environments and/or a result and/or a report of a failed formal verification process; the thirty-fourth determination sub-module includes, but is not limited to, one or more of: a nineteenth determining unit, configured to determine a gate-level netlist portion that fails in verification, and/or a module and/or a unit and/or design information corresponding to the failed portion as an IP core that is called and/or suspected to be called by the target chip and/or the information of the target chip; a twentieth determining unit, configured to determine that the gate-level netlist portion corresponding to the mismatch point found in the verification, and/or the module and/or unit and/or design information corresponding to the portion and/or mismatch point is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a twenty-first determining unit, configured to determine an inequivalent portion found in verification, and/or a gate netlist portion corresponding to the inequivalent portion, and/or a module and/or a unit and/or design information corresponding to the inequivalent portion as an IP core for information call and/or suspected call of the target chip and/or the target chip; a twenty-second determining unit, configured to determine that a difference between logic and/or functions in two gate-level netlists found in the verification and/or a gate-level netlist portion, and/or a module and/or a unit and/or design information corresponding to the difference are/is an IP core called and/or suspected to be called by the target chip and/or the target chip;

A thirty-fifth determining sub-module, configured to determine, according to two gate-level netlists of a chip, a result and/or a report of one or more formal verification operations in one or more formal verification operations using one or more formal verification software and/or tools and/or environments after modifying one or a part of the number of modules and/or units, and an IP core that is called and/or suspected to be called, the target chip and/or information of the target chip; the thirty-fifth determination sub-module includes, but is not limited to, one or more of the following: a twenty-third determining unit, configured to determine a failed gate-level netlist portion in verification, and/or a module and/or a unit and/or design information corresponding to the failed portion as an IP core called and/or suspected to be called by the target chip and/or information of the target chip; a twenty-fourth determining unit, configured to determine that the gate-level netlist portion corresponding to the mismatch point found in the verification, and/or the module and/or unit and/or design information corresponding to the portion and/or mismatch point is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a twenty-fifth determining unit, configured to determine an inequivalent part found in verification, and/or a gate-level netlist part corresponding to the inequivalent part, and/or a module and/or a unit and/or design information as an IP core called and/or suspected to be called by the target chip and/or information of the target chip; a twenty-sixth determining unit, configured to determine that a difference between logic and/or functions in the two gate-level netlists found in the verification and/or a gate-level netlist portion, and/or a module and/or a unit and/or design information corresponding to the difference are/is an IP core called and/or suspected to be called by the target chip and/or the target chip;

When the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the two gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the function and/or logic and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the function and/or logic and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logic and/or pins of the auxiliary design and/or auxiliary test include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the enable pin corresponding to the SCAN SCAN chain, the enable pin and/or the enable pin corresponding to the JTAG chain and/or the JTAG chain, and the corresponding pin and/or pin of the chip design for testability and/or design for testability.

Optionally, the second information includes a chip RTL code, and/or a gate-level netlist of the chip; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

a thirty-sixth determining sub-module, configured to determine a position of a nineteenth identifier in a chip RTL code and/or a portion where the nineteenth identifier is located and/or a portion where a code length between the nineteenth identifier and the nineteenth identifier is less than or equal to a forty-first preset threshold and/or a portion where an occupation ratio of the code length between the nineteenth identifier and the chip RTL code is less than or equal to a fifth proportion threshold, and/or a module and/or a unit and/or an IP core whose design information calls and/or is suspected to call the information of the target chip and/or the target chip; the nineteenth mark is a mark of a company other than the design company of the target chip and/or a mark representing a company other than the design company of the target chip;

a thirty-seventh determining sub-module, configured to determine a position of a twentieth identifier in the chip RTL code and/or a portion where a code length between the twentieth identifier and the twentieth identifier is smaller than or equal to a forty-first preset threshold and/or a portion where a ratio of the code length between the twentieth identifier and the chip RTL code is smaller than or equal to a sixth ratio threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the portion and/or the twentieth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the twentieth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

A thirty-eighth determining sub-module, configured to determine, according to a part of the chip RTL code where other level descriptions except the register transmission level description are located, the target chip and/or an IP core that is called by the information of the target chip and/or suspected of being called by the information of the target chip; the other level descriptions besides register transfer level description include but are not limited to gate level descriptions; wherein the thirty-eighth determination submodule includes, but is not limited to, one or more of: a twenty-seventh determining unit, configured to determine that one or more keywords present in the chip RTL code, and/or keywords corresponding to a forty-second preset threshold in the total number of the one or more keywords present in the chip RTL code, and/or keywords corresponding to a forty-third preset threshold in the proportion that the total number of the one or more keywords present in the chip RTL code occupies the entire chip RTL code, and determine, as the target core, a portion where a position and/or a portion where the keyword is located, and/or a portion where a code length between the keyword and the keyword is less than or equal to the forty-fourth preset threshold, and/or a portion where a code length between the keyword and the keyword is less than or equal to a seventh proportional threshold in the chip RTL code, and/or a module and/or unit and/or design information corresponding to the position and/or the portion, and/or the keyword And the IP core called by the information and/or suspected to be called of the chip and/or the target chip, wherein the keywords are keywords representing other level descriptions except for register transmission level descriptions, and the types of the keywords include but are not limited to one or more of the following: a characterization description level code, a characterization description level vocabulary and/or phrase, a characterization description level script, a characterization description level program, a characterization description level netlist, wherein the netlist includes but is not limited to a gate level netlist; a twenty-eighth determining unit, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twenty-fourth part and/or a twenty-fourth part in the chip RTL code, where the module and/or the unit and/or the design information are the same as and/or similar to a twenty-third part of the gate-level netlist of the chip and/or have a similarity greater than or equal to a forty-fifth preset threshold;

A thirty-ninth determining sub-module, configured to determine, as an IP core called and/or suspected to be called by information of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to a twenty-sixth part and/or a twenty-sixth part in the chip RTL code, where the module and/or unit and/or design information is the same as and/or similar to a twenty-fifth part of the RTL code in a twenty-third preset library and/or has a similarity greater than or equal to a forty-sixth preset threshold; the twenty-third preset library does not contain RTL codes designed by a design company of the target chip;

a fortieth determining sub-module, configured to determine, as an IP core called by the information and/or suspected to be called by the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twenty-eighth part and/or a twenty-eighth part of the chip RTL code, where the module and/or the unit and/or the design information is the same as and/or similar to a twenty-seventh part of the RTL code in a twenty-fourth preset library and/or has a similarity greater than or equal to a forty-seventh preset threshold; an RTL code designed for a design company of the target chip and/or an RTL code IP core library of the design company of the target chip and/or an IP core library of the design company of the target chip in the twenty-fourth preset library;

A forty-first determining submodule, configured to determine, according to a gate-level netlist of a chip RTL code and the chip, a result and/or a report of formal verification that one or more types of formal verification software and/or tools and/or environments are used for performing one or more times of formal verification, and fails, an IP core for information call and/or suspected call of the target chip and/or the target chip; the forty-first determination submodule includes, but is not limited to, one or more of: a twenty-ninth determining unit, configured to determine that an RTL code portion that fails in verification, and/or a gate-level netlist portion that fails, and/or a module and/or a unit and/or design information corresponding to the failed portion is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a thirtieth determining unit, configured to determine that an RTL code portion and/or a gate-level netlist portion corresponding to a mismatch point found in the verification, and/or a module and/or a unit and/or design information corresponding to the portion and/or the mismatch point are/is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a thirty-first determining unit, configured to determine an inequivalent portion found in verification, and/or an RTL code portion corresponding to the inequivalent portion, and/or a gate-level netlist portion, and/or a module and/or a unit and/or design information as an IP core for information call and/or suspected call of the target chip and/or the target chip; a thirty-second determining unit, configured to determine differences between logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist, and/or RTL code portions corresponding to the differences, and/or gate-level netlist portions, and/or modules and/or units and/or IP cores for which design information is called and/or suspected to be called for the target chip and/or information of the target chip, which are found in the verification;

A forty-second determining submodule, configured to determine, according to a gate-level netlist of a chip RTL code and a chip, a result and/or a report of formal verification that one or more formal verification software and/or tools and/or environments are used for performing one or more times of formal verification after one or a part of the number of the modules and/or units is modified, and the result and/or the report of the failed formal verification, an IP core for information call and/or suspected call of the target chip and/or the target chip; the forty-second determination submodule includes, but is not limited to, one or more of: a thirty-third determining unit, configured to determine that the failed RTL code portion and/or the failed gate-level netlist portion and/or the module and/or unit and/or design information corresponding to the failed RTL code portion and/or the failed gate-level netlist portion are/is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an RTL code part and/or a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or a unit and/or design information corresponding to the part and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a thirty-fourth determining unit, configured to determine an inequivalent portion found in verification, and/or an RTL code portion corresponding to the inequivalent portion, and/or a gate-level netlist portion, and/or a module and/or a unit and/or design information as an IP core for information call and/or suspected call of the target chip and/or the target chip; a thirty-fifth determining unit, configured to determine differences between the logic and/or functions in the RTL code and the logic and/or functions in the gate-level netlist, and/or RTL code portions and/or gate-level netlist portions corresponding to the differences, and/or modules and/or units and/or design information, which are found in the verification, as IP cores called and/or suspected to be called by the target chip and/or the target chip;

Optionally, the determining, according to the first information, whether to call the IP core and/or determine whether to call the IP core or not, when determining whether to call the IP core or not, the used preset threshold and/or identifier and/or preset library and/or the area and/or the portion thereof, and the determining, according to the second information, the information of the target chip and/or the target chip, the IP core called and/or suspected to be called, the used preset threshold and/or identifier and/or preset library and/or the area and/or the portion thereof are the same or different;

According to the first information, determining whether an IP core is called and/or is suspected to be called in a target chip and/or information of the target chip, and using preset thresholds and/or identifiers and/or preset libraries and/or areas and/or parts thereof, wherein the preset thresholds and/or identifiers and/or preset libraries and/or areas and/or parts thereof of the same type are the same or different;

and according to the second information, determining that the information of the target chip and/or the target chip, the IP core called and/or suspected to be called, the used preset threshold and/or identifier and/or preset library and/or the area and/or part thereof are the same or different.

Optionally, the IP core includes, but is not limited to, a non-self-developed IP core and/or a self-developed IP core;

wherein the non-self-developed IP core includes, but is not limited to, one or more of the following: an IP core not designed by the design company of the target chip, an IP core purchased by the design company of the target chip from other companies, an IP core called by the design company of the target chip from a non-self-developed IP core library, and an IP core of which intellectual property does not belong to the design company of the target chip;

Wherein, the self-developed IP core comprises but is not limited to one or more of the following: the design company of the target chip designs the IP core, the design company of the target chip independently develops the IP core, the design company of the target chip independently accumulates the IP cores, and intellectual property rights belong to the IP core of the design company of the target chip.

Optionally, the apparatus further comprises: the IP core classification module is used for determining whether the information of the target chip and/or the target chip, the called and/or suspected called IP core is a non-self-developed IP core and/or a self-developed IP core according to the first information and/or the second information and/or the information of the target chip and/or the design file of the target chip and/or the authorization data of the target chip; and/or

The IP core classification module is used for determining whether the IP core is a non-self-grinding IP core and/or a self-grinding IP core while determining the information of the target chip and/or the target chip, calling and/or suspected calling IP cores according to second information;

wherein, the IP core classification module comprises: the first classification submodule is used for determining the target chip and/or the information of the target chip, and the called and/or suspected called IP core as a non-self-research IP core; the first classification submodule includes, but is not limited to, one or more of the following:

The first classification unit is used for determining that the IP core determined by the contents corresponding to the blank area and/or the blank area in the chip design layout and/or the blank area is a non-self-research IP core;

the second classification unit is used for determining that the IP core determined by the inconsistency and/or the content corresponding to the inconsistency when the chip design layout and/or the corresponding chip real object and/or the real object layout and/or the layout is a non-self-research IP core;

a third classification unit, configured to determine that the IP core determined by a twenty-first identifier in the third information of the target chip is a non-self-developed IP core; the twenty-first mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

a fourth classification unit, configured to determine that an IP core determined by a twenty-sixth area in the third information of the target chip, which is the same as and/or similar to a twenty-fifth area of the information in the twenty-fifth preset library and/or has a similarity greater than or equal to a forty-eighth preset threshold, and/or a content corresponding to the twenty-sixth area is a non-self-research IP core; the twenty-fifth preset library does not contain the information designed by the design company of the target chip;

A fifth classification unit, configured to determine that an IP core determined by the same and/or similar to a twenty ninth part of the information in the twenty sixth preset library and/or a content corresponding to the thirtieth part of the third information of the target chip and/or the thirtieth part of the thirtieth information of the target chip, where the similarity is greater than or equal to a forty ninth preset threshold, is a non-self-research IP core; the twenty-sixth preset library does not contain the information designed by the design company of the target chip;

a sixth classification unit, configured to determine, by determining a position and/or a region of a chip real object and/or a real object layout and/or a module and/or a cell and/or design information corresponding to the position and/or the region, an IP core for determining a position and/or a region of a chip design layout and/or a design information corresponding to the chip design layout and/or the design layout and/or a module and/or a cell and/or design information corresponding to the position and/or the region, as a non-self-research IP core;

a seventh classification unit, configured to determine that, in one or more LVS verifications performed according to one or more LVS verification software and/or tools and/or environments, an IP core determined by a result of a failed LVS verification and/or a report is a non-self-developed IP core;

An eighth classification unit, configured to determine a result of formal verification that fails and/or report the determined IP core as a non-self-developed IP core in one or more formal verifications performed according to one or more formal verification software and/or tools and/or environments;

a ninth classification unit, configured to determine that an IP core determined according to a part of the level descriptions in the chip RTL code, excluding the register transfer level descriptions, is a non-self-developed IP core;

a tenth classification unit, configured to call and/or suspect-to-call an IP core for the information of the target chip and/or the target chip, and if it is determined that the IP core is not the information of the target chip and/or the target chip, the called and/or suspected-to-call self-research IP core, determine that the IP core is a non-self-research IP core for the information call and/or suspected-to-call of the target chip and/or the target chip;

wherein, the IP core classification module comprises: a second classification sub-module, configured to determine that the target chip and/or the IP core suspected to be called, which is called and/or called, is a self-research IP core, where the second classification sub-module includes, but is not limited to, one or more of the following:

an eleventh classification unit, configured to determine that the IP core determined by the twenty-second identifier in the third information of the target chip is a self-research IP core; the twenty-second identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

A twelfth classification unit, configured to determine that an IP core determined by a twenty-eighth region in the third information of the target chip and/or a content corresponding to the twenty-eighth region is the self-research IP core, where the twenty-seventh region is the same as and/or similar to the twenty-seventh region of the information in the twenty-seventh preset library and/or the similarity is greater than or equal to a fifty-fifth preset threshold; the twenty-seventh preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

a thirteenth classification unit, configured to determine that the IP core determined by the thirty-second part in the third information of the target chip and/or the content corresponding to the thirty-second part is the same as and/or similar to the thirty-first part of the information in the twenty-eighth preset library and/or the similarity is greater than or equal to the fifty-first preset threshold is a self-research IP core; the twenty-eighth preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

a fourteenth classification unit, configured to determine, by determining a position and/or a region of a chip real object and/or a real object layout and/or a module and/or a cell and/or design information corresponding to the position and/or the region, an IP core for determining a chip design layout and/or a position and/or a region of a design layout and/or a design layout corresponding to the chip real object and/or a real object layout and/or a module and/or a cell and/or design information corresponding to the position and/or the region, and the IP core for determining the module and/or the cell and/or the design information corresponding to the position and/or the region is a self-research IP core;

A fifteenth classification unit, configured to call and/or suspected to call an IP core for the information of the target chip and/or the target chip, and if it is determined that the IP core is not the information of the target chip and/or the target chip, the called and/or suspected called non-self-research IP core, determine that the IP core is a self-research IP core called and/or suspected called by the information of the target chip and/or the target chip;

wherein the third information of the target chip includes, but is not limited to, one or more of the following: the method comprises the following steps of designing a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a transistor-level netlist of the chip, a gate-level netlist of the chip, an RTL code of the chip, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information;

the twenty-fifth preset library and/or the twenty-sixth preset library and/or the twenty-seventh preset library and/or the twenty-eighth preset library and/or the information designed by the design company of the target chip and/or the information in the information IP core library of the design company of the target chip, and the information types include, but are not limited to, one or more of the following: layout and/or place-route patterns, schematic diagrams, transistor-level netlists, gate-level netlists, RTL codes.

Optionally, the apparatus further comprises: the judging module is used for judging the autonomy and/or the controllability of the chip; the decision module includes, but is not limited to, one or more of the following:

the first requirement determining unit is used for determining one or more kinds of fourth information required for judging the autonomy and/or the controllability of the chip, and the fourth information comprises but is not limited to one or more of the following: the chip comprises a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a chip transistor-level netlist, a chip gate-level netlist, a chip RTL code, all or part information of one or more kinds of information in first information, all or part information of one or more kinds of information in second information, and other information of the chip except the first information and the second information;

the first score distribution unit is used for distributing a score corresponding to each kind of the required one or more kinds of fourth information; wherein the first value assigning unit includes, but is not limited to: a first assigning subunit for assigning a score according to the difficulty level and/or the criticality level of realization and/or design of each fourth information;

A first score determining unit, configured to, for each type of the required fourth information, determine that a score obtained by the chip is: subtracting the score corresponding to the part of the information to be determined, which is absent in the obtained fourth information, and/or the absent function and/or the absent logic and/or the absent module and/or the absent unit, from the score corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information, and then, remaining the score; and/or, determining the score obtained by the chip as: a score corresponding to the fourth information, a score obtained by subtracting a first proportion of scores corresponding to the information part and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit of the chip to be judged which is missing in the fourth information, and a score obtained by subtracting a second proportion of scores corresponding to the non-self-research IP core which is called and/or suspected to be called in the fourth information; wherein, if the part of the information to be determined of the chip and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit in the obtained fourth information have repeated and/or overlapped contents with the non-self-research IP core called and/or suspected to be called in the obtained fourth information, the score is reduced once and/or not repeated and reduced for the repeated and/or overlapped contents; wherein the first score determining unit includes: a first ratio determining subunit configured to determine a first ratio and/or a second ratio, where the first ratio and/or the second ratio are satisfied by one or more of the following conditions: a ratio of less than or equal to 1, a ratio of greater than or equal to 0, a ratio of the missing information portion of the chip to be determined and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit when in country is less than or equal to a ratio when in non-country, a ratio of the called and/or suspected called non-self-study IP cores when in country is less than or equal to a ratio of the non-self-study IP cores when in non-country;

A second score determining unit, configured to, for each type of the required fourth information, if the obtained type of fourth information includes all the information of the chip to be determined and/or includes all functions and/or all logics and/or all modules and/or all units of the chip to be determined, and the obtained type of fourth information does not call a non-self-study IP core and is not suspected to call a non-self-study IP core, determine that a score obtained by the chip is: the score corresponding to the fourth information;

a third score determining unit, configured to determine, for each type of the required fourth information, that the chip does not obtain a score under the type of the fourth information if the type of the fourth information is not obtained and/or it cannot be confirmed that the obtained type of the fourth information is the fourth information of the chip;

the first judging unit is used for summing the actual scores obtained by the chip aiming at each kind of the required one or more kinds of fourth information to serve as the total score of the chip, and judging the autonomy and/or the controllability of the chip through the total score;

wherein, one of the obtained fourth information does not include all the information of the chip to be determined and/or does not include all the functions and/or all the logics and/or all the modules and/or all the units of the chip to be determined is that the non-self-developed IP core is called in other information after the design of the fourth information is completed, and the function and/or the logic and/or the module and/or the unit corresponding to the IP core is not designed in the fourth information;

When the required one or more types of fourth information are assigned with the scores corresponding to the various types of fourth information, it is required to ensure that the scores corresponding to the chips with the given functions under different schemes and with the same degree of autonomy and/or controllability are the same; the premise that the scores corresponding to the same degree of autonomy and/or controllability are all the same includes but is not limited to: under different schemes, the sum of the scores corresponding to the required various fourth information of a chip with a given function is the same;

the second requirement determining unit is used for determining various functions and/or logics and/or modules and/or units required for judging the degree of autonomy and/or controllability of the chip;

a second score distribution unit, configured to distribute, for each of the various required functions and/or logics and/or modules and/or units, a score corresponding to the function and/or logic and/or module and/or unit; wherein the second component assigning unit includes, but is not limited to: a second assignment subunit for assigning a score according to the ease and/or criticality of each function and/or logic and/or module and/or unit, implementation and/or design;

a fourth score determining unit, configured to determine, for each of the required functions and/or logics and/or modules and/or units, that the chip obtains a score corresponding to the function and/or logic and/or module and/or unit if no non-self-researched IP core is called and no non-self-researched IP core is suspected to be called in the function and/or logic and/or module and/or unit of the chip to be determined;

A fifth value determining unit, configured to determine, for each of the required functions and/or logics and/or modules and/or units, that the chip does not obtain a score corresponding to the function and/or logic and/or module and/or unit and/or that the chip obtains a score of a third ratio of scores corresponding to the function and/or logic and/or module and/or unit if a non-self-research IP core is called and/or suspected to be called in the function and/or logic and/or module and/or unit of the chip to be determined; wherein the third proportion is required to satisfy conditions including but not limited to one or more of the following: the proportion is less than or equal to 1, the proportion is greater than or equal to 0, and the proportion of the called and/or suspected called non-self-developed IP cores when the called and/or suspected called non-self-developed IP cores are in national hours is greater than or equal to the proportion of the called and/or suspected called non-self-developed IP cores when the called and/or suspected called non-self-developed IP cores are in non-national hours;

a sixth score determining unit, configured to determine, for each of the required functions and/or logics and/or modules and/or units, that the chip does not obtain a score under the function and/or logic and/or module and/or unit if the chip is determined to lack the function and/or logic and/or module and/or unit;

A second judging unit, configured to sum actual scores obtained by the chip for each of the various required functions and/or logics and/or modules and/or units, as a total score of the chip, and judge an autonomy and/or controllability of the chip through the total score;

when the scores corresponding to the various functions and/or logics and/or modules and/or units are distributed for the various required functions and/or logics and/or modules and/or units, it is required to ensure that the scores corresponding to the same degree of autonomy and/or controllability of a chip with a given function are the same under different schemes; the premise that the scores corresponding to the same degree of autonomy and/or controllability are all the same includes but is not limited to: the sum of the scores corresponding to the various required functions and/or logics and/or modules and/or units of a chip with a given function is the same under different schemes.

Optionally, the first score determining unit is further configured to calculate scores corresponding to the information part of the chip to be determined that is absent from the obtained fourth information and/or the absent function and/or the absent logic and/or the absent module and/or the absent unit, and/or scores corresponding to the non-self-study IP cores called and/or suspected to be called from the obtained fourth information, where the first score determining unit further includes, but is not limited to, one or more of the following:

The first value distribution subunit is used for distributing the values corresponding to various functions and/or logics and/or modules and/or units aiming at the needed fourth information and various functions and/or logics and/or modules and/or units, and the sum of the values corresponding to the various functions and/or logics and/or modules and/or units is the value corresponding to the fourth information; wherein the first partition subunit is used for, but not limited to: assigning a score based on the ease and/or criticality of each function and/or logic and/or module and/or unit, implementation and/or design;

a first score determining subunit, configured to find, among various functions and/or logics and/or modules and/or units in the required kind of fourth information, information portions and/or functions and/or logics and/or modules and/or units of chips to be determined that are absent from the obtained fourth information, and determine that a sum of scores or scores assigned to the information portions and/or logics and/or modules and/or units of chips to be determined that are absent from the obtained fourth information is a score corresponding to the information portions of chips to be determined that are absent from the obtained fourth information, and/or the absent functions and/or logics and/or modules and/or units;

And a second score determining subunit, configured to find, in various functions and/or logics and/or modules and/or units in the required fourth information, a function and/or logic and/or module and/or unit corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information, and determine that a score or a sum of scores assigned to the part of functions and/or logics and/or modules and/or units is a score corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information.

Optionally, the apparatus further includes a confirmation module, configured to confirm that the obtained information is information of the target chip; the information includes, but is not limited to, one or more of the following: the method comprises the following steps of designing a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a transistor-level netlist of the chip, a gate-level netlist of the chip, an RTL code of the chip, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information; other information of the chip except the first information and the second information; the confirmation module includes, but is not limited to, one or more of the following:

The first confirming submodule is used for confirming whether the acquired information is declared or identified as the information of the target chip;

the second confirming submodule is used for determining the obtained chip real object and/or real object layout and wiring diagram as the information of the target chip;

a third confirming sub-module, configured to compare and/or verify the obtained information to confirm whether the obtained information is the information of the target chip, where the third confirming sub-module includes, but is not limited to, one or more of the following: the first confirming unit is used for comparing and/or verifying the acquired information and the information declared or identified as the target chip for one or more times, and if the comparison and/or verification is passed, the acquired information is confirmed to be the information of the target chip; the second confirmation unit is used for comparing and/or verifying the acquired information with a chip real object and/or a real object layout and/or a wiring diagram for one time or more times, and if the comparison and/or verification is passed, the acquired information is confirmed to be the information of the target chip;

And the fourth confirming submodule is used for carrying out comparison and/or verification for one time or more times on the acquired information and the information confirmed as the target chip through comparison and/or verification, and if the comparison and/or verification is passed, the acquired information is the information of the target chip.

Optionally, the first acknowledgement unit and/or the second acknowledgement unit and/or the fourth acknowledgement submodule includes, but is not limited to, one or more of the following:

the first comparison subunit is used for comparing the chip design layout and/or design layout and wiring diagram with the chip real object and/or real object layout and wiring diagram;

the second comparison subunit is used for comparing the chip design layout and/or layout pattern with the chip real object and/or real object layout and/or layout pattern, and after removing the part and/or area and/or module and/or unit of the non-self-research IP core which is confirmed to be called or suspected to be called by the target chip, the rest chip design layout and/or design layout pattern with the rest chip real object and/or real object layout and/or layout pattern;

The first verification subunit is used for performing LVS verification on the schematic diagram of the chip and the chip design layout and/or the design layout and wiring;

a second verification subunit, configured to perform LVS verification on the schematic diagram of the remaining chip, and the design layout and/or layout of the remaining chip after removing the portion and/or region and/or module and/or cell and/or design information of the non-self-developed IP core that has been confirmed as a target chip call or suspected call;

the third verification subunit is used for performing LVS verification on the netlist of the chip transistor level and the chip design layout and/or the design layout pattern;

a fourth verification subunit, configured to perform LVS verification on the netlist of the remaining chip transistor level, and the design layout and/or design layout after removing the part and/or region and/or module and/or cell and/or design information of the non-self-developed IP core that has been confirmed as a target chip call or suspected call;

The fifth verification subunit is used for performing LVS verification on the gate-level netlist of the chip and the chip design layout and/or the design layout and wiring diagram;

a sixth verification subunit, configured to perform LVS verification on the gate-level netlist of the remaining chip, and the remaining chip design layout and/or design layout pattern after removing the part and/or region and/or module and/or cell and/or design information of the non-self-researched IP core that has been confirmed as a target chip call or suspected call;

the seventh verification subunit is used for performing LVS verification on the converted gate-level netlist of the chip and the chip design layout and/or the design layout after converting the gate-level netlist of the chip into the chip transistor-level netlist;

the eighth verification subunit is used for converting the gate-level netlist of the chip into a chip transistor-level netlist, then converting the converted chip transistor-level netlist into a chip design layout and/or a design layout pattern, removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-research IP core which is confirmed to be called or suspected to be called by the target chip, and then performing LVS verification on the rest chip transistor-level netlist, and the rest chip design layout and/or the design layout pattern;

A ninth verification subunit, configured to remove a part and/or a region and/or a module and/or a cell and/or design information of the non-self-study IP core that is determined to be called or suspected to be called by the target chip, and then convert the remaining gate-level netlist into a transistor-level netlist, and perform LVS verification on the converted transistor-level netlist and the remaining chip design layout and/or layout pattern part;

the tenth verification subunit is used for performing formal verification on one gate-level netlist of the chip and the other gate-level netlist of the chip;

an eleventh verification subunit, configured to perform formal verification on the one-level netlist of the remaining chips and the another-level netlist of the remaining chips after removing the part and/or the region and/or the module and/or the unit and/or the design information of the non-self-developed IP core that has been determined as the target chip call or the suspected call;

the twelfth verification subunit is used for performing formal verification on the RTL code of the chip and the gate-level netlist of the chip;

A thirteenth verification subunit, configured to perform formal verification on the RTL code of the remaining chip and the gate-level netlist of the remaining chip after removing the part and/or the region and/or the module and/or the unit and/or the design information of the non-self-researched IP core that is confirmed as the target chip call or suspected call;

when the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or the auxiliary test are different between the two verified gate-level netlists and/or between the verified RTL code and the gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

Optionally, the chip design layout and/or design place and route pattern, and/or the area in the chip design layout and/or design place and route pattern, including but not limited to all layers and/or part of layers and/or one layer of chip design layout and/or design place and route pattern, for one layer, the chip design layout and/or design place-and-route pattern includes, but is not limited to, a chip design layout and/or design place-and-route pattern for an entire area and/or for a plurality of local areas and/or for one local area; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different; and/or the presence of a gas in the atmosphere,

the chip real object and/or physical layout of the chip comprises, but is not limited to, all layers and/or part layers and/or one layer of chip real object and/or physical layout, and for one layer of the chip real object and/or physical layout of the chip real object and/or physical layout of the whole area and/or a plurality of local areas and/or one local area, but not limited to the whole area and/or the physical layout and/or physical layout of the chip of the whole area An object layout wiring and/or a physical layout wiring diagram; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different; and/or the presence of a gas in the gas,

The layout and/or place-and-route patterns, and/or the regions in the layout and/or place-and-route patterns in the preset library, including but not limited to all layers and/or partial layers and/or one layer of layout and/or place-and-route patterns, for one of the layers, the layout and/or place-and-route patterns include but not limited to the layout and/or place-and-route patterns of the whole region and/or a plurality of partial regions and/or one partial region; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different; and/or the presence of a gas in the atmosphere,

a schematic diagram of the chip, and/or a region in a schematic diagram of the chip, including but not limited to a chip schematic diagram of an entire region and/or a plurality of partial regions and/or a partial region; and/or the presence of a gas in the atmosphere,

schematic diagrams in the preset library and/or areas in the schematic diagrams, including but not limited to schematic diagrams of the whole area and/or a plurality of local areas and/or one local area; and/or the presence of a gas in the atmosphere,

the chip transistor-level netlist, and/or portions of a transistor-level netlist, include, but are not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level; and/or the presence of a gas in the atmosphere,

The transistor-level netlist, and/or the portions of the transistor-level netlist in the preset library include, but are not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level; and/or the presence of a gas in the gas,

the gate level netlist, and/or portions of the gate level netlist of the chip, include, but are not limited to: the whole gate-level netlist and a part of gate-level netlist; and/or the presence of a gas in the gas,

the gate level netlist in the preset library, and/or the portion of the gate level netlist, include but are not limited to: the whole gate-level netlist and a part of gate-level netlist; and/or the presence of a gas in the gas,

the chip RTL code, and/or portions of RTL code, include, but are not limited to, one or more of: the whole RTL code, part of the RTL code, the RTL code claimed by the design company of the target chip, and the code designed by the design company of the target chip in the RTL design stage; and/or the presence of a gas in the gas,

the RTL code in the preset library, and/or portions of the RTL code, include but are not limited to: the whole RTL code and part of the RTL code; and/or the presence of a gas in the gas,

the chip design layout and/or design place-and-route patterns include, but are not limited to, one or more of the following: a comment and/or description in the chip design layout and/or design layout pattern; and/or the presence of a gas in the gas,

The chip real object and/or real object layout and/or layout of the chip real object and/or real object layout and/or layout of the chip real object and/or real object layout and/or layout of the chip real object layout and/or layout of the chip real object and/or the chip real object layout of the chip real object layout and/or the layout of the chip of the: annotation and/or description in chip real object and/or real object layout wiring diagram; and/or the presence of a gas in the gas,

the schematic diagram of the chip includes, but is not limited to, one or more of the following: schematic diagram of the chip, comments and/or explanations in the schematic diagram of the chip; and/or the presence of a gas in the gas,

the netlist at the chip transistor level includes, but is not limited to, one or more of the following: a netlist at the chip transistor level, comments and/or descriptions in the netlist at the chip transistor level; and/or the presence of a gas in the gas,

the gate-level netlist of the chip includes, but is not limited to, one or more of the following: a gate-level netlist of the chip, comments and/or descriptions in the gate-level netlist of the chip; and/or the presence of a gas in the gas,

the chip RTL code includes but is not limited to one or more of the following: chip RTL code, comments and/or descriptions in the chip RTL code; and/or the presence of a gas in the gas,

the identification includes one or more of: text, graphics, trademarks, names, logos, indicia, watermarks.

In a third aspect, the present invention further provides an electronic device, including a memory, a processor, and a program stored in the memory and executable on the processor; and when the processor executes the program, the steps of any one of the IP core calling detection methods are realized.

In a fourth aspect, the present invention further provides a readable storage medium, on which a program is stored, where the program, when executed by a processor, implements the steps in any of the methods for detecting an IP core call described above.

The technical scheme of the invention has the following beneficial effects:

the embodiment of the invention improves the accuracy and the reliability of the detection of the calling condition of the IP core.

Drawings

Fig. 1 is a schematic flowchart of a detection method for IP core invocation in a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a detection apparatus for IP core invocation in a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of an electronic device in a third embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic flowchart of a method for detecting an IP core call according to an embodiment of the present invention, including the following steps:

step 11: determining whether to call (also can be called to use, borrow, embed, nest and the like, the same below) an IP core and/or whether to call the IP core suspected to be in the target chip and/or the information of the target chip according to the first information;

step 12: according to the second information, determining the target chip and/or the information of the target chip, and calling and/or suspected calling IP cores;

It should be noted that the first information and the second information may be physical information and/or design information of the target chip, and the first information and the second information may be the same or different. The information of the target chip may be physical information and/or design information of the target chip. Specifically, the following can be referred to.

The embodiment of the invention can improve the accuracy and the reliability of the detection of the calling condition of the IP core.

In other optional embodiments, only step 11 may be performed, that is, only the first information may be used to determine whether to invoke the IP core and/or whether to suspect to invoke the IP core in the target chip and/or the information of the target chip, and step 12 is not performed. Only step 12 may be performed, that is, only the information of the target chip and/or the target chip may be determined according to the second information, and the IP core to be called and/or suspected to be called is called and not step 11 is performed.

Optionally, the target chip is a whole or partial chip, and the types of the chips include but are not limited to one or more of the following: a packaged chip, an unpackaged die (die is also referred to as die, die), a module in a die (including a functional module in a die), a unit in a die (including a functional unit in a die) has been completed.

It should be noted that from the classification point of view, the chip is a general term, and includes but is not limited to integrated circuit ICs, microsystems MEMS, microelectromechanical systems, semiconductor devices, discrete devices, sensors, actuators, and so on.

Optionally, the determining whether the IP core is called and/or suspected to be called in the target chip and/or the information of the target chip is performed in two steps or performed in one step with the determining of the IP core that is called and/or suspected to be called in the target chip and/or the information of the target chip;

optionally, the IP core that determines whether the information of the target chip and/or the target chip is called and/or suspected to be called is also a method for determining whether the IP core is called and/or suspected to be called in the target chip and/or the information of the target chip.

Optionally, the first information includes a chip design layout and/or a design layout pattern, and/or a chip entity and/or an entity layout pattern;

optionally, the determining, according to the first information, whether to invoke the IP core and/or whether to suspect to invoke the IP core in the target chip and/or in the information of the target chip includes, but is not limited to, one or more of the following 5.1 to 5.8:

5.1, in a chip design layout and/or a design layout, if a blank area and/or a blank area is larger than or equal to a first preset threshold and/or a blank area occupation ratio is larger than or equal to a second preset threshold and/or a blank area is a regular geometric figure, determining that an IP core is called and/or suspected to be called in the target chip and/or the information of the target chip;

optionally, the blank area occupation ratio refers to a ratio of blank areas occupying the design layout and/or the design layout pattern;

optionally, the regular geometry includes, but is not limited to, one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc;

5.2, comparing a chip design layout and/or design layout with a corresponding chip real object and/or real object layout and/or layout, and if the comparison is not consistent, determining that an IP core is called and/or suspected to be called in the target chip and/or the information of the target chip;

optionally, the case of inconsistent alignment includes but is not limited to one or more of the following: all layers and/or a part of layers and/or a layer are not in consistent alignment; the whole area and/or a plurality of local areas and/or one local area in all layers and/or part layers and/or one layer are not consistent in comparison;

5.3, if a first identifier exists in the chip design layout and/or chip real object and/or real object layout and/or layout, determining that an IP core is called and/or suspected to be called in the target chip and/or the information of the target chip; the first mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

5.4, if a second identifier exists in the chip design layout and/or the chip real object and/or real object layout, determining that an IP core is called and/or an IP core is suspected to be called in the target chip and/or the information of the target chip; the second identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

5.5, comparing the chip design layout and/or design layout pattern with a layout and/or layout pattern in a first preset library, and if a first area in the chip design layout and/or design layout pattern is the same as and/or similar to a second area in the layout and/or layout pattern in the first preset library and/or the similarity is larger than or equal to a third preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; the first preset library does not contain a layout and/or a wiring layout of the design company of the target chip;

5.6, comparing the chip design layout and/or design layout pattern with the layout and/or layout pattern in a second preset library, and if a third area in the chip design layout and/or design layout pattern is the same as and/or similar to and/or has a similarity degree greater than or equal to a fourth preset threshold with the layout and/or layout pattern in the second preset library, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; and the second preset library is a layout and/or a wiring layout diagram designed for the design company of the target chip, and/or a layout and/or a wiring layout diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip.

5.7, arranging the chip in a real object and/or a real object layout, comparing the chip layout, the same and/or similar and/or similarity degree with the sixth area of the layout and/or place-and-route pattern in the third preset library is larger than or equal to a fifth preset threshold, determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core; the third preset library does not contain the layout and/or the wiring layout diagram designed by the design company of the target chip;

5.8, arranging the chip in a real object and/or a real object layout, comparing with the layout and/or layout of the chip in the seventh area of the real object and/or real object layout and/or layout of the chip in the fourth preset library, the same and/or similar and/or similarity degree with the eighth area of the layout and/or routings layout in the fourth preset library is larger than or equal to a sixth preset threshold, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip; and the fourth preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip.

Optionally, the first information includes a schematic diagram of the chip, and/or a chip design layout and/or a design layout diagram;

Optionally, the determining, according to the first information, whether to invoke an IP core and/or determine whether to invoke an IP core in the target chip and/or in the information of the target chip, includes but is not limited to one or more of the following 6.1 to 6.6:

6.1, if a third identifier exists in the schematic diagram of the chip, determining that an IP core is called and/or suspected to be called in the target chip and/or the information of the target chip; the third mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

6.2, if a fourth identifier exists in the schematic diagram of the chip, determining that an IP core is called and/or suspected to be called in the target chip and/or the information of the target chip; the fourth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

6.3, comparing the schematic diagram of the chip with a schematic diagram in a fifth preset library, and if a ninth area in the schematic diagram of the chip is the same as and/or similar to a tenth area in the schematic diagram of the fifth preset library and/or the similarity is greater than or equal to a seventh preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core; the fifth preset library does not contain a schematic diagram designed by a design company of the target chip;

6.4, comparing the schematic diagram of the chip with a schematic diagram in a sixth preset library, and if the eleventh area in the schematic diagram of the chip is the same as or similar to the twelfth area in the schematic diagram of the sixth preset library and/or the similarity is greater than or equal to an eighth preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core; the sixth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

6.5, aiming at the schematic diagram of the chip and the chip design layout and/or layout diagram, one or more LVS verification software and/or tools and/or environments are used for performing one or more LVS verification, and if the one or more LVS verification fails, the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core;

it should be noted that the LVS verification environment may be: a set of Electronic Design Automation (EDA) environments including LVS verification, such as a set of EDA software environments capable of performing design, simulation and verification, and performing LVS verification directly in the whole set of environments. In one example, if the verification object passes the verification in one set of LVS verification environments, but does not pass the verification in another set of LVS verification environments, it is determined that the target chip and/or the information of the target chip call the IP core and/or is suspected to call the IP core.

6.6, aiming at the schematic diagram of the chip and the chip design layout and/or wiring diagram, modifying one or part of the number or all of the module (which may be the module itself or an instantiated module) and/or unit name, and performing one or more times of LVS verification by using one or more LVS verification software and/or tools and/or environments after modification, if one or more times of LVS verification fails, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core.

It should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. In one example, if the verification object passes the verification in one set of LVS verification environments, but does not pass the verification in another set of LVS verification environments, it is determined that the target chip and/or the information of the target chip invokes the IP core and/or is suspected to invoke the IP core.

Optionally, the first information includes a netlist of a chip transistor level, and/or a chip design layout and/or a design place and route pattern;

Optionally, the netlist of the transistor level includes, but is not limited to, one or more of the following: the analog-digital mixed chip is composed of a transistor-level netlist corresponding to an analog module schematic diagram and/or a transistor-level netlist corresponding to a digital module-finished gate-level netlist of the final design; it should be noted that, the netlist at the transistor level refers to describe the transistor level (including devices such as transistors, capacitors, resistors, etc.), and the forms are various, such as cdl netlist, scs netlist, spice netlist, etc.;

optionally, the determining, according to the first information, whether to invoke an IP core and/or determine whether to suspect to invoke an IP core in the target chip and/or in the information of the target chip includes, but is not limited to, one or more of the following 7.1 to 7.6:

7.1, if a fifth identifier exists in the netlist of the chip transistor level, determining that the target chip and/or the information of the target chip call an IP core and/or suspected to call the IP core; the fifth identification is an identification of a company other than the design company of the target chip and/or an identification representing the company other than the design company of the target chip;

7.2, if a sixth identifier exists in the netlist of the chip transistor level, determining that the IP core is called by the target chip and/or the information of the target chip and/or the suspected IP core is called; the sixth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

7.3, comparing the netlist of the chip transistor level with the netlist of the transistor level in a seventh preset library, and if the first part of the netlist of the chip transistor level is the same as the second part of the netlist of the transistor level in the seventh preset library and/or is similar to the second part of the netlist of the transistor level in the seventh preset library and/or the similarity is greater than or equal to a ninth preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core; the seventh preset library does not contain a netlist of a transistor level designed by a design company of the target chip;

7.4, comparing the netlist of the chip transistor level with the netlist of the transistor level in an eighth preset library, and if a third part in the netlist of the chip transistor level is the same as a fourth part in the netlist of the transistor level in the eighth preset library and/or is similar to the third part and/or has a similarity degree larger than or equal to a tenth preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; the eighth preset library is a netlist of a transistor level designed by a design company of the target chip, and/or a netlist IP core library of a transistor level of a design company of the target chip, and/or an IP core library of a design company of the target chip;

7.5, aiming at the netlist of the chip transistor level and the chip design layout and/or design layout, one or more LVS verification software and/or tools and/or environments are used for performing LVS verification for one time or more times, and if the LVS verification for one time or more times does not pass, the IP core is called by the information of the target chip and/or the suspected IP core is called;

7.6, aiming at the netlist of the chip transistor level and the chip design layout and/or layout, modifying one or part of the number or all of the module and/or unit names, and performing LVS verification for one time or more times by using one or more LVS verification software and/or tools and/or environments after modification, and if the LVS verification for one time or more times does not pass, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core.

It should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. In one example, if the verification object passes the verification in one set of LVS verification environments, but does not pass the verification in another set of LVS verification environments, it is determined that the target chip and/or the information of the target chip call the IP core and/or is suspected to call the IP core.

Optionally, the first information includes a gate-level netlist of the chip, and/or a chip design layout and/or a design place and route pattern;

optionally, the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip register transmission level RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process are finished; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

Optionally, the determining, according to the first information, whether to call the IP core and/or whether to call the IP core in the target chip and/or the information of the target chip is suspected to call the IP core includes, but is not limited to, one or more of the following 8.1 to 8.11:

8.1, if a seventh identifier exists in the gate-level netlist of the chip, determining that the target chip and/or the information of the target chip call an IP core and/or suspected call the IP core; the seventh mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

8.2, if the eighth identifier exists in the gate-level netlist of the chip, determining that the IP core is called by the target chip and/or the information of the target chip and/or suspected to be called by the target chip; the eighth mark is a mark of a design company of the target chip and/or a mark representing the design company of the target chip;

8.3, comparing the gate-level netlist of the chip with a gate-level netlist in a ninth preset library, and if a fifth part of the gate-level netlist of the chip is the same as a sixth part of the gate-level netlist in the ninth preset library and/or is similar to the sixth part of the gate-level netlist in the ninth preset library and/or the similarity is greater than or equal to an eleventh preset threshold, determining that the IP core is called by the target chip and/or the information of the target chip and/or the IP core is suspected to be called; the ninth preset library does not contain a gate-level netlist designed by a design company of the target chip;

8.4, comparing the gate-level netlist of the chip with a gate-level netlist in a tenth preset library, and if a seventh part of the gate-level netlist of the chip is the same as an eighth part of the gate-level netlist in the tenth preset library and/or similar to the eighth part of the gate-level netlist in the tenth preset library and/or the similarity is greater than or equal to a twelfth preset threshold, determining that the IP core is called by the target chip and/or the information of the target chip and/or the suspected IP core is called by the information of the target chip; a gate-level netlist designed for a design company of the target chip, and/or a gate-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the tenth preset library;

8.5, aiming at the gate-level netlist of the chip and the chip design layout and/or design layout pattern, one or more LVS verification software and/or tools and/or environments are used for performing LVS verification for one time or more times, and if the LVS verification for one time or more times does not pass, the IP core is called by the information of the target chip and/or the IP core is suspected to be called;

8.6, aiming at the gate-level netlist of the chip and the chip design layout and/or design layout pattern, modifying one or part of the number or all of the module and/or unit names, and performing LVS verification for one or more times in one or more LVS verification software and/or tools and/or environments after modification, and if the LVS verification for one or more times does not pass, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core;

it should be noted that, the LVS verification environment may be: a set of EDA environment including LVS verification, such as a set of EDA software environment capable of being designed, simulated and verified, is directly used for LVS verification in the whole set of environment. In one example, if the verification object passes the verification in one set of LVS verification environments, but does not pass the verification in another set of LVS verification environments, it is determined that the target chip and/or the information of the target chip call the IP core and/or is suspected to call the IP core.

8.7, after converting the gate-level netlist of the chip into a chip transistor-level netlist, aiming at the converted chip transistor-level netlist and the chip design layout and/or design layout wiring diagram, performing LVS verification for one or more times by using one or more LVS verification software and/or tools and/or environments, and if the LVS verification for one or more times fails, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core;

It should be noted that the LVS verification environment may be: a set of EDA environment including LVS verification, such as a set of EDA software environment capable of being designed, simulated and verified, is directly used for LVS verification in the whole set of environment. In one example, if the verification object passes the verification in one set of LVS verification environments, but does not pass the verification in another set of LVS verification environments, it is determined that the target chip and/or the information of the target chip call the IP core and/or is suspected to call the IP core.

8.8, after converting the gate-level netlist of the chip into a chip transistor-level netlist, modifying one or part of the netlist or names of all modules and/or units according to the converted chip transistor-level netlist and the chip design layout and/or design layout wiring diagram, and performing one or more LVS verifications in one or more LVS verification software and/or tools and/or environments after modification, if the one or more LVS verifications fail, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core;

8.9, aiming at the gate-level netlist of the chip and the chip design layout and/or design layout wiring diagram, modifying one or part of the number or all of the names of the modules and/or units, converting the modified gate-level netlist into a chip transistor-level netlist, aiming at the converted chip transistor-level netlist and the modified chip design layout and/or design layout wiring diagram, carrying out LVS verification for one or more times by using one or more LVS verification software and/or tools and/or environments, if the LVS verification for one or more times does not pass, determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core;

8.10, performing Formal Verification once or more times by using one or more Formal Verification (FV) software and/or tools and/or environments aiming at two gate-level netlists of the chip, and if the Formal Verification once or more times does not pass, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core;

it should be noted that the two gate-level netlists may be any two of, and/or two of, one or more of, but not limited to: the final design is completed through a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by synthesizing chip register transfer level RTL codes, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist in the chip design process, wherein the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists.

It should be noted that the formal verification environment may be: a set of EDA environment including formal verification, such as a set of EDA software environment which can be used for design, simulation and verification, is directly used for formal verification in the whole set of environment. In one example, if the verification object passes verification in one set of formal verification environments but does not pass verification in another set of formal verification environments, it is determined that the target chip and/or the information of the target chip invokes the IP core and/or is suspected to invoke the IP core.

8.11, aiming at two gate-level netlists of the chip, modifying one or part of the number or all the names of the modules and/or units, and performing one or more times of formal verification by using one or more formal verification software and/or tools and/or environments after modification, and if the one or more times of formal verification fails, determining that the target chip and/or the information of the target chip call an IP core and/or suspected to call the IP core;

it should be noted that the two gate level netlists may be any two, and/or two, of one or more of the following, including but not limited to: the final design is completed through a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by synthesizing chip register transfer level RTL codes, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist in the chip design process, wherein the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists. It should be noted that the two gate level netlists may be any two, and/or two, of one or more of the following, including but not limited to: the final design is completed through a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by synthesizing chip register transfer level RTL codes, a front-end gate-level netlist, a back-end gate-level netlist, and a gate-level netlist in the chip design process, wherein the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists. It should be noted that the formal verification environment may be: a set of EDA environment including formal verification, such as a set of EDA software environment which can be used for design, simulation and verification, is directly used for formal verification in the whole set of environment. In one example, if the verification object passes verification in one set of formal verification environments but does not pass verification in another set of formal verification environments, it is determined that the target chip and/or the information of the target chip invokes the IP core and/or is suspected to invoke the IP core.

Optionally, when performing formal verification, if there is a difference between the two gate-level netlists in the functions and/or logics of the auxiliary design and/or auxiliary test, the function and/or logic corresponding to the difference is not verified or verified;

for example, one gate-level netlist is a front-end netlist, one gate-level netlist is a back-end netlist, and the back-end netlist is added with a scan chain for testability design, and if the scan chain is considered to be a function convenient for subsequent chip testing and not used as a focus point for IP core detection, verification can be omitted; otherwise, if the IP core detection is also needed, the verification is carried out; similarly, for other functions and/or logic, whether to verify or not may also be determined according to the interest points detected for the IP core.

Optionally, the method for verifying the function and/or logic corresponding to the difference includes, but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid;

optionally, the functional and/or logic and/or pins of the design and/or test assistance include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

Optionally, the first information includes a chip RTL code, and/or a gate-level netlist of the chip;

optionally, the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

optionally, the determining, according to the first information, whether to call the IP core and/or whether to call the IP core in the target chip and/or in the information of the target chip is suspected to call the IP core includes, but is not limited to, one or more of the following 9.1 to 9.7:

9.1, if a ninth identification exists in the chip RTL code, determining that the target chip and/or the information of the target chip call an IP core and/or suspected call the IP core; the ninth mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

9.2, if the chip RTL code has a tenth identifier, determining that the target chip and/or the information of the target chip call an IP core and/or suspected calling the IP core; the tenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

9.3, if other level descriptions except the register transmission level description exist in the RTL code of the chip, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip;

optionally, the other level descriptions besides the register transfer level description include, but are not limited to, a gate level description;

optionally, the method for checking whether there are other level descriptions besides the register transfer level description in the chip RTL code includes, but is not limited to, one or more of the following:

optionally, keyword retrieval is performed on the chip RTL code;

optionally, comparing the chip RTL code with the gate-level netlist of the chip, and if a ninth part of the chip RTL code is the same as and/or similar to a tenth part of the gate-level netlist of the chip and/or the similarity is greater than or equal to a thirteenth preset threshold, determining that other level descriptions except for the register transmission level description exist in the chip RTL code;

Optionally, the method for performing keyword search on the chip RTL code includes, but is not limited to, one or more of the following: searching the RTL code by using one or more keywords representing other level descriptions except the register transmission level description, and if the RTL code is found to have one or more keywords and/or the total quantity of the one or more keywords in the RTL code is greater than or equal to a fourteenth preset threshold and/or the proportion of the total quantity of the one or more keywords in the RTL code occupying the whole RTL code word is greater than or equal to a fifteenth preset threshold, determining that other level descriptions except the register transmission level description exist in the chip RTL code; searching the RTL code by using one or more keywords representing register transmission level descriptions, and if various keywords are found not to exist in the RTL code and/or one or more keywords do not exist in the RTL code, determining that other level descriptions except the register transmission level descriptions exist in the chip RTL code; the categories of the keywords include, but are not limited to, one or more of the following: code at a representation description level, words and/or phrases at a representation description level, scripts at a representation description level, programs at a representation description level, RTL code at a representation description level, a netlist at a representation description level, wherein the netlist includes but is not limited to a gate-level netlist;

9.4, comparing the chip RTL code with an RTL code in an eleventh preset library, and if the eleventh part in the chip RTL code is the same as and/or similar to the twelfth part in the RTL code in the eleventh preset library and/or the similarity is greater than or equal to a sixteenth preset threshold, determining that the IP core is called by the target chip and/or the information of the target chip and/or the suspected IP core is called by the information of the target chip; the eleventh preset library does not contain RTL codes designed by a design company of the target chip;

9.5, comparing the chip RTL code with an RTL code in a twelfth preset library, and if a thirteenth part of the chip RTL code is the same as and/or similar to a fourteenth part of the RTL code in the twelfth preset library and/or the similarity is greater than or equal to a seventeenth preset threshold, determining that the target chip and/or the information of the target chip call an IP core and/or is suspected to call the IP core; an RTL code designed for a design company of the target chip and/or an RTL code IP core library of the design company of the target chip and/or an IP core library of the design company of the target chip in the twelfth preset library;

9.6, performing formal verification for one or more times by using one or more formal verification software and/or tools and/or environments aiming at the RTL code of the chip and the gate-level netlist of the chip, and if the formal verification for one or more times does not pass, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core;

It should be noted that the formal verification environment may be: the method comprises a set of EDA environments including formal verification, for example, a set of EDA software environments capable of being designed, simulated and verified, and formal verification is directly performed in the whole set of environments. In one example, if the authentication object passes authentication in one set of formal authentication contexts but does not pass authentication in another set of formal authentication contexts, then it is determined that the target chip and/or the information of the target chip invokes an IP core and/or is suspected of invoking an IP core.

9.7, aiming at the gate-level netlist of the chip RTL code and the chip, modifying one or part of the number or all of the names of the modules and/or units, performing one or more formal verification in one or more formal verification software and/or tools and/or environments after modification, and if any one or more formal verification fails, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core;

Optionally, when performing formal verification, if there is a difference between the RTL code and the netlist in terms of functions and/or logics of the auxiliary design and/or auxiliary test, the function and/or logic corresponding to the difference is not verified or verified;

for example, the gate-level netlist is a back-end netlist, and compared with an RTL code, a scan chain for testability design is added, and if it is considered that the scan chain is a function convenient for subsequent chip testing and is not used as a focus point for IP core detection, verification may not be performed; otherwise, if the IP core detection is also needed, the verification is carried out; similarly, for other functions and/or logic, whether to verify may also be determined based on whether the focus of detection is for an IP core.

Optionally, the method for not verifying the function and/or logic corresponding to the difference includes, but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid;

optionally, the determining, according to the second information, information of the target chip and/or the target chip, and the IP core called and/or suspected to be called include, but are not limited to, one or more of the following 10.1 to 10.11:

10.1, determining a blank area in the chip design layout and/or design layout pattern, and/or a blank area with an area larger than or equal to an eighteenth preset threshold, and/or a blank area with an occupation ratio larger than or equal to a nineteenth preset threshold, and/or a blank area of a regular geometric figure, and corresponding the blank area, and/or the blank area (referring to the former blank area in the chip design layout and/or design layout pattern, and/or design layout pattern), and/or the blank area with an area larger than or equal to the eighteenth preset threshold, and/or the blank area with an occupation ratio larger than or equal to the nineteenth preset threshold, and/or a blank area of the regular geometric figure) to the design layout and/or design layout pattern Or the design layout and wiring diagram, and/or the blank region (referring to the blank region in the front: chip design layout and/or blank region with area larger than or equal to eighteenth preset threshold, and/or blank region with occupation ratio larger than or equal to nineteenth preset threshold, and/or blank region of regular geometric figure), the corresponding module (may be the layout itself, or may be a series of information such as layout/schematic diagram/gate-level netlist/RTL code corresponding to the module, and the unit is determined as the target core and/or the design information The IP core of the information calling and/or suspected calling of the piece and/or the target chip;

Optionally, the occupation ratio refers to a ratio of the blank areas occupying the design layout and/or the design placement and/or the design layout;

optionally, the regular geometry includes, but is not limited to, one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc; the blank area includes, but is not limited to, one or more areas;

10.2, determining the inconsistency of the chip design layout and/or layout of the chip real object and/or real object layout and/or layout of the corresponding chip real object, determining the inconsistent position and/or the design layout and/or the chip real object and/or the real object layout and/or the chip real object layout corresponding to the inconsistent position and/or the chip real object layout information corresponding to the inconsistent position as the IP core for the information calling and/or the chip suspected to be called;

Optionally, wherein the inconsistency includes, but is not limited to, one or more of the following: all layers and/or part of layers and/or one layer are inconsistent in comparison; all layers and/or part of layers and/or one layer, wherein the whole area and/or a plurality of local areas and/or one local area are in inconsistent alignment; the inconsistency place includes but is not limited to one or more places of layout and/or place-route patterns;

10.3, determining the position of the eleventh mark in the chip design layout and/or object layout and/or layout, and/or the region where the eleventh mark is located and/or the region where the distance from the eleventh mark is less than or equal to the twentieth preset threshold, and/or the position and/or the region (referring to the previous chip design layout and/or layout of the previous chip object and/or object layout and/or object layout and/or eleventh mark location and/or region where the eleventh mark is located and/or Or an area with a distance from the eleventh identifier smaller than or equal to a twentieth preset threshold) and/or a module and/or a unit corresponding to the eleventh identifier and/or design information is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip;

10.4, determining the position of the eleventh marker in the chip design layout and/or physical layout, and/or the region of the eleventh marker with the distance from the eleventh marker being less than or equal to the twenty-first preset threshold, and/or the position and/or the region (referring to the previous chip design layout and/or the previous chip physical layout and/or physical layout and/or the eleventh marker position of the eleventh marker and/or the region of the eleventh marker in the chip physical layout and/or physical layout /or an area with a distance from the eleventh identifier smaller than or equal to a twenty-first preset threshold) and/or module and/or unit and/or design information corresponding to the eleventh identifier, determining the position and/or area of one or more layers and/or the module and/or unit and/or design information corresponding to the position and/or area of the one or more layers as an IP core called by the information of the target chip and/or suspected to be called; wherein the twenty-first preset threshold is the same as or different from the twentieth preset threshold;

Optionally, wherein the eleventh identifier is an identifier of a company other than the design company of the target chip and/or an identifier representing a company other than the design company of the target chip;

10.5, determining the position of a twelfth mark in a chip design layout and/or physical layout of the position of the twelfth mark and/or physical layout Or an area with a distance from the twelfth identifier smaller than or equal to a twenty-second preset threshold) and/or a module and/or a unit and/or design information corresponding to the twelfth identifier is an IP core called by the target chip and/or the information of the target chip and/or suspected to be called;

10.6, determining the position of the twelfth mark in the chip design layout and/or physical layout, and/or the region of the twelfth mark with the distance from the twelfth mark being less than or equal to a twenty-third preset threshold, and/or the position and/or the region (referring to the front side: in the chip design layout and/or physical layout and/or physical layout Or an area with a distance from the twelfth identifier smaller than or equal to a twenty-third preset threshold) and/or module and/or unit and/or design information corresponding to the twelfth identifier, determining the position and/or area of one or more layers and/or the module and/or unit and/or design information corresponding to the position and/or area of the one or more layers as an IP core called by the information of the target chip and/or suspected to be called; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold;

Optionally, wherein the twelfth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

10.7, determining modules and/or units and/or design information corresponding to a fourteenth area and/or a fourteenth area in the chip design layout and/or design layout, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-fourth preset threshold with respect to a thirteenth area of the layout and/or layout in a thirteenth preset library as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the thirteenth preset library does not contain the layout and/or layout wiring diagram designed by the design company of the target chip;

10.8, determining modules and/or units and/or design information corresponding to a sixteenth region and/or sixteenth region in the chip design layout and/or design layout, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-fifth preset threshold with respect to a fifteenth region of the layout and/or layout in a fourteenth preset library, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the fourteenth preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring and/or layout and wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

10.9, determining modules and/or units and/or design information corresponding to an eighteenth area and/or eighteenth area in the chip real object and/or real object layout and/or wiring diagram, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-sixth preset threshold in a fifteenth preset library, as an IP core for information calling and/or suspected calling of the target chip and/or the target chip; the fifteenth preset library does not contain a layout and/or a wiring layout designed by a design company of the target chip;

10.10, determining a module and/or unit and/or design information corresponding to a twentieth area and/or a twentieth area in the chip real object and/or real object layout and/or layout diagram, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-seventh preset threshold with respect to a nineteenth area in a sixteenth preset library, as an IP core for information calling and/or suspected calling of the target chip and/or the target chip; the sixteenth preset library is a layout and/or routing and/or layout-wiring pattern designed for the design company of the target chip, and/or a layout and/or layout-wiring pattern IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

10.11, calling and/or suspected to be called chip real objects and/or real object layout and/or layout of the IP core determined as the target chip and/or the target chip, and/or the module and/or unit and/or design information corresponding to the position and/or the area, and determining the position and/or area of the corresponding chip design layout and/or design information, and/or the module and/or unit and/or design information corresponding to the position and/or area as the IP core called and/or suspected called by the information of the target chip and/or the target chip.

optionally, the determining information of the target chip and/or the target chip, and the calling and/or suspected calling IP cores according to the second information include, but are not limited to, one or more of the following 11.1 to 11.6:

11.1, determining the position and/or the area of the thirteenth mark in the schematic diagram of the chip and/or the area of which the distance from the thirteenth mark is less than or equal to a twenty-eighth preset threshold, and/or the position and/or the area (referring to the front: the position and/or the area of the thirteenth mark in the schematic diagram of the chip and/or the area of which the distance from the thirteenth mark is less than or equal to the twenty-eighth preset threshold) and/or the module and/or unit and/or design information corresponding to the thirteenth mark is the IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the thirteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

11.2, determining the position and/or the area of the fourteenth identifier in the schematic diagram of the chip and/or the area whose distance from the fourteenth identifier is less than or equal to a twenty-ninth preset threshold, and/or the position and/or the area (referring to the front side: the position and/or the area of the fourteenth identifier in the schematic diagram of the chip and/or the area whose distance from the fourteenth identifier is less than or equal to the twenty-ninth preset threshold) and/or the module and/or unit and/or design information corresponding to the fourteenth identifier is the IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the fourteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

11.3, determining modules and/or units and/or design information corresponding to a twenty-second area and/or a twenty-second area in the schematic diagram of the chip, which are the same as and/or similar to the twenty-first area of the schematic diagram in a seventeenth preset library and/or have the similarity larger than or equal to a thirty-first preset threshold, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the seventeenth preset library does not contain a schematic diagram designed by a design company of the target chip;

11.4, determining modules and/or units and/or design information corresponding to a twenty-fourth area and/or a twenty-fourth area in the schematic diagram of the chip, which are the same as and/or similar to a twenty-third area of the schematic diagram in an eighteenth preset library and/or have similarity greater than or equal to a thirty-first preset threshold, as IP cores for information calling and/or suspected calling of the target chip and/or the target chip; the eighteenth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

11.5, according to a schematic diagram of a chip and a chip design layout and/or design layout diagram, performing one or more times of LVS verification by using one or more LVS verification software and/or tools and/or environments, and determining an IP core for information calling and/or suspected calling of the target chip and/or the target chip according to the result and/or report of the failed LVS verification;

it should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. In one example, for the verification object, if the verification passes in one set of LVS verification environment, but not in another set of LVS verification environment, the IP core can be determined according to the latter.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to failed schematic diagram areas, and/or failed chip design layouts and/or design layout area, and/or failed areas (referring to the former: failed schematic diagram areas, and/or failed chip design layouts and/or design layout and layout area) in verification as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; determining the difference of the device and/or connection relation in the schematic diagram found in the verification and the device and/or connection relation in the chip design layout and/or design layout and wiring diagram, and/or a schematic diagram area corresponding to the difference, and/or a chip design layout and/or design layout and wiring diagram area, and/or a module, and/or a unit, and/or design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

11.6, according to the schematic diagram of the chip and the chip design layout and/or wiring diagram, after modifying one or part of the number or all of the module and/or unit names, using one or more LVS verification software and/or tools and/or environments to perform one or more times of LVS verification, and determining the result and/or report of failed LVS verification, and determining the IP core of the target chip and/or the information call and/or suspected call of the target chip;

it should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. As an example, for the verification object, if the verification object passes through the one set of LVS verification environment, but does not pass through the other set of LVS verification environment, the IP core may be determined according to the latter) (it should be noted that, if the determined IP core happens to be a module and/or unit whose name is modified during verification, the module and/or unit is IP before and after modifying the name.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to failed schematic diagram areas, and/or failed chip design layouts and/or design layout areas, and/or failed areas (referring to the former: failed schematic diagram areas, and/or failed chip design layouts and/or design layout areas) in verification as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; determining the difference of the devices and/or the connection relations in the schematic diagram found in the verification and the device and/or the connection relations in the chip design layout and/or the design layout area, and/or the module, and/or the unit, and/or the design information corresponding to the difference, and/or the schematic diagram area, and/or the chip design layout and/or the design layout area, and/or the module, and/or the unit, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip.

Optionally, the second information includes a netlist of a chip transistor level, and/or a chip design layout and/or a design layout pattern;

optionally, the netlist of the transistor level includes, but is not limited to, one or more of the following: the description is a netlist at a transistor level, a netlist at a transistor level corresponding to a chip schematic diagram, a netlist at a transistor level corresponding to a gate-level netlist of a final design completed by a chip, a netlist at a transistor level corresponding to a chip design layout and/or design layout diagram, and a netlist at a transistor level consisting of a netlist at a transistor level corresponding to a gate-level netlist of a final design completed by an analog module schematic diagram and/or a digital module in an analog-digital hybrid chip;

it should be noted that the transistor-level netlist refers to a netlist describing a transistor level (including devices such as transistors, capacitors, resistors, and the like), and the form is various, such as an cdl netlist, an scs netlist, a spice netlist, and the like.

Optionally, the determining information of the target chip and/or the target chip, and the calling and/or suspected calling IP cores according to the second information include, but are not limited to, one or more of the following 12.1 to 12.6:

12.1, determining the position of the fifteenth mark in the netlist of the chip transistor level and/or the part of the fifteenth mark with the code length between the fifteenth mark and the fifteenth mark with less than or equal to the thirty-second preset threshold and/or the part of the chip transistor level with the code length between the fifteenth mark and the fifteenth mark with less than or equal to the first proportional threshold, and/or determining the position and/or the part (referring to the former part: the position of the fifteenth mark in the netlist of the chip transistor level and/or the part of the fifteenth mark with the code length between the fifteenth mark and the fifteenth mark with less than or equal to the thirty-second preset threshold and/or the part of the code length between the fifteenth mark and the netlist of the chip transistor level with less than or equal to the first proportional threshold) and/or determining the module and/or unit and/or design information corresponding to the fifteenth mark The information is the target chip and/or the IP core called by the information of the target chip and/or suspected calling; the fifteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

12.2, determining the position of the sixteenth mark in the netlist of the chip transistor level and/or the part of the sixteenth mark and/or the part of the code length between the sixteenth mark and the sixteenth mark, which is less than or equal to a thirty-third preset threshold, and/or the part of the code length between the sixteenth mark and the netlist of the chip transistor level, which has a ratio of less than or equal to a second proportional threshold, in the netlist of the chip transistor level, and/or the position and/or the part (referring to the former part: the position of the sixteenth mark in the netlist of the chip transistor level and/or the part of the sixteenth mark and/or the part of the code length between the sixteenth mark and the sixteenth mark, which has a ratio of less than or equal to the second proportional threshold) and/or the module and/or the unit and/or the design information corresponding to the sixteenth mark The information is the IP core called and/or suspected to be called by the target chip and/or the information of the target chip; the sixteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

12.3, determining modules and/or units and/or design information corresponding to a sixteenth part and/or a sixteenth part in the netlist of the transistor level, which are the same as and/or similar to a fifteenth part of the netlist of the transistor level in a nineteenth preset library and/or have a similarity greater than or equal to a thirty-fourth preset threshold, as IP cores called and/or suspected to be called by the target chip and/or the target chip; the nineteenth preset library does not contain a transistor-level netlist designed by a design company of the target chip;

12.4, determining modules and/or units and/or design information corresponding to an eighteenth part and/or an eighteenth part in the netlist of the transistor level, which are the same as and/or similar to a seventeenth part of the netlist of the transistor level in a twentieth preset library and/or have the similarity greater than or equal to a thirty-fifth preset threshold, as IP cores called by the information of the target chip and/or the target chip; a netlist of a transistor level designed for a design company of the target chip and/or a netlist IP core library of a transistor level of a design company of the target chip and/or an IP core library of a design company of the target chip in the twentieth preset library;

12.5, according to a netlist and a chip design layout and/or a design layout pattern of a chip transistor level, using one or more LVS verification software and/or tools and/or environments to perform one or more LVS verification, and determining the result and/or report of failed LVS verification, and determining the target chip and/or the IP core which is called by the target chip information and/or the target chip;

it should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. In one example, for the verification object, if the verification passes in one set of LVS verification environments, but the verification does not pass in another set of LVS verification environments, the IP core may be determined according to the latter.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to the failed transistor-level netlist part, and/or the failed chip design layout and/or design layout pattern region, and/or the failed part and/or the failed region (referring to the previous failed transistor-level netlist part, and/or the failed chip design layout and/or design layout pattern region) in the verification as IP cores called and/or suspected to be called for the information of the target chip and/or the target chip; determining the device and/or connection relation in the transistor-level netlist found in the verification, and the transistor-level netlist part corresponding to the difference and/or the difference between the device and/or connection relation in the chip design layout and/or design layout area, and/or module, and/or unit, and/or design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

12.6, according to the netlist and the chip design layout and/or design layout, after one or part of the number or all of the module(s) and/or unit(s) names are modified, performing LVS verification for one or more times by using one or more LVS verification software and/or tools and/or environments, and determining the IP core(s) of the target chip and/or the information call and/or suspected call of the target chip according to the result and/or report of the failed LVS verification;

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to the failed transistor-level netlist part, and/or the failed chip design layout and/or design layout pattern region, and/or the failed part and/or the failed region (referring to the previous failed transistor-level netlist part, and/or the failed chip design layout and/or design layout pattern region) in the verification as IP cores called and/or suspected to be called for the information of the target chip and/or the target chip; and determining the difference of the device and/or connection relation in the transistor-level netlist found in the verification and the device and/or connection relation in the chip design layout and/or design layout-wiring diagram, and/or the transistor-level netlist part corresponding to the difference, and/or the chip design layout and/or design layout-wiring diagram area, and/or the module, and/or the unit, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip.

Optionally, the second information includes a gate-level netlist of the chip, and/or a chip design layout and/or a design place and route pattern;

optionally, the gate-level netlist of the chip includes, but is not limited to, one or more of the following: a gate-level netlist, a gate-level netlist corresponding to the chip design layout and/or design layout pattern, a gate-level netlist formed by integrating RTL codes of the chip, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process are finally designed; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

optionally, the determining information of the target chip and/or the target chip, and the calling and/or suspected calling IP cores according to the second information include, but are not limited to, one or more of the following 13.1 to 13.11:

13.1, determining the position of the seventeenth mark in the gate-level netlist of the chip and/or the part of the seventeenth mark with a code length smaller than or equal to a thirty-sixth preset threshold and/or the part of the seventeenth mark with a code length smaller than or equal to a third proportional threshold in the gate-level netlist of the chip, and/or determining the position and/or the part (referring to the former part: the position of the seventeenth mark in the gate-level netlist of the chip and/or the part of the seventeenth mark with a code length smaller than or equal to a thirty-sixth preset threshold and/or the part of the seventeenth mark with a code length smaller than or equal to a third proportional threshold in the gate-level netlist of the chip) and/or determining the module and/or the unit and/or the design information corresponding to the seventeenth mark as the target chip And/or the information of the target chip calls and/or suspected called IP core; the seventeenth mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

13.2, determining the position of the eighteenth mark in the gate-level netlist of the chip and/or the part of the eighteenth mark with a code length between the eighteenth mark and the eighteenth mark being less than or equal to a thirty-seventh preset threshold and/or the part of the gate-level netlist of the chip with a code length between the eighteenth mark and the eighteenth mark being less than or equal to a fourth proportional threshold, and/or determining the position and/or the part (referring to the former part: the position of the eighteenth mark in the gate-level netlist of the chip and/or the part of the eighteenth mark and/or the part of the gate-level netlist of the chip with a code length between the eighteenth mark and the eighteenth mark being less than or equal to a thirty-seventh preset threshold and/or the part of the code length between the eighteenth mark and the gate-level netlist of the chip being less than or equal to the fourth proportional threshold) and/or determining the module and/or the unit and/or the design information corresponding to the eighteenth mark as the target chip And/or the information of the target chip calls and/or suspected called IP core; the eighteenth mark is a mark of a design company of the target chip and/or a mark representing the design company of the target chip;

13.3, determining modules and/or units and/or design information corresponding to the twentieth part and/or the twentieth part in the gate-level netlist of the chip, which are the same as and/or similar to the nineteenth part and/or have the similarity greater than or equal to a thirty-eighth preset threshold, as the IP cores of the target chip and/or the information call and/or the suspected call of the target chip; the twenty-first preset library does not contain a gate-level netlist designed by a design company of the target chip;

13.4, determining modules and/or units and/or design information corresponding to a twenty-second part and/or a twenty-second part in the gate-level netlist of the chip, which are the same as and/or similar to a twenty-first part of the gate-level netlist in a twenty-second preset library and/or have the similarity greater than or equal to a thirty-ninth preset threshold, as the target chip and/or the IP core which is called by the target chip information call and/or the target chip is suspected to be called; a gate-level netlist designed for a design company of the target chip, and/or a gate-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the twenty-second preset library;

13.5, according to a gate-level netlist of a chip and a chip design layout and/or design layout pattern, performing one or more LVS verification for one or more times by using one or more LVS verification software and/or tools and/or environments, and determining the result and/or report of the failed LVS verification, and determining an IP core called and/or suspected to be called by information of the target chip and/or the target chip;

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining a module and/or unit and/or design information corresponding to the failed gate-level netlist part, and/or the failed chip design layout and/or design layout pattern region, and/or the failed part and/or the failed region (referring to the previous failed gate-level netlist part, and/or the failed chip design layout and/or design layout pattern region) in verification as an IP core called and/or suspected to be called for the information of the target chip and/or the target chip; determining the difference between the device and/or connection relation in the gate-level netlist found in the verification and the device and/or connection relation in the chip design layout and/or design layout corresponding to the difference, and/or the gate-level netlist portion corresponding to the difference, and/or the chip design layout and/or design layout area, and/or the module, and/or the cell, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

13.6, according to the gate-level netlist and the chip design layout and/or layout, after one or part of the number or all of the module(s) and/or unit(s) names are modified, performing one or more LVS verification(s) by using one or more LVS verification software and/or tools and/or environments, and determining the IP core(s) of the target chip and/or the information call and/or suspected call of the target chip according to the result and/or report of the failed LVS verification;

it should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. As an example, for the verification object, if the verification passes in one set of LVS verification environments, but the verification does not pass in another set of LVS verification environments, the IP core may be determined according to the latter) (it should be noted that, if the determined IP core is exactly the module and/or unit whose name is modified during verification, the module and/or unit is IP before and after modifying the name.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to the failed gate-level netlist part, and/or the failed chip design layout and/or design layout pattern region, and/or the failed part and/or the failed region (referring to the previous failed gate-level netlist part, and/or the failed chip design layout and/or design layout pattern region) in verification as the IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; determining the difference between the device and/or connection relation in the gate-level netlist found in the verification and the device and/or connection relation in the chip design layout and/or design placement and routing diagram, and/or the gate-level netlist part corresponding to the difference, and/or the chip design layout and/or design placement and routing diagram area, and/or the module, and/or the unit, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

13.7, after the gate-level netlist of the chip is converted into the netlist of the chip transistor level, the converted netlist of the chip transistor level and the chip design layout and/or design layout wiring diagram are used for carrying out LVS verification for one or more times by using one or more LVS verification software and/or tools and/or environments, and determining the IP core of information calling and/or suspected calling of the target chip and/or the target chip;

it should be noted that, the LVS verification environment may be: the EDA environment including LVS verification includes one EDA software environment for design, simulation and verification and one LVS verification in the environment. In one example, for the verification object, if the verification passes in one set of LVS verification environment, but the verification fails in another set of LVS verification environment, the IP core is determined according to the latter.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining the failed transistor-level netlist part in the verification and/or the gate-level netlist part corresponding to the failed transistor-level netlist part, and/or IP cores which are called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or unit and/or design information corresponding to the failed chip design layout and/or design layout pattern area and/or the failed part and/or the failed area (refer to the former: failed transistor-level netlist part and/or the gate-level netlist part corresponding to the failed transistor-level netlist part and/or the failed chip design layout and/or design layout pattern area); determining the difference of the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference, the gate-level netlist part corresponding to the transistor-level netlist part corresponding to the gate-level netlist part, the gate-level netlist part corresponding to the chip design layout and/or design layout pattern region, the module, the cell and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

13.8, after the gate-level netlist of the chip is converted into the netlist of the chip transistor level, the converted netlist of the chip transistor level and the chip design layout and/or design layout wiring diagram, after one or part of the number of the modules and/or the names of all the cells are modified, the result and/or report of failed LVS verification in one or more LVS verification processes by using one or more LVS verification software and/or tools and/or environments are used, and the IP core of the information call and/or suspected call of the target chip and/or the target chip is determined;

it should be noted that, the LVS verification environment may be: a set of EDA environment including LVS verification, such as a set of EDA software environment capable of being designed, simulated and verified, is directly used for LVS verification in the whole set of environment. As an example, for the verification object, if the verification passes in one set of LVS verification environments, but the verification does not pass in another set of LVS verification environments, the IP core may be determined according to the latter) (it should be noted that, if the determined IP core is exactly the module and/or unit whose name is modified during verification, the module and/or unit is IP before and after modifying the name.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining the failed transistor-level netlist part in the verification and/or the gate-level netlist part corresponding to the failed transistor-level netlist part, and/or IP core for calling and/or suspected calling for information of the target chip and/or the target chip by the module and/or unit and/or design information corresponding to the failed chip design layout and/or design placement and/or layout pattern area and/or failed part and/or failed area (referring to the former: failed transistor-level netlist part and/or the gate-level netlist part corresponding to the failed transistor-level netlist part and/or the failed chip design layout and/or design placement and layout area); determining the difference of the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference and/or the gate-level netlist part corresponding to the transistor-level netlist part, the gate-level netlist part corresponding to the corresponding chip design layout and/or design layout area, and/or a module, and/or a cell, and/or design information corresponding to the transistor-level netlist part, and/or the IP core called and/or suspected to be called for the information of the target chip and/or the target chip;

13.9, according to the gate-level netlist of the chip and the chip design layout and/or design placement wiring diagram, modifying one or part of the number or all of the names of the modules and/or units, converting the modified gate-level netlist into a chip transistor-level netlist, performing one or more LVS verification in one or more LVS verification software and/or tools and/or environments on the converted chip transistor-level netlist and the modified chip design layout and/or design layout diagram, and determining the result and/or report of the failed LVS verification, and determining the target chip and/or the IP core called by the target chip information;

13.10, according to two gate-level netlists of the chip, using one or more formal verification software and/or tools and/or environments to perform one or more times of results and/or reports of formal verification in a failed formal verification process, and determining the target chip and/or an IP core which is called by information and/or suspected to be called by the target chip;

it should be noted that the two gate level netlists may be any two, and/or two, of one or more of the following, including but not limited to: the final design is completed, and the final design is completed by using the gate-level netlist, the chip design layout and/or the design layout pattern corresponding to the gate-level netlist, the gate-level netlist formed by synthesizing the chip register transfer level RTL codes, the front-end gate-level netlist, the back-end gate-level netlist, and the gate-level netlist in the chip design process, wherein the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists.

It should be noted that the formal verification environment may be: the method comprises a set of EDA environments including formal verification, for example, a set of EDA software environments capable of being designed, simulated and verified, and formal verification is directly performed in the whole set of environments. In one example, for the authentication object, if authentication passes in one set of formal authentication contexts, but not in another set of formal authentication contexts, then the IP core may be determined from the latter.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining a failed gate-level netlist part in verification and/or a module and/or a unit and/or an IP core which is called and/or suspected to be called for the target chip and/or the information of the target chip by the design information corresponding to the failed part (referred to as the previous failed gate-level netlist part); determining a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or unit and/or design information corresponding to the part (referred to as the gate-level netlist part corresponding to the mismatch point found in verification) and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an inequivalence part found in verification, and/or a gate-level netlist part corresponding to the inequivalence part, and/or a module and/or unit and/or design information corresponding to the inequivalence part as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining the difference of logic and/or functions in the two gate-level netlists found in the verification, and/or the gate-level netlist part corresponding to the difference, and/or the module and/or unit and/or design information as the target chip and/or the IP core called by the information of the target chip and/or the target chip;

13.11, determining the IP core called by the information and/or suspected to be called by the target chip and/or the target chip according to two gate-level netlists of the chip, after modifying one or part of the number of the chips or the names of all the modules and/or units, and using one or more types of formal verification software and/or tools and/or environments to perform one or more times of formal verification and/or report of failed formal verification;

it should be noted that the two gate level netlists may be any two, and/or two, of one or more of the following, including but not limited to: the final design is completed, and the final design is completed by using the gate-level netlist, the chip design layout and/or the design layout pattern corresponding to the gate-level netlist, the gate-level netlist formed by synthesizing the chip register transfer level RTL codes, the front-end gate-level netlist, the back-end gate-level netlist, and the gate-level netlist in the chip design process, wherein the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process include but are not limited to one or more gate-level netlists. It should be noted that the formal verification environment may be: the method comprises a set of EDA environments including formal verification, for example, a set of EDA software environments capable of being designed, simulated and verified, and formal verification is directly performed in the whole set of environments. In one example, for the authentication object, if authentication passes in one set of formal authentication environments, but not in another set of formal authentication environments, then an IP core may be determined from the latter. It should be noted that, if the determined IP core is the module and/or unit whose name is modified just during verification, the module and/or unit is the IP before and after modifying the name.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining a failed gate-level netlist part in verification, and/or determining modules and/or units and/or design information corresponding to the failed part (referring to the previous failed gate-level netlist part in verification) as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or unit and/or design information corresponding to the part (referred to as the gate-level netlist part corresponding to the mismatch point found in verification) and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an inequivalence part found in verification, and/or a gate-level netlist part corresponding to the inequivalence part, and/or a module and/or unit and/or design information corresponding to the inequivalence part as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining the difference of logic and/or functions in the two gate-level netlists found in the verification, and/or the gate-level netlist part corresponding to the difference, and/or the module and/or unit and/or design information as the target chip and/or the IP core called by the information of the target chip and/or the target chip;

Optionally, when performing formal verification, if there is a difference between the two gate-level netlists in the functions and/or logics of the auxiliary design and/or auxiliary test, the functions and/or logics corresponding to the difference are not verified or verified; for example, one gate-level netlist is a front-end netlist, one gate-level netlist is a back-end netlist, and a scan chain for testability design is added to the back-end netlist; otherwise, if the IP core detection is also needed, the verification is carried out; similarly, for other functions and/or logic, whether to verify may also be determined based on whether the focus of detection is for an IP core.

Optionally, the second information includes a chip RTL code, and/or a gate-level netlist of the chip;

optionally, the determining information of the target chip and/or the target chip, and the calling and/or suspected calling IP cores according to the second information include, but are not limited to, one or more of the following 14.1 to 14.7:

14.1, determining the position of the nineteenth mark in the chip RTL code and/or the part of the nineteenth mark and/or the part of the chip RTL code with the code length between the nineteenth mark and the nineteenth mark being less than or equal to a forty-th preset threshold and/or the part of the chip RTL code with the code length between the nineteenth mark and the nineteenth mark being less than or equal to a fifth proportion threshold, and/or determining the position and/or the part (referring to the former part: the position of the nineteenth mark in the chip RTL code and/or the part of the chip RTL code with the nineteenth mark being less than or equal to the forty-th preset threshold and/or the part of the chip RTL code with the code length between the nineteenth mark and the nineteenth mark being less than or equal to the fifth proportion threshold) and/or determining the module and/or unit and/or the design information corresponding to the nineteenth mark as the target chip and/or the target chip An IP core for information calling and/or suspected calling of the piece; the nineteenth mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

14.2, determining the position of the twentieth mark in the chip RTL code and/or the part of the twentieth mark and/or the part of the chip RTL code with the code length between the twentieth mark and the twentieth mark smaller than or equal to a forty-first preset threshold and/or the part of the chip RTL code with the code length between the twentieth mark and the twentieth mark smaller than or equal to a sixth ratio threshold, and/or determining the position and/or the part (referring to the former part: the position of the twentieth mark in the chip RTL code and/or the part of the chip RTL code with the code length between the twentieth mark and the part of the chip RTL code with the code length between the twentieth mark smaller than or equal to the forty-first preset threshold and/or the part of the chip RTL code with the code length between the twentieth mark and the sixth ratio threshold) and/or determining the module and/or the unit and/or the design information corresponding to the twentieth mark as the target chip and/or the target chip An IP core for information calling and/or suspected calling of the target chip; the twentieth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

14.3, determining the target chip and/or the IP core which is called by the information of the target chip and/or the suspected calling according to the part of the other level descriptions except the register transmission level description in the chip RTL code;

optionally, wherein the method of determining includes, but is not limited to, one or more of the following: determining one or more keywords existing in the chip RTL code, and/or determining keywords corresponding to the fact that the total quantity of the one or more keywords existing in the chip RTL code is greater than or equal to a forty-second preset threshold, and/or determining keywords corresponding to the fact that the proportion of the total quantity of the one or more keywords existing in the chip RTL code occupying the whole chip RTL code is greater than or equal to a forty-third preset threshold, and determining the positions and/or the parts of the keywords having the code length smaller than or equal to the forty-fourth preset threshold, and/or the positions and/or the parts (front: the positions and/or the parts of the keywords and/or the code length between the keywords and the parts of the keywords and/or the parts of the keywords is smaller than or equal to a forty-fourth preset threshold A part of a preset threshold and/or a part of a code length between the preset threshold and the keyword, in the chip RTL code, having a ratio smaller than or equal to a seventh ratio threshold) and/or a module and/or a unit and/or design information corresponding to the keyword are determined as an IP core for information call and/or suspected call of the target chip and/or the target chip, wherein the keyword is a keyword representing other level descriptions besides register transmission level descriptions, and the category of the keyword includes, but is not limited to, one or more of the following: code at a characterization description level, words and/or phrases at a characterization description level, scripts at a characterization description level, programs at a characterization description level, netlists at a characterization description level, wherein the netlists include, but are not limited to, gate-level netlists; determining modules and/or units and/or design information corresponding to a twenty-fourth part and/or a twenty-fourth part in the RTL code of the chip, which are the same as and/or similar to the twenty-third part of the gate-level netlist of the chip and/or have similarity greater than or equal to a forty-fifth preset threshold, as IP cores called by the information and/or suspected to be called of the target chip and/or the target chip;

14.4, determining modules and/or units and/or design information corresponding to a twenty-sixth part and/or a twenty-sixth part in the chip RTL codes, which are the same as and/or similar to a twenty-fifth part of the RTL codes in a twenty-third preset library and/or have similarity greater than or equal to a forty-sixth preset threshold, as IP cores for information calling and/or suspected calling of the target chip and/or the target chip; the twenty-third preset library does not contain the RTL code designed by the design company of the target chip;

14.5, determining modules and/or units and/or design information corresponding to a twenty-eighth part and/or a twenty-eighth part in the chip RTL code, which are the same as and/or similar to a twenty-seventh part of the RTL code in a twenty-fourth preset library and/or have a similarity greater than or equal to a forty-seventh preset threshold, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; an RTL code designed for a design company of the target chip and/or an RTL code IP core library of the design company of the target chip and/or an IP core library of the design company of the target chip in the twenty-fourth preset library;

14.6, according to a gate-level netlist of a chip RTL code and a chip, and results and/or reports of one or more formal verification tests and/or tools and/or environments, wherein the results and/or reports of the formal verification tests are not passed, determining the target chip and/or an IP core which is called and/or suspected to be called by the information of the target chip;

it should be noted that the formal verification environment may be: the method comprises a set of EDA environments including formal verification, for example, a set of EDA software environments capable of being designed, simulated and verified, and formal verification is directly performed in the whole set of environments. In one example, for the authentication object, if authentication passes in one set of formal authentication environments, but not in another set of formal authentication environments, then an IP core may be determined from the latter.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to failed RTL code parts and/or failed gate-level netlist parts in verification, and/or modules and/or units and/or design information corresponding to the failed parts (referring to the previous failed RTL code parts and/or failed gate-level netlist parts) as the target chip and/or the IP core which is called and/or suspected to be called by the information of the target chip; determining an RTL code part and/or a gate-level netlist part corresponding to the mismatch point found in the verification, and/or a module and/or a unit and/or a design information corresponding to the part (referring to the former RTL code part and/or the gate-level netlist part corresponding to the mismatch point) and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an inequivalent part found in verification, and/or an RTL code part corresponding to the inequivalent part, and/or a gate-level netlist part corresponding to the inequivalent part, and/or a module and/or unit and/or design information corresponding to the inequivalent part as an IP core for information call and/or suspected call of the target chip and/or the target chip; determining differences of logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist and/or corresponding RTL code parts, and/or gate-level netlist parts, and/or modules and/or units and/or design information in the verification to be IP cores called and/or suspected to be called by the target chip and/or the information of the target chip;

14.7, according to the gate-level netlist of the RTL code and the chip of the chip, after modifying one or a part of the number or all of the module and/or unit names, using one or more formal verification software and/or tools and/or environments to perform one or more times of formal verification, and determining the result and/or report of failed formal verification, and determining the target chip and/or the IP core which is called and/or suspected to be called by the information of the target chip;

it should be noted that the formal verification environment may be: the method comprises a set of EDA environments including formal verification, for example, a set of EDA software environments capable of being designed, simulated and verified, and formal verification is directly performed in the whole set of environments. In one example, for the verification object, if the verification passes in one set of formal verification environment, but if the verification fails in another set of formal verification environment, the IP core may be determined according to the latter) (it should be noted that, if the determined IP core happens to be a module and/or unit whose name is modified during verification, the module and/or unit is IP before and after modifying the name.

Optionally, the method of determining includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to failed RTL code parts and/or failed gate-level netlist parts in verification (referring to the former: failed RTL code parts and/or failed gate-level netlist parts) as IP cores called and/or suspected to be called by the target chip and/or the information of the target chip; determining an RTL code part and/or a gate-level netlist part corresponding to a mismatch point found in verification, and/or determining an IP core called and/or suspected to be called for the target chip and/or the information of the target chip by a module and/or a unit and/or design information corresponding to the part (the RTL code part and/or the gate-level netlist part corresponding to the mismatch point in the front) and/or the mismatch point; determining an inequivalence part found in verification, and/or an RTL code part and/or a gate-level netlist part corresponding to the inequivalence part, and/or a module and/or a unit and/or design information corresponding to the inequivalence part as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining differences of logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist, and/or RTL code portions corresponding to the differences, and/or gate-level netlist portions, and/or modules and/or units and/or design information, which are found in verification, as IP cores called and/or suspected to be called for the target chip and/or the information of the target chip;

Optionally, when performing formal verification, if there is a difference between the RTL code and the netlist in terms of functions and/or logics of the auxiliary design and/or auxiliary test, the function and/or logic corresponding to the difference is not verified or verified; for example, the gate-level netlist is a back-end netlist, and compared with an RTL code, a scan chain for testability design is added, and if it is considered that the scan chain is a function convenient for subsequent chip testing and is not used as a focus point for IP core detection, verification may not be performed; otherwise, if the IP core detection is also needed, the verification is carried out; similarly, for other functions and/or logic, whether to verify may also be determined based on whether the focus of detection is for an IP core.

optionally, the functional and/or logic and/or pins of the auxiliary design and/or auxiliary test include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

optionally, according to the first information, determining whether to call an IP core and/or determine whether to call the IP core, and when the IP core is suspected to be called, the preset thresholds and/or identifiers and/or preset libraries and/or areas and/or portions thereof used are the same or different, where the preset thresholds and/or identifiers and/or preset libraries and/or areas and/or portions thereof of the same type are the same or different;

optionally, according to the second information, it is determined that, of the target chip and/or the information of the target chip, the IP core called and/or suspected to be called, the preset threshold and/or the identifier and/or the preset library used and/or the area and/or the portion thereof, the preset thresholds and/or the identifiers and/or the preset libraries of the same type and/or the area and/or the portion thereof are the same or different.

optionally, wherein the non-self-research IP core includes, but is not limited to, one or more of the following: the IP core is not designed by the design company of the target chip, the IP core purchased by the design company of the target chip from other companies, the IP core called by the design company of the target chip from a non-self-research IP core library, and the IP core of which the intellectual property right does not belong to the design company of the target chip;

optionally, wherein the self-research IP core includes, but is not limited to, one or more of the following: the IP core designed by the design company of the target chip, the IP core independently developed by the design company of the target chip, the IP core owned by the design company of the target chip, the IP core accumulated by the design company of the target chip and the IP core of which the intellectual property belongs to the design company of the target chip.

Optionally, the method further comprises: determining whether the information of the target chip and/or the target chip, the called and/or suspected called IP core is a non-self-developed IP core and/or a self-developed IP core according to the first information and/or the second information and/or the information of the target chip and/or the design file of the target chip and/or the authorization data (including but not limited to IP core authorization data, chip self-authorization data, chip design company authorization data and the like) of the target chip; and/or

Optionally, while determining the information of the target chip and/or the target chip and calling and/or suspected calling IP cores according to the second information, determining whether the IP cores are non-self-research IP cores and/or self-research IP cores;

optionally, the method for determining that the target chip and/or the information, calling and/or suspected calling IP core of the target chip is a non-self-research IP core includes, but is not limited to, one or more of the following 17.1.1-17.1.10:

17.1.1, determining the IP core as a non-self-research IP core according to the content corresponding to the blank area and/or the blank area in the chip design layout and/or layout; (for example, consider a 10.1-deterministic IP core as a non-self-polishing IP core)

17.1.2, determining the IP core as a non-self-research IP core according to the inconsistency of the chip design layout and/or the comparison of the chip real object and/or the real object layout and/or the comparison of the inconsistency and the content corresponding to the inconsistency; (for example, consider an IP core of 10.2 determinations as a non-self-developed IP core)

17.1.3, determining the IP core as a non-self-developed IP core through the twenty-first identification in the third information of the target chip; the twenty-first mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip; (for example, consider 10.3 identified IP core as non self-research IP core, 10.4 identified IP core as non self-research IP core, 11.1 identified IP core as non self-research IP core, 12.1 identified IP core as non self-research IP core, 13.1 identified IP core as non self-research IP core, 14.1 identified IP core as non self-research IP core)

17.1.4, determining that the IP core is a non-self-research IP core according to the content corresponding to the twenty-sixth area and/or the twenty-sixth area in the third information of the target chip, which is the same as and/or similar to the twenty-fifth area of the information in the twenty-fifth preset library and/or has the similarity larger than or equal to the forty-eighth preset threshold; the twenty-fifth preset library does not contain the information designed by the design company of the target chip; (for example, consider 10.7 the identified IP core as a non-self-developed IP core, 10.9 the identified IP core as a non-self-developed IP core, and 11.3 the identified IP core as a non-self-developed IP core)

17.1.5, determining the IP core as a non-self-research IP core according to the content corresponding to the thirtieth part and/or the thirtieth part in the third information of the target chip, which is the same as and/or similar to the twenty-ninth part of the information in the twenty-sixth preset library and/or has the similarity larger than or equal to the forty-ninth preset threshold; the twenty-sixth preset library does not contain information designed by a design company of the target chip; (for example, consider 12.3 identified IP core as non-self-developed IP core, 13.3 identified IP core as non-self-developed IP core, and 14.4 identified IP core as non-self-developed IP core)

17.1.6, determining the IP core as the position and/or area of the chip design layout and/or design information corresponding to the IP core and/or the module and/or cell and/or design information corresponding to the position and/or area by determining the position and/or area of the chip real object and/or real object layout and/or design information corresponding to the IP core as the non-self-research IP core;

For example, in 10.11, the positions and/or areas of the chip physical and/or physical layouts of the non-self-researched IP cores determined as the target chip and/or the information calls and/or suspected calls of the target chip, and/or the modules and/or cells and/or design information corresponding to the positions and/or areas are/is determined, and determining the position and/or area of the corresponding chip design layout and/or design information, and/or the module and/or unit and/or design information corresponding to the position and/or area as the non-self-research IP core of the information call and/or suspected call of the target chip and/or the target chip.

17.1.7, performing one or more LVS verifications according to one or more LVS verification software and/or tools and/or environments, and reporting the result of failed LVS verification and/or determining that the IP core is a non-self-developed IP core; (for example, consider 11.5 determined IP core as a non-self-study IP core, 11.6 determined IP core as a non-self-study IP core, 12.5 determined IP core as a non-self-study IP core, 12.6 determined IP core as a non-self-study IP core, 13.5 determined IP core as a non-self-study IP core, 13.6 determined IP core as a non-self-study IP core, 13.7 determined IP core as a non-self-study IP core, 13.8 determined IP core as a non-self-study IP core, and 13.9 determined IP core as a non-self-study IP core)

17.1.8, performing one or more formal verification according to one or more formal verification software and/or tools and/or environments, failing the formal verification, and/or reporting that the determined IP core is a non-self-developed IP core; (for example, consider the IP core determined at 13.10 as a non self-research IP core, the IP core determined at 13.11 as a non self-research IP core, the IP core determined at 14.6 as a non self-research IP core, and the IP core determined at 14.7 as a non self-research IP core)

17.1.9, determining the IP core as a non-self-research IP core according to the other level descriptions except the register transmission level description in the chip RTL code; (for example, consider an IP core identified as 14.3 a non self-polishing IP core)

17.1.10, calling and/or suspected calling IP (Internet protocol) core aiming at the information of the target chip and/or the target chip, if the IP core is determined not to be the information of the target chip and/or the target chip, the called and/or suspected called self-research IP core, the IP core is the information calling and/or suspected called non-self-research IP core of the target chip and/or the target chip;

optionally, the method for determining that the target chip and/or the information, calling and/or suspected calling IP core of the target chip are self-research IP cores includes, but is not limited to, one or more of the following 17.2.1-17.2.5:

17.2.1, the IP core determined by the twenty-second identifier in the third information of the target chip is a self-research IP core; the twenty-second identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip; (for example, consider 10.5 identified IP core as self-research IP core, 10.6 identified IP core as self-research IP core, 11.2 identified IP core as self-research IP core, 12.2 identified IP core as self-research IP core, 13.2 identified IP core as self-research IP core, 14.2 identified IP core as self-research IP core)

17.2.2, determining that the IP core is a self-research IP core according to the content corresponding to the twenty-eighth area and/or the twenty-eighth area in the third information of the target chip, which is the same as and/or similar to the twenty-seventh area of the information in the twenty-seventh preset library and/or has the similarity larger than or equal to the fifty-fifth preset threshold; the twenty-seventh preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip; (for example, consider 10.8, 10.10, 11.4, and 14.5 as the respective IP cores of self-research.)

17.2.3, determining the IP core to be a self-research IP core according to the content corresponding to the thirty-second part and/or the thirty-second part in the third information of the target chip, which is the same as and/or similar to the thirty-first part of the information in the twenty-eighth preset library and/or has the similarity larger than or equal to the fifty-first preset threshold; the twenty-eighth preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip; (for example, consider 12.4 identified IP core as self-research IP core and 13.4 identified IP core as self-research IP core)

17.2.4, determining the IP core as the self-research IP core by determining the positions and/or areas of the chip real objects and/or real object layouts and/or real object layout and/real object layout area of the self-research IP core;

For example, in 10.11, the positions and/or areas of the chip entity and/or entity layout and/or layout of the self-researched IP core determined as the information call and/or suspected call of the target chip and/or the target chip, and/or the modules and/or units and/or design information corresponding to the positions and/or areas, and determining the position and/or area of the corresponding chip design layout and/or design information, and/or the module and/or unit and/or design information corresponding to the position and/or area as the information call and/or suspected called self-research IP core of the target chip and/or the target chip.

17.2.5, calling and/or suspected calling IP (Internet protocol) core aiming at the information of the target chip and/or the target chip, if the IP core is determined not to be the information of the target chip and/or the target chip, the called and/or suspected called non-self-research IP core, the IP core is the information calling and/or suspected called self-research IP core of the target chip and/or the target chip;

optionally, the third information of the target chip includes, but is not limited to, one or more of the following: the method comprises the following steps of designing a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a transistor-level netlist of the chip, a gate-level netlist of the chip, an RTL code of the chip, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information;

Optionally, the twenty-fifth preset library and/or the twenty-sixth preset library and/or the twenty-seventh preset library and/or the twenty-eighth preset library and/or the information designed by the design company of the target chip and/or the information in the information IP core library of the design company of the target chip, and the information type thereof includes, but is not limited to, one or more of the following: layout and/or place-and-route patterns, schematic diagrams, transistor-level netlists, gate-level netlists, RTL codes.

Optionally, the method further comprises: judging the degree of autonomy and/or controllability of the chip; the method of determination includes, but is not limited to, one or more of the following 18.1-18.15:

18.1, determining one or more fourth information required for determining the autonomy and/or controllability of the chip, wherein the fourth information comprises but is not limited to one or more of the following: a chip design layout and/or a design layout pattern, a chip real object and/or a real object layout pattern, a schematic diagram of a chip, a netlist at a chip transistor level, a gate-level netlist of the chip, a chip RTL code, all or part information of one or more kinds of information in the first information, all or part information of one or more kinds of information in the second information, and other information of the chip except the first information and the second information;

18.2, aiming at each kind of the one or more kinds of the required fourth information, distributing a score corresponding to the kind of the fourth information;

optionally, the method for assigning the score includes, but is not limited to: distributing scores according to the difficulty and/or the criticality of the realization and/or the design of each fourth information;

18.3, for each of said required fourth information, if all of said information of said chip to be determined is not contained in said obtained fourth information, and/or all functions and/or all logic and/or all blocks and/or all units of said chip to be determined are not contained in said obtained fourth information, and/or if a non-self-study IP core is called and/or suspected to be called in said obtained fourth information, said chip obtains a score of: subtracting the obtained score corresponding to the information part to be judged chip and/or the lacked function and/or the lacked logic and/or the lacked module and/or the lacked unit in the fourth information from the score corresponding to the called and/or suspected called non-self-researched IP core in the fourth information, and then remaining the score; and/or the chip obtains the score as follows: a score corresponding to the fourth information, a first ratio of the obtained scores corresponding to the information part to be judged chip and/or the function lacking and/or the logic lacking and/or the module lacking and/or the unit lacking in the fourth information, and a second ratio of the obtained scores corresponding to the called and/or suspected called IP core not in self-research;

Optionally, if the part of the information to be determined of the chip and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit in the obtained fourth information have repeated and/or overlapped contents with the non-self-researched IP core called and/or suspected to be called in the obtained fourth information, the score is reduced only once and/or not repeated and/or reduced for the repeated and/or overlapped contents;

optionally, the determination method of the first ratio and/or the second ratio includes, but is not limited to, one or more of the following: a ratio of less than or equal to 1, a ratio of greater than or equal to 0, a ratio of the missing information portion of the chip to be determined and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit when in country is less than or equal to a ratio when in non-country, a ratio of the called and/or suspected called non-self-study IP cores when in country is less than or equal to a ratio of the non-self-study IP cores when in non-country;

18.4, for each of said required fourth information, if the obtained fourth information includes all the information of said chip to be determined and/or includes all the functions and/or all the logics and/or all the modules and/or all the units of said chip to be determined, and the obtained fourth information does not call a non-self-research IP core and is not suspected to call a non-self-research IP core, the chip obtains the score as: the score corresponding to the fourth information;

18.5, aiming at each type of the required fourth information, if the type of the fourth information is not acquired and/or the acquired type of the fourth information cannot be confirmed to be the fourth information of the chip, the chip does not acquire a score under the type of the fourth information;

18.6, summing the actual scores obtained by the chip aiming at each of the one or more kinds of the required fourth information to serve as the total score of the chip, and judging the autonomy and/or the controllability of the chip through the total score;

18.7, in a case that the obtained fourth information does not include all the information of the chip to be determined and/or does not include all functions and/or all logics and/or all modules and/or all units of the chip to be determined, the non-self-developed IP core is called in other information after the fourth information is designed, and the function and/or logic and/or module and/or unit corresponding to the IP core is not designed in the fourth information;

18.8, when the scores corresponding to various fourth information are distributed aiming at the needed one or more kinds of fourth information, the chips with a given function need to be ensured to have the same score under different schemes and with the same degree of autonomy and/or controllability; the implementation method for ensuring that the scores corresponding to the same degree of autonomy and/or controllability are the same includes but is not limited to: under different schemes, the sum of the scores corresponding to the required various fourth information of a chip with a given function is the same;

For example 1, it is determined that the required fourth information is a chip real object, a chip design layout, a chip gate-level netlist and a chip RTL code, and the score of each fourth information is 25;

if the obtained chip gate-level netlist is found to lack the function of a module A, the score obtained by the chip in the gate-level netlist is 25 points of the RTL code, and the score of the module A (assumed to be 5 points) is 20 points;

finding that a non-self-developed IP core B is called in the obtained chip design layout, wherein the score obtained by the chip in the design layout is 25 points of the design layout, and the score of the non-self-developed IP core B (assumed to be 5 points) is 20 points;

finding that the obtained chip real object contains all the information of the chip to be judged and/or all the functions and/or all logics and/or all modules and/or all units of the chip to be judged, and the chip obtains a score of 25 points of the chip real object when the chip real object does not call a non-self-research IP core and is not suspected to call the non-self-research IP core;

if the RTL code is not obtained, the chip does not obtain a score in the RTL code;

the total score of the last chip is then 20 +25 to 65.

For example 2, it is determined that the required fourth information is a chip real object, a chip design layout, a chip gate-level netlist and a chip RTL code, and the score of each fourth information is 25;

Finding that the obtained gate-level netlist of the chip lacks the function of a module A, obtaining a score of the chip in the gate-level netlist, wherein the score is 25 minutes of the RTL code-the score of the module A (assumed to be 5 minutes) is 22 minutes, and the first ratio (assumed to be 0.6) is 22 minutes;

finding that a non-self-research IP core B is called in the obtained chip design layout, wherein the score obtained by the chip in the design layout is 25 minutes-the score of the non-self-research IP core B (assumed to be 5 minutes) is 23 minutes, namely, the second ratio (assumed to be 0.4);

finding that the obtained chip real object contains all the information of the chip to be judged and/or all the functions and/or all the logics and/or all the modules and/or all the units of the chip to be judged, and the chip obtains a score value of 25 points of the chip real object if the non-self-study IP core is not called and is not suspected to be called;

the total score of the last chip is then 70, with 22 +23 + 25.

For example 3, if more than one of the missing information portion of the decision chip and/or missing function and/or missing logic and/or missing module and/or missing unit, and/or calling and/or suspected calling non-self-research IP core is needed for a certain required fourth information, it is sufficient to continue to decrement.

For example 4, if there is more than one and there is a repetition of the missing part of the information to be determined for a certain required fourth information and/or the missing function and/or the missing logic and/or the missing block and/or the missing unit, and/or the calling and/or suspected calling non-self-research IP core, the repeated part is reduced by one when reduced, and the duplicate deduction is avoided. And for a different kind of required fourth information, there may be no such limitation if there is duplication between them.

For example 5, the second ratio of different IP cores, such as IP core C, IP core D, IP core E, etc., may be the same or different; likewise, the first ratio may be the same or different for different modules.

18.9, various functions and/or logics and/or modules and/or units determined to be required for determining the autonomy and/or controllability of the chip;

18.10, assigning, for each of said required functions and/or logics and/or modules and/or units, a score corresponding to such function and/or logic and/or module and/or unit;

optionally, the method for assigning the score includes, but is not limited to: assigning a score based on the ease and/or criticality of each function and/or logic and/or module and/or unit, implementation and/or design;

18.11, for each said required function and/or logic and/or module and/or unit, if said chip has no non-self-research IP core called and no suspected non-self-research IP core called in said function and/or logic and/or module and/or unit, said chip obtains the corresponding score for said function and/or logic and/or module and/or unit;

18.12, for each said required function and/or logic and/or module and/or unit, if said chip has called a non-self-research IP core and/or is suspected of having called a non-self-research IP core in said function and/or logic and/or module and/or unit to be determined, said chip does not obtain a score corresponding to said function and/or logic and/or module and/or unit, and/or said chip obtains a score corresponding to said function and/or logic and/or module and/or unit that is a third proportion of the score corresponding to said function and/or logic and/or module and/or unit;

optionally, the determination method of the third ratio includes, but is not limited to, one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, and the ratio of the called and/or suspected called non-self-researched IP core when the called and/or suspected called non-self-researched IP core is in a state is greater than or equal to the ratio of the called and/or suspected called non-self-researched IP core when the called and/or suspected called non-self-researched IP core is in a state;

18.13, for each of said required functions and/or logics and/or modules and/or units, if said chip is to be determined to lack such function and/or logic and/or module and/or unit, said chip does not obtain a score under such function and/or logic and/or module and/or unit;

18.14, summing the actual scores obtained by the chip for each function and/or logic and/or module and/or unit in the various required functions and/or logics and/or modules and/or units to serve as the total score of the chip, and judging the autonomy and/or controllability of the chip through the total score;

18.15, wherein, when the scores corresponding to the various functions and/or logics and/or modules and/or units are distributed for the various required functions and/or logics and/or modules and/or units, it is required to ensure that the scores corresponding to the chips of a given function are the same under different schemes and with the same degree of autonomy and/or controllability; the implementation method for ensuring that the scores corresponding to the same degree of autonomy and/or controllability are the same includes but is not limited to: the sum of the scores corresponding to the various functions and/or logics and/or modules and/or units required by a given function chip under different schemes is the same.

For example 1, determining various functions and/or logics and/or modules and/or units required for determining the autonomy and/or the controllability of the chip as a module 1, a module 2, a module 3 and a module 3, wherein the scores distributed by the module 1, the module 2, the module 3 and the module 3 are all 25 points;

finding that no non-self-grinding IP core is called and no suspected non-self-grinding IP core is called in a module 1 of the chip, wherein the chip obtains a score of 25 points corresponding to the module 1;

if the non-self-research IP core a is called in the module 2 of the chip, the chip obtains a score of a third ratio (assuming that the third ratio is 0.6 when a is domestic, 0 when a is non-domestic, and a is domestic in this example) of the score corresponding to the module 2, that is, 25 points is 0.6 to 15 points;

if the non-self-research IP core b is called in the module 3 of the found chip, the chip obtains a score of a third ratio of scores corresponding to the module 3 (assuming that the third ratio is 0.4 when b is domestic, 0 when b is non-domestic, and b is non-domestic in this example), that is, 25 points 0 to 0 points;

if the chip is found to lack the module 4, the chip does not obtain the score under the module 4;

the total score of the chip is 25 points +15 points +0 points to 40 points.

For example 2, the third ratio of different IP cores, such as IP core c, IP core d, IP core e, etc., may be the same or different.

Optionally, the score corresponding to the part of the information to be determined of the chip and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit in the obtained fourth information, and/or the score corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information, includes but is not limited to one or more of the following 19.1-19.3:

19.1, aiming at the needed fourth information, distributing scores corresponding to various functions and/or logics and/or modules and/or units aiming at various functions and/or logics and/or modules and/or units, wherein the sum of the scores corresponding to various functions and/or logics and/or modules and/or units is the score corresponding to the fourth information;

19.2, finding out information parts and/or functions and/or logics and/or modules and/or units of chips to be judged which are lacked in the acquired fourth information, wherein the scores or the sum of the scores distributed by the parts of functions and/or logics and/or modules and/or units are the scores corresponding to the information parts of chips to be judged which are lacked in the acquired fourth information and/or the lacked functions and/or logics and/or modules and/or units;

19.3, finding out functions and/or logics and/or modules and/or units corresponding to the called and/or suspected called non-self-researched IP cores in the obtained fourth information from various functions and/or logics and/or modules and/or units in the needed fourth information, wherein the sum of the scores or the scores distributed by the parts of functions and/or logics and/or modules and/or units is the score corresponding to the called and/or suspected called non-self-researched IP cores in the obtained fourth information.

Optionally, the method further comprises: confirming that the obtained information is the information of the target chip;

optionally, the information includes, but is not limited to, one or more of the following: the method comprises the following steps of designing a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a transistor-level netlist of the chip, a gate-level netlist of the chip, an RTL code of the chip, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information; other information of the chip except the first information and the second information;

Optionally, the method of confirmation includes, but is not limited to, one or more of the following 20.1-20.4:

20.1, the obtained information, the information that has been declared or identified as the target chip;

20.2, determining the obtained chip real object and/or real object layout and/or wiring diagram as the information of the target chip;

20.3, comparing and/or verifying the acquired information to confirm whether the acquired information is the information of the target chip, wherein the information includes but is not limited to one or more of the following: comparing and/or verifying the acquired information with information declared or identified as the target chip for one or more times, wherein if the comparison and/or verification is passed, the acquired information is the information of the target chip; comparing and/or verifying the acquired information with a chip real object and/or a real object layout, wherein if the comparison and/or verification is passed, the acquired information is the information of the target chip;

and 20.4, carrying out one or more times of comparison and/or verification on the acquired information and the information which is confirmed to be the target chip through comparison and/or verification, wherein if the comparison and/or verification is passed, the acquired information is the information of the target chip.

Optionally, the alignment and/or validation includes, but is not limited to, one or more of the following 21.1-21.16:

21.1, comparing a chip design layout and/or a design layout with a chip real object and/or a real object layout;

21.2, comparing the chip design layout and/or design layout pattern with a chip real object and/or real object layout pattern, removing the part and/or area and/or module and/or unit of the non-self-research IP core which is confirmed to be called or suspected to be called by the target chip, and comparing the rest chip design layout and/or design layout pattern with the rest chip real object and/or real object layout pattern;

21.3, performing LVS verification on the schematic diagram of the chip and the chip design layout and/or design layout and wiring diagram;

21.4, performing LVS verification on the schematic diagram of the chip, the design layout and/or the design layout diagram of the rest chip after removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip;

21.5, performing LVS verification on the netlist of the chip transistor level and the chip design layout and/or the design layout pattern;

21.6, after removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-research IP core which is confirmed to be called or suspected to be called by the target chip, performing LVS verification on the netlist of the rest chip transistor level and the rest chip design layout and/or the design layout;

21.7, performing LVS verification on the gate-level netlist of the chip and the chip design layout and/or the design layout and wiring diagram;

21.8, performing LVS verification on the gate-level netlist of the rest chip, and the rest chip design layout and/or layout after removing the part and/or region and/or module and/or unit and/or design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip;

21.9, after converting the gate-level netlist of the chip into a chip transistor-level netlist, performing LVS verification on the converted chip transistor-level netlist and a chip design layout and/or a design layout pattern;

21.10, after converting the gate-level netlist of the chip into a chip transistor-level netlist, and then connecting the converted chip transistor-level netlist with the chip design layout and/or design layout and wiring, and after removing the part and/or area and/or module and/or unit and/or design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip, performing LVS verification on the remaining chip transistor-level netlist, and the remaining chip design layout and/or design layout wiring;

21.11, removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-research IP core which is confirmed to be called or suspected to be called by the target chip, converting the rest gate-level netlist into a transistor-level netlist, and performing LVS verification on the converted transistor-level netlist and the rest chip design layout and/or design layout;

21.12, performing formal verification on one gate-level netlist of the chip and the other gate-level netlist of the chip;

21.13, removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-research IP core which is confirmed to be called or suspected to be called of the target chip from the gate-level netlist of the chip and the other gate-level netlist of the chip, and performing formal verification on the gate-level netlist of the rest chip and the other gate-level netlist of the rest chip;

21.14, performing formal verification on the RTL code of the chip and the gate-level netlist of the chip;

21.15, removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-research IP core which is confirmed to be called or suspected to be called by the target chip from the RTL code of the chip and the gate-level netlist of the chip, and performing formal verification on the RTL code of the rest chip and the gate-level netlist of the rest chip;

21.16, when the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or the auxiliary test are different between the two verified gate-level netlists and/or between the verified RTL code and the gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified;

Optionally, including but not limited to one or more of the following 22.1-22.18:

22.1, the chip design layout and/or design place-and-route pattern, and/or the area in the chip design layout and/or design place-and-route pattern, including but not limited to all layers and/or part of layers and/or one layer of the chip design layout and/or design place-and-route pattern, for one layer, the chip design layout and/or design place-and-route pattern includes, but is not limited to, a chip design layout and/or design place-and-route pattern for an entire area and/or for a plurality of local areas and/or for one local area; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different;

22.2, the areas in the chip real object and/or real object layout wiring, including but not limited to all layers and/or partial layers and/or one layer of chip real object and/or real object layout wiring, for one layer, the chip real object and/or real object layout wiring include but not limited to the chip real object and/or real object layout wiring of the whole area and/or a plurality of local areas and/or one local area Or physical layout wiring and/or physical layout wiring diagram; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different;

22.3, regions in the layout and/or place-route, and/or layout and/or place-route in said preset library, including but not limited to all layers and/or part layers and/or one layer of the layout and/or place-route, for one of the layers, said layout and/or place-route including but not limited to the layout and/or place-route of the whole area and/or of a plurality of partial areas and/or of one partial area; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different;

22.4, a schematic diagram of the chip, and/or a region in a schematic diagram of a chip, including but not limited to a chip schematic diagram of an entire region and/or a plurality of partial regions and/or a partial region;

22.5 schematic diagrams in the preset library, and/or areas in the schematic diagrams, including but not limited to the schematic diagrams of the whole area and/or a plurality of local areas and/or one local area;

22.6, the chip transistor-level netlist, and/or portions of a transistor-level netlist, including but not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level;

22.7, a transistor-level netlist in the preset library, and/or a portion of a transistor-level netlist, including but not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level;

22.8, a gate level netlist of the chip, and/or portions of a gate level netlist, including but not limited to: the whole gate-level netlist and a part of gate-level netlist;

22.9, a gate level netlist in the preset library, and/or a portion of a gate level netlist, including but not limited to: the whole gate-level netlist and a part of gate-level netlist;

22.10, the chip RTL code, and/or portions of RTL code, including but not limited to one or more of: the whole RTL code, part of the RTL code, the RTL code claimed by the design company of the target chip, and the code designed by the design company of the target chip in the RTL design stage;

22.11, RTL code in the preset library, and/or portions of RTL code, including but not limited to: the whole RTL code and part of the RTL code;

22.12, said chip design layout and/or design place-and-route pattern including, but not limited to, one or more of: a comment and/or description in the chip design layout and/or design layout pattern;

22.13, the chip physical and/or physical layout and/or layout diagram includes but is not limited to one or more of the following: annotation and/or description in chip real object and/or real object layout wiring diagram;

22.14 schematic diagrams of the chip include, but are not limited to, one or more of: schematic diagram of the chip, comments and/or explanations in the schematic diagram of the chip;

22.15, netlist at the chip transistor level includes, but is not limited to, one or more of: a chip transistor-level netlist, annotations and/or descriptions in a chip transistor-level netlist;

22.16, the gate-level netlist of the chip includes, but is not limited to, one or more of: a gate-level netlist of the chip, comments and/or descriptions in the gate-level netlist of the chip;

22.17, the chip RTL code includes but is not limited to one or more of the following: chip RTL code, comments and/or descriptions in the chip RTL code;

22.18, the identification includes one or more of: text, graphics, trademarks, names, logos, indicia, watermarks.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a detection apparatus for IP core invocation according to a second embodiment of the present invention, where the detection apparatus 20 for IP core invocation includes:

the IP core calling judging module 21 is configured to determine whether to call an IP core and/or determine whether to call the suspected IP core in the target chip and/or the information of the target chip according to the first information;

the IP core call determining module 22 is configured to determine, according to the second information, information of the target chip and/or the target chip, and call and/or suspect-to-call an IP core;

In other optional specific embodiments, the apparatus 20 for detecting an IP core call may also include only the IP core call determining module 21, or only the IP core call determining module 22.

Optionally, the target chip is a whole or partial chip, and the types of the chips include but are not limited to one or more of the following: packaged chips, unpackaged dies, modules in a die, units in a die have been completed.

the IP core call judging module 21 includes, but is not limited to, one or more of the following:

the first judgment sub-module is used for judging whether a target chip and/or information of the target chip call an IP core and/or is suspected to call an IP core if a blank area and/or a blank area is larger than or equal to a first preset threshold and/or a blank area occupation ratio is larger than or equal to a second preset threshold and/or a blank area is a regular geometric figure; the blank area occupation ratio refers to a ratio of blank areas occupying the design layout and/or design placement and/or design layout, and the regular geometric figures include, but are not limited to, one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc;

A fourth judgment sub-module, configured to determine that an IP core is called and/or an IP core is suspected to be called in the target chip and/or the information of the target chip if a second identifier exists in the chip design layout and/or the chip physical layout and/or the physical layout; the second identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

a fifth judgment sub-module, configured to compare the chip design layout and/or design layout pattern with a layout and/or layout pattern in a first preset library, and if a first region in the chip design layout and/or design layout pattern is the same as and/or similar to and/or has a similarity greater than or equal to a third preset threshold with a second region in the layout and/or layout pattern in the first preset library, determine that an IP core is invoked by the information of the target chip and/or an IP core is suspected to be invoked; the first preset library does not contain the layout and/or the wiring and/or the layout and wiring diagram designed by the design company of the target chip;

A sixth judgment sub-module, configured to compare the chip design layout and/or design layout pattern with a layout and/or layout pattern in a second preset library, and if a third region in the chip design layout and/or design layout pattern is the same as and/or similar to and/or greater than or equal to a fourth preset threshold, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core; the second preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring and/or layout and/or wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

a seventh judging submodule, configured to arrange the chip in real objects and/or in real object layouts, comparing with the layout and/or layout of the chip in the third preset library, if the chip in the fifth area in the real object and/or real object layout and/or layout, the same and/or similar and/or similarity degree with the sixth area of the layout and/or place-and-route pattern in the third preset library is larger than or equal to a fifth preset threshold, determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core; the third preset library does not contain the layout and/or the wiring layout diagram designed by the design company of the target chip;

An eighth judging submodule, configured to arrange the chip in real objects and/or in real object layouts, comparing with the layout and/or layout of the chip in the seventh area of the real object and/or real object layout and/or layout of the chip in the fourth preset library, the same and/or similar and/or similarity degree with the eighth area of the layout and/or routings layout in the fourth preset library is larger than or equal to a sixth preset threshold, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip; and the fourth preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip.

a ninth determining sub-module, configured to determine that an IP core is called and/or an IP core is suspected to be called in the target chip and/or in the information of the target chip if a third identifier exists in the schematic diagram of the chip; the third identification is an identification of other companies except the design company of the target chip and/or an identification representing other companies except the design company of the target chip;

a tenth judging submodule, configured to determine that an IP core is called and/or an IP core is suspected to be called in the target chip and/or information of the target chip if a fourth identifier exists in the schematic diagram of the chip; the fourth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

A twelfth judging sub-module, configured to compare the schematic diagram of the chip with a schematic diagram in a sixth preset library, and if an eleventh area in the schematic diagram of the chip is the same as and/or similar to a twelfth area in the schematic diagram in the sixth preset library and/or a similarity degree of the eleventh area and/or the twelfth area is greater than or equal to an eighth preset threshold, determine that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the sixth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

a thirteenth judging submodule, configured to perform one or more LVS verifications with respect to the schematic diagram of the chip and the chip design layout and/or design layout diagram, using one or more LVS verification software and/or tools and/or environments, and if one or more LVS verifications fail, determining that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

a fourteenth determining submodule, configured to modify one or a part of the number of modules and/or names of all of the cells, and perform one or more LVS verifications using one or more LVS verification software and/or tools and/or environments after the modification, and if the one or more LVS verifications do not pass, determine that the information of the target chip and/or the target chip invokes the IP core and/or is suspected to invoke the IP core.

Optionally, the first information includes a netlist at a chip transistor level, and/or a chip design layout and/or a design layout pattern; the transistor-level netlist includes, but is not limited to, one or more of the following: the description is a netlist at a transistor level, a netlist at a transistor level corresponding to a chip schematic diagram, a netlist at a transistor level corresponding to a gate-level netlist of a final design completed by a chip, a netlist at a transistor level corresponding to a chip design layout and/or design layout diagram, and a netlist at a transistor level consisting of a netlist at a transistor level corresponding to a gate-level netlist of a final design completed by an analog module schematic diagram and/or a digital module in an analog-digital hybrid chip;

a fifteenth judgment sub-module, configured to determine that the target chip and/or the information of the target chip invokes an IP core and/or is suspected to invoke an IP core if a fifth identifier exists in the netlist of the chip transistor level; the fifth mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

A sixteenth determining sub-module, configured to determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core if a sixth identifier exists in the chip-transistor-level netlist; the sixth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

a seventeenth judging submodule, configured to compare the netlist of the chip transistor level with the netlist of the transistor level in a seventh preset library, and if a first part of the netlist of the chip transistor level is the same as a second part of the netlist of the transistor level in the seventh preset library and/or is similar to the second part of the netlist of the transistor level in the seventh preset library and/or has a similarity greater than or equal to a ninth preset threshold, determine that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; the seventh preset library does not contain a netlist of a transistor level designed by a design company of the target chip;

A nineteenth judgment sub-module, configured to perform one or more LVS verifications using one or more LVS verification software and/or tools and/or environments for the netlist of the chip transistor level and the chip design layout and/or the layout, and if one or more LVS verifications fail, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core;

a twenty-second judgment sub-module, configured to determine that the target chip and/or the information of the target chip invokes an IP core and/or is suspected to invoke an IP core if an eighth identifier exists in the gate-level netlist of the chip; the eighth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

A twenty-sixth judgment sub-module, configured to modify one or some number of the modules and/or names of all the modules and/or units according to the gate-level netlist of the chip and the chip design layout and/or layout diagram, perform one or more times of LVS verification using one or more types of LVS verification software and/or tools and/or environments after the modification, and determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core if one or more times of LVS verification fails;

a twenty-seventh judging submodule, configured to convert the gate-level netlist of the chip into a chip-transistor-level netlist, and then perform, for the converted chip-transistor-level netlist and the chip design layout and/or design layout pattern, one or more LVS verifications for one or more times using one or more LVS verification software and/or tools and/or environments, and if one or more LVS verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core;

A twenty-eighth judging submodule, configured to convert the gate-level netlist of the chip into a chip-transistor-level netlist, modify one or some of the numbers or names of all of the modules and/or cells for the converted chip-transistor-level netlist and the chip design layout and/or layout pattern, and perform one or more LVS verifications in one or more LVS verification software and/or tools and/or environments after the modification, and if the one or more LVS verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected of invoking an IP core;

a twenty-ninth judgment sub-module, configured to modify one or some or all of the module and/or cell names according to the gate-level netlist of the chip and the chip design layout and/or design layout, and then convert the modified gate-level netlist into a transistor-level netlist, and perform one or more LVS verifications in one or more LVS verification software and/or tools and/or environments according to the converted transistor-level netlist and the modified chip design layout and/or design layout, if one or more LVS verifications fail, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip;

a thirty-first judging submodule, configured to modify one or a part of the numbers of the modules and/or unit names or all of the module and/or unit names for two gate-level netlists of the chip, and perform one or more formal verifications using one or more formal verification software and/or tools and/or environments after the modification, and if the one or more formal verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core;

when the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the two gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logic and/or pins of the auxiliary design and/or auxiliary test include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

A thirty-fifth judging sub-module, configured to compare the chip RTL code with an RTL code in an eleventh preset library, and if an eleventh part of the chip RTL code is the same as a twelfth part of the RTL code in the eleventh preset library and/or is similar to the eleventh preset library and/or has a similarity greater than or equal to a sixteenth preset threshold, determine that the target chip and/or the information of the target chip has called an IP core and/or is suspected to call an IP core; the eleventh preset library does not contain an RTL code designed by a design company of the target chip;

a thirty-eighth judging sub-module, configured to modify one or a part of the number of the RTL codes of the chip and the gate-level netlist of the chip or names of all the modules and/or units, and perform one or more formal verifications in one or more formal verification software and/or tools and/or environments after the modification, and if any one or more formal verifications do not pass, determine that the information of the target chip and/or the target chip invokes an IP core and/or is suspected to invoke an IP core;

when the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the RTL code and the gate level netlist, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logic and/or pins of the auxiliary design and/or auxiliary test include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

the IP core call determination module 22 includes, but is not limited to, one or more of the following:

a first determining submodule for determining blank areas in the chip design layout and/or design layout, and/or blank areas with an area greater than or equal to an eighteenth preset threshold, and/or blank areas with an occupation ratio greater than or equal to a nineteenth preset threshold, and/or blank areas of regular geometric figures, and connecting the blank areas, and/or the design layout pattern corresponding to the blank area, and/or the module and/or the unit and/or the design information corresponding to the blank area are determined as the IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the occupation ratio refers to the proportion of the blank areas occupying the design layout and/or design layout, and the regular geometric figures include but are not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc; the blank area includes, but is not limited to, one or more areas;

A second determining submodule, configured to determine a mismatch between a chip design layout and/or a design layout diagram and a corresponding chip real object and/or a real object layout diagram when they are compared, and determine the mismatch, and the design layout and/or the design layout diagram corresponding to the mismatch, and/or the chip real object and/or the real object layout diagram corresponding to the mismatch, and/or the module and/or the unit and/or the design information corresponding to the mismatch as the information calling and/or the suspected calling and/or the design information of the target chip and/or the target chip An IP core for use; wherein the inconsistency includes, but is not limited to, one or more of the following: all layers and/or part of layers and/or one layer are inconsistent in comparison; all layers and/or part of layers and/or one layer, wherein the whole area and/or a plurality of local areas and/or one local area are in inconsistent alignment; the inconsistency places include but are not limited to one or more places of layout and/or place-and-route patterns;

a fifth determining submodule, configured to determine that a module and/or a unit and/or design information corresponding to a twelfth identifier calls and/or calls a suspected IP core for information of the target chip and/or the target chip, and/or determine that a suspected IP core is called and/or called for information of the target chip and/or the target chip, and/or a chip real object and/or a real object layout in a position where the twelfth identifier is located and/or a region where a distance from the twelfth identifier to the twelfth identifier is less than or equal to a twenty-second preset threshold;

a sixth determining submodule, configured to determine, after determining a position and/or a region where a twelfth tag is located and/or a region where a distance from the twelfth tag is less than or equal to a twenty-third preset threshold in a chip design layout and/or a design layout, and/or a physical layout, and/or determining, as the target chip and/or the target chip, the position and/or the region of one or more layers, and/or the module and/or the cell and/or the design information corresponding to the position and/or the region of the one or more layers The IP core is called and/or suspected to be called by the information of the target chip; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold;

a seventh determining submodule, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a cell and/or design information corresponding to a fourteenth region and/or a fourteenth region in the chip design layout and/or design layout, and/or design information corresponding to a thirteenth region, which is the same as, similar to, and/or has a similarity greater than or equal to a twenty-fourth preset threshold, of the layout and/or layout in a thirteenth preset library; the thirteenth preset library does not contain the layout and/or layout wiring diagram designed by the design company of the target chip;

an eighth determining submodule, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a cell and/or design information corresponding to a sixteenth region and/or a sixteenth region in the chip design layout and/or design layout, where the module and/or the cell and/or the design information is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-fifth preset threshold with respect to a fifteenth region in a layout and/or layout in a fourteenth preset library; the fourteenth preset library is a layout and/or a routing and/or a layout and/or a routing diagram designed for the design company of the target chip, and/or a layout and/or a routing diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

A ninth determining submodule, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to an eighteenth area and/or eighteenth area in the chip real object and/or real object layout and/or layout, where the seventeenth area is the same as, and/or similar to, and/or has a similarity greater than or equal to a twenty sixth preset threshold; the fifteenth preset library does not contain a layout and/or a wiring layout designed by a design company of the target chip;

a tenth determining submodule, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to a twentieth region and/or a twentieth region in the chip real object and/or real object layout and/or wiring diagram that is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-seventh preset threshold with respect to a nineteenth region of the layout and/or wiring diagram in a sixteenth preset library; the sixteenth preset library is a layout and/or routing and/or layout-wiring pattern designed for the design company of the target chip, and/or a layout and/or layout-wiring pattern IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

An eleventh determining sub-module, configured to determine a position and/or a region of a chip entity and/or an entity layout and/or an IP core suspected to be invoked for the information of the target chip and/or the target chip, and/or a module and/or a unit and/or design information corresponding to the position and/or the region, and determining the position and/or area of the corresponding chip design layout and/or design layout, and/or the module and/or unit and/or design information corresponding to the position and/or area as the IP core called and/or suspected to be called by the information of the target chip and/or the target chip.

a twelfth determining sub-module, configured to determine a location of a thirteenth identifier in the schematic diagram of the chip, and/or an area where the thirteenth identifier is located, and/or an area where a distance from the thirteenth identifier to the thirteenth identifier is smaller than or equal to a twenty-eighth preset threshold, and/or a module and/or a unit and/or design information corresponding to the location and/or the area and/or the thirteenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the thirteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

A fourteenth determining submodule, configured to determine a position where a fourteenth identifier is located in a schematic diagram of the chip and/or an area where the fourteenth identifier is located and/or an area where a distance from the fourteenth identifier to the fourteenth identifier is smaller than or equal to a twenty-ninth preset threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the area and/or the fourteenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the fourteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

a fifteenth determining submodule, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twenty-second area and/or a twenty-second area in the schematic diagram of the chip, where the module and/or the unit and/or the design information are the same as and/or similar to a twenty-first area of the schematic diagram in a seventeenth preset library and/or a similarity is greater than or equal to a thirty-first preset threshold; the seventeenth preset library does not contain a schematic diagram designed by a design company of the target chip;

a sixteenth determining sub-module, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twenty-fourth area and/or a twenty-fourth area in the schematic diagram of the chip, where the module and/or the unit and/or the design information are the same as and/or similar to a twenty-third area and/or have a similarity greater than or equal to a thirty-first preset threshold; the eighteenth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

A seventeenth determining submodule, configured to determine, according to a schematic diagram of a chip and a chip design layout and/or design layout diagram, an IP core for information call and/or suspected call of the target chip and/or the target chip in one or more LVS verifications performed using one or more LVS verification software and/or tools and/or environments, and a result and/or report of a failed LVS verification; the seventeenth determination submodule includes, but is not limited to, one or more of: the first determining unit is used for determining that modules and/or units and/or design information corresponding to failed schematic areas, failed chip design layouts and/or design layout areas, and/or failed areas call and/or suspected to call IP cores for the information of the target chip and/or the target chip; a second determining unit, configured to determine a difference between devices and/or connection relationships in the schematic found in the verification and device and/or connection relationships in the chip design layout and/or design layout, and/or schematic regions corresponding to the difference, and/or chip design layout and/or design layout regions, and/or modules, and/or cells, and/or design information, and invoke and/or suspect-to-invoke IP cores for information of the target chip and/or the target chip;

An eighteenth determining submodule, configured to determine, according to a schematic diagram of a chip and a chip design layout and/or design layout diagram, after modifying one or a part of the number of modules and/or all of the names of the modules and/or cells, in one or more times of LVS verification using one or more types of LVS verification software and/or tools and/or environments, and a result and/or report of failed LVS verification, an IP core for information invocation and/or suspected invocation of the target chip and/or the target chip; the eighteenth determining submodule includes, but is not limited to, one or more of: a third determining unit, configured to determine that a failed schematic area, and/or a failed chip design layout and/or design layout pattern area, and/or a module and/or a cell and/or design information corresponding to the failed area invoke and/or a suspected invoked IP core for the information of the target chip and/or the target chip; and the fourth determining unit is used for determining the device and/or connection relation in the schematic diagram found in the verification, and schematic diagram areas corresponding to the difference and/or the difference between the device and/or connection relation in the chip design layout and/or design layout, and/or chip design layout and/or design layout area, and/or module, and/or cell, and/or design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip.

A twentieth determining sub-module, configured to determine a position where a sixteenth identifier is located in the netlist of the chip transistor level and/or a portion where the sixteenth identifier is located and/or a portion where a code length between the sixteenth identifier and the sixteenth identifier is smaller than or equal to a thirty-third preset threshold and/or a portion where an occupation ratio of a code length between the sixteenth identifier and the netlist of the chip transistor level is smaller than or equal to a second ratio threshold, and/or a module and/or a unit and/or an IP core whose design information calls and/or is suspected to call the information of the target chip and/or the target chip, where the module and/or the unit and/or the design information corresponding to the position and/or the sixteenth identifier are/or modules and/or units and/or IP cores whose design information calls and/or is suspected to call the information of the target chip; the sixteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

A twenty-second determining sub-module, configured to determine, as an IP core called and/or suspected to be called by information of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to an eighteenth part and/or an eighteenth part in the netlist of the chip transistor level, where the seventeenth part is the same as and/or similar to and/or has a similarity greater than or equal to a thirty-fifth preset threshold; a netlist of a transistor level designed for a design company of the target chip and/or a netlist IP core library of a transistor level of a design company of the target chip and/or an IP core library of a design company of the target chip in the twentieth preset library;

a twenty-third determining submodule, configured to determine, according to a netlist of a chip transistor level and a chip design layout and/or a design layout pattern, a result and/or a report of failed LVS verification in one or more times of LVS verification performed using one or more LVS verification software and/or tools and/or environments, an IP core for information call and/or suspected call of the target chip and/or the target chip; the twenty-third determination sub-module includes, but is not limited to, one or more of: a fifth determining unit, configured to determine that the IP core called and/or suspected to be called by the information of the target chip and/or the target chip is the module and/or the cell and/or the design information corresponding to the failed transistor-level netlist portion, and/or the failed chip design layout and/or the design layout pattern area, and/or the failed portion and/or the failed area in the verification; a sixth determining unit, configured to determine the device and/or connection relationship in the transistor-level netlist found in the verification, and the transistor-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or design layout, and/or the transistor-level netlist portion corresponding to the difference, and/or the IP core called and/or suspected to be called for the information of the target chip and/or the target chip;

A twenty-fourth determining submodule, configured to determine, according to the netlist of the chip transistor level and the chip design layout and/or design layout pattern, after modifying one or a part of the number of modules and/or names of all of the modules and/or cells, an information-called and/or suspected-called IP core of the target chip and/or the target chip in one or more times of LVS verifications using one or more types of LVS verification software and/or tools and/or environments, and a result and/or a report of a failed LVS verification; the twenty-fourth determination submodule includes, but is not limited to, one or more of: a seventh determining unit, configured to determine an IP core called and/or suspected to be called for information of the target chip and/or the target chip by the module and/or cell and/or design information corresponding to the failed transistor-level netlist portion and/or the failed chip design layout and/or design layout pattern region and/or the failed portion and/or the failed region in the verification; and the eighth determining unit is used for determining the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference and/or the difference between the device and/or connection relation in the chip design layout and/or design layout-layout diagram, and/or the chip design layout and/or design layout-layout diagram area, and/or the module, and/or the cell, and/or the design information, and calling and/or suspected calling the IP core for the information of the target chip and/or the target chip.

Optionally, the second information includes a gate-level netlist of the chip, and/or a chip design layout and/or a design place and route pattern; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

A twenty-sixth determining sub-module, configured to determine a position where an eighteenth identifier is located in a gate-level netlist of a chip and/or a portion where a code length between the eighteenth identifier and the eighteenth identifier is smaller than or equal to a thirty-seventh preset threshold and/or a portion where a ratio of the code length between the eighteenth identifier and the gate-level netlist of the chip is smaller than or equal to a fourth ratio threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the portion and/or the eighteenth identifier is an IP core called and/or suspected to be called for information of the target chip and/or the target chip; the eighteenth mark is a mark of a design company of the target chip and/or a mark representing the design company of the target chip;

a twenty-seventh determining sub-module, configured to determine, as the target chip and/or the IP core called by the information of the target chip and/or suspected to be called, a module and/or a unit and/or design information corresponding to a twentieth part and/or a twentieth part of the gate-level netlist of the chip, where the module and/or the unit and/or the design information are the same as and/or similar to a nineteenth part of the gate-level netlist in the twenty-first preset library and/or have a similarity greater than or equal to a thirty-eighth preset threshold; the twenty-first preset library does not contain a gate-level netlist designed by a design company of the target chip;

a twenty-ninth determining submodule, configured to determine, according to a gate-level netlist of a chip and a chip design layout and/or design layout pattern, a result and/or a report of passing or failing LVS verification in one or more times of LVS verification using one or more LVS verification software and/or tools and/or environments, an IP core for information call and/or suspected call of the target chip and/or the target chip; the twenty-ninth determining sub-module includes, but is not limited to, one or more of: a ninth determining unit, configured to determine that the failed gate-level netlist portion in the verification, and/or the failed chip design layout and/or design layout pattern area, and/or the module and/or cell and/or design information corresponding to the failed portion and/or the failed area are/is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; a tenth determining unit, configured to determine the device and/or connection relationship in the gate-level netlist found in the verification, the gate-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or design layout, and/or the gate-level netlist portion corresponding to the difference, and/or the chip design layout and/or design placement and/or design layout area, and/or the module, and/or the cell, and/or the design information, and call and/or suspect-called IP cores for the information of the target chip and/or the target chip;

A thirtieth determining submodule, configured to determine, according to the gate-level netlist of the chip and the chip design layout and/or design layout diagram, after modifying one or a part of the number of modules and/or names of all of the modules and/or cells, in one or more times of LVS verifications using one or more types of LVS verification software and/or tools and/or environments, and a result and/or report of failed LVS verification, an IP core for information call and/or suspected call of the target chip and/or the target chip; the thirtieth determination sub-module includes, but is not limited to, one or more of the following: an eleventh determining unit, configured to determine that the failed gate-level netlist portion in the verification, and/or the failed chip design layout and/or design layout pattern area, and/or the module and/or cell and/or design information corresponding to the failed portion and/or the failed area are/is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; a twelfth determining unit, configured to determine the device and/or connection relationship in the gate-level netlist found in the verification, the gate-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or design layout, and/or the gate-level netlist portion corresponding to the difference, and/or the chip design layout and/or design placement and/or design layout area, and/or the module, and/or the cell, and/or the design information, and call and/or suspect-called IP cores for the information of the target chip and/or the target chip;

A thirty-first determining submodule, configured to determine, according to a gate-level netlist of a chip, an IP core for information call and/or suspected call of the target chip and/or the target chip after the converted gate-level netlist of the chip is converted into a chip-transistor-level netlist, in one or more LVS verifications performed using one or more LVS verification software and/or tools and/or environments and a result and/or report of a failed LVS verification; the thirty-first determination submodule includes, but is not limited to, one or more of: a thirteenth determining unit, configured to determine an IP core called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or cell and/or design information corresponding to the failed transistor-level netlist portion and/or the failed chip design layout and/or design layout area, and/or the failed portion and/or the failed area; a fourteenth determining unit, configured to determine the device and/or connection relationship in the transistor-level netlist found in the verification, the transistor-level netlist portion corresponding to the difference between the device and/or connection relationship in the chip design layout and/or design placement and/or layout, and/or the gate-level netlist portion corresponding to the difference, and/or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and/or the corresponding chip design layout and/or design placement and layout area, and/or module, and/or cell, and/or design information, and invoke and/or suspect-to-invoke IP cores for the information of the target chip and/or the target chip;

A thirty-third determining submodule, configured to, after modifying one or a part of the number of modules and/or unit names according to the gate-level netlist of the chip and the chip design layout and/or design layout, convert the modified gate-level netlist into a transistor-level netlist of the chip, determining the IP core called by the information and/or suspected calling of the target chip and/or the target chip by using the converted netlist of the chip transistor level and the modified chip design layout and/or design layout diagram and using one or more LVS verification software and/or tools and/or environments to perform one or more LVS verification of the failed LVS verification; the thirty-third determination sub-module includes, but is not limited to, one or more of: a seventeenth determining unit, configured to determine an IP core called and/or suspected to be called for information of the target chip and/or the target chip by a module and/or a cell and/or design information corresponding to a failed transistor-level netlist portion in the verification, and/or a gate-level netlist portion corresponding to the failed transistor-level netlist portion, and/or a failed chip design layout and/or design layout area, and/or a failed portion and/or a failed area; an eighteenth determining unit, configured to determine the device and/or connection relationships in the transistor-level netlist found in the verification, the transistor-level netlist portion corresponding to the difference with the device and/or connection relationships in the chip design layout and/or design placement and/or layout, and/or the gate-level netlist portion corresponding to the difference, and/or the gate-level netlist portion corresponding to the corresponding transistor-level netlist portion, and/or the corresponding chip design layout and/or design layout area, and/or module, and/or cell, and/or design information, and call and/or suspect-called IP cores for the information of the target chip and/or the target chip;

A thirty-fourth determining submodule, configured to determine, according to two gate-level netlists of a chip, an IP core that is called and/or suspected to be called by information of the target chip and/or the target chip in one or more formal verification processes using one or more formal verification software and/or tools and/or environments and/or a result and/or a report of a failed formal verification process; the thirty-fourth determination sub-module includes, but is not limited to, one or more of: a nineteenth determining unit, configured to determine a gate-level netlist portion that fails in verification, and/or a module and/or a unit and/or design information corresponding to the failed portion as an IP core that is called and/or suspected to be called by the target chip and/or the information of the target chip; a twentieth determining unit, configured to determine that the gate-level netlist portion corresponding to the mismatch point found in the verification, and/or the module and/or unit and/or design information corresponding to the portion and/or mismatch point is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a twenty-first determining unit, configured to determine an inequivalent part found in verification, and/or a gate level netlist part corresponding to the inequivalent part, and/or a module and/or a unit corresponding to the inequivalent part, and/or an IP core for which design information is called and/or suspected to be called by the target chip and/or the information of the target chip; a twenty-second determining unit, configured to determine that a difference between logic and/or functions in two gate-level netlists found in the verification and/or a gate-level netlist portion, and/or a module and/or a unit and/or design information corresponding to the difference are/is an IP core called and/or suspected to be called by the target chip and/or the target chip;

A thirty-fifth determining sub-module, configured to determine, according to two gate-level netlists of a chip, a result and/or a report of one or more formal verification operations in one or more formal verification operations using one or more formal verification software and/or tools and/or environments after modifying one or a part of the number of modules and/or units, and an IP core that is called and/or suspected to be called, the target chip and/or information of the target chip; the thirty-fifth determination sub-module includes, but is not limited to, one or more of the following: a twenty-third determining unit, configured to determine a failed gate-level netlist portion in verification, and/or a module and/or a unit and/or design information corresponding to the failed portion as an IP core called and/or suspected to be called by the target chip and/or information of the target chip; a twenty-fourth determining unit, configured to determine that the gate-level netlist portion corresponding to the mismatch point found in the verification, and/or the module and/or unit and/or design information corresponding to the portion and/or mismatch point is the IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a twenty-fifth determining unit, configured to determine an inequivalent part found in verification, and/or a gate-level netlist part corresponding to the inequivalent part, and/or a module and/or a unit and/or design information as an IP core called and/or suspected to be called by the target chip and/or information of the target chip; a twenty-sixth determining unit, configured to determine that a difference between logic and/or functions in the two gate-level netlists found in the verification and/or a gate-level netlist portion, and/or a module and/or a unit and/or design information corresponding to the difference are/is an IP core called and/or suspected to be called by the target chip and/or the target chip;

a thirty-seventh determining sub-module, configured to determine a location of a twentieth identifier in the chip RTL code and/or a portion where the twentieth identifier is located and/or a portion where the code length between the twentieth identifier and the twentieth identifier is less than or equal to a forty-first preset threshold and/or a portion where the ratio of the code length between the twentieth identifier and the twentieth identifier in the chip RTL code is less than or equal to a sixth ratio threshold, and/or a module and/or a unit and/or design information corresponding to the location and/or the portion and/or the twentieth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the twentieth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

A thirty-eighth determining submodule, configured to determine, according to a part of the chip RTL code where the other level descriptions except the register transmission level description are located, an IP core called by the information of the target chip and/or suspected to be called by the information of the target chip; the other level descriptions besides the register transfer level description include, but are not limited to, gate level descriptions; wherein the thirty-eighth determination submodule includes, but is not limited to, one or more of: a twenty-seventh determining unit, configured to determine that one or more keywords present in the chip RTL code, and/or keywords corresponding to a forty-second preset threshold in the total number of the one or more keywords present in the chip RTL code, and/or keywords corresponding to a forty-third preset threshold in the proportion that the total number of the one or more keywords present in the chip RTL code occupies the entire chip RTL code, and determine, as the target core, a portion where a position and/or a portion where the keyword is located, and/or a portion where a code length between the keyword and the keyword is less than or equal to the forty-fourth preset threshold, and/or a portion where a code length between the keyword and the keyword is less than or equal to a seventh proportional threshold in the chip RTL code, and/or a module and/or unit and/or design information corresponding to the position and/or the portion, and/or the keyword And the IP core called and/or suspected to be called by the information of the chip and/or the target chip, wherein the keywords are keywords representing other level descriptions besides the register transmission level description, and the categories of the keywords include but are not limited to one or more of the following: code at a characterization description level, words and/or phrases at a characterization description level, scripts at a characterization description level, programs at a characterization description level, netlists at a characterization description level, wherein the netlists include, but are not limited to, gate-level netlists; a twenty-eighth determining unit, configured to determine, as an IP core for information call and/or suspected call of the target chip and/or the target chip, a module and/or a unit and/or design information corresponding to a twenty-fourth part and/or a twenty-fourth part in the chip RTL code, where the module and/or the unit and/or the design information are the same as and/or similar to a twenty-third part of the gate-level netlist of the chip and/or have a similarity greater than or equal to a forty-fifth preset threshold;

A thirty-ninth determining sub-module, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to a twenty-sixth part and/or a twenty-sixth part of the chip RTL code, where the module and/or unit and/or design information is the same as and/or similar to and/or has a similarity greater than or equal to a forty-sixth preset threshold with respect to a twenty-fifth part of the RTL code in a twenty-third preset library; the twenty-third preset library does not contain the RTL code designed by the design company of the target chip;

a fortieth determining sub-module, configured to determine, as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip, a module and/or unit and/or design information corresponding to a twenty-eighth part and/or a twenty-eighth part of the chip RTL code, where the module and/or unit and/or design information is the same as and/or similar to and/or has a similarity greater than or equal to a forty-seventh preset threshold with respect to a twenty-seventh part of the RTL code in a twenty-fourth preset library; an RTL code designed for a design company of the target chip and/or an RTL code IP core library of the design company of the target chip and/or an IP core library of the design company of the target chip in the twenty-fourth preset library;

A forty-first determining submodule, configured to determine, according to a gate-level netlist of a chip RTL code and the chip, a result and/or a report of formal verification that one or more types of formal verification software and/or tools and/or environments are used for performing one or more times of formal verification, and fails, an IP core for information call and/or suspected call of the target chip and/or the target chip; the forty-first determination submodule includes, but is not limited to, one or more of: a twenty-ninth determining unit, configured to determine that an RTL code portion that fails in verification, and/or a gate-level netlist portion that fails, and/or a module and/or a unit and/or design information corresponding to the failed portion is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a thirtieth determining unit, configured to determine that an RTL code portion and/or a gate-level netlist portion corresponding to a mismatch point found in the verification, and/or a module and/or a unit and/or design information corresponding to the portion and/or the mismatch point are/is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a thirty-first determining unit, configured to determine an inequivalent part found in verification, and/or an RTL code part corresponding to the inequivalent part, and/or a gate-level netlist part, and/or a module and/or a unit, and/or an IP core for which design information is called and/or suspected to be called for the target chip and/or the information of the target chip; a thirty-second determining unit, configured to determine differences between logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist, and/or differences between the logic and/or functions in the RTL code and the gate-level netlist, and/or a gate-level netlist part, and/or a module and/or a unit and/or an IP core for which design information is called and/or suspected to be called for the target chip and/or the target chip;

A forty-second determining sub-module, configured to determine, according to the RTL code of the chip and the gate-level netlist of the chip, and after modifying one or a part of the number of modules and/or units, a result and/or a report of one or more formal verification operations performed in one or more formal verification operations using one or more formal verification software and/or tools and/or environments, and a result and/or a report of an unsuccessful formal verification operation, an IP core called and/or suspected to be called by information of the target chip and/or the target chip; the forty-second determination submodule includes, but is not limited to, one or more of: a thirty-third determining unit, configured to determine that the failed RTL code portion and/or the failed gate-level netlist portion and/or the module and/or unit and/or design information corresponding to the failed RTL code portion and/or the failed gate-level netlist portion are/is an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an RTL code part and/or a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or a unit and/or design information corresponding to the part and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; a thirty-fourth determining unit, configured to determine an inequivalent part found in verification, and/or an RTL code part corresponding to the inequivalent part, and/or a gate-level netlist part, and/or a module and/or a unit, and/or an IP core for which design information is called and/or suspected to be called for the target chip and/or the information of the target chip; a thirty-fifth determining unit, configured to determine differences between logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist, and/or RTL code portions corresponding to the differences, and/or gate-level netlist portions, and/or modules and/or units and/or IP cores for which design information is called and/or suspected to be called for the target chip and/or information of the target chip, which are found in the verification;

When the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the RTL code and the gate level netlist, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the non-verification of the corresponding function and/or logic of the difference includes but is not limited to: when the constants are set, the function and/or logic and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the function and/or logic and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logic and/or pins of the auxiliary design and/or auxiliary test include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

Optionally, the determining, according to the first information, whether to call an IP core and/or determine whether to call an IP core suspected of being called, a preset threshold and/or an identifier and/or a preset library used and/or a region and/or a part therein, and the determining, according to the second information, of the information of the target chip and/or the target chip, the IP core called and/or suspected of being called, the preset threshold and/or the identifier and/or the preset library used and/or the region and/or the part therein, are the same or different;

According to the first information, whether an IP core is called and/or is suspected to be called is determined in the target chip and/or the information of the target chip, and the used preset threshold and/or identification and/or preset library and/or the area and/or part thereof, wherein the preset thresholds and/or identifications and/or preset libraries and/or the area and/or part thereof of the same type are the same or different;

and according to the second information, determining that the information of the target chip and/or the target chip, the IP core called and/or suspected to be called, the used preset threshold and/or identification and/or the preset library and/or the area and/or part thereof are the same or different, wherein the preset threshold and/or identification and/or the preset library and/or the area and/or part thereof are the same or different.

wherein the non-self-research IP core comprises but is not limited to one or more of the following: the IP core is not designed by the design company of the target chip, the IP core purchased by the design company of the target chip from other companies, the IP core called by the design company of the target chip from a non-self-research IP core library, and the IP core of which the intellectual property right does not belong to the design company of the target chip;

Wherein, the self-developed IP core comprises but is not limited to one or more of the following: the IP core designed by the design company of the target chip, the IP core independently developed by the design company of the target chip, the IP core owned by the design company of the target chip, the IP core accumulated by the design company of the target chip and the IP core of which the intellectual property belongs to the design company of the target chip.

Optionally, the apparatus further comprises: the IP core classification module is used for determining whether the information of the target chip and/or the target chip, the calling and/or suspected calling IP core is a non-self-research IP core and/or a self-research IP core according to the first information and/or the second information and/or the information of the target chip and/or the design file of the target chip and/or the authorization data of the target chip; and/or

The IP core classification module is used for determining whether the IP core is a non-self-grinding IP core and/or a self-grinding IP core or not while determining the information of the target chip and/or the target chip, calling and/or suspected calling IP core according to second information;

the second classification unit is used for determining the IP core determined by the inconsistency and/or the content corresponding to the inconsistency when the chip design layout and/or the corresponding chip real object and/or the real object layout and/or the layout are compared as a non-self-research IP core;

A fifth classification unit, configured to determine that an IP core determined by contents corresponding to a thirtieth part in the third information of the target chip, which is the same as and/or similar to a twenty-ninth part of the information in the twenty-sixth preset library and/or has a similarity greater than or equal to a forty-ninth preset threshold, and/or the thirtieth part, is a non-self-research IP core; the twenty-sixth preset library does not contain information designed by a design company of the target chip;

An eighth classification unit, configured to determine that the determined IP core is a non-self-research IP core in one or more formal verifications performed according to one or more formal verification software and/or tools and/or environments, and/or report a result of a failed formal verification;

a ninth classification unit, configured to determine that an IP core determined according to a part of the chip RTL code where the level descriptions other than the register transfer level description are located is a non-self-research IP core;

a tenth type unit, configured to call and/or suspected to call an IP core for the information of the target chip and/or the target chip, and if it is determined that the IP core is not the information of the target chip and/or the target chip, the called and/or suspected called self-research IP core, determine that the IP core is a non-self-research IP core called and/or suspected called by the information of the target chip and/or the target chip;

an eleventh classifying unit, configured to determine that the IP core determined by the twenty-second identifier in the third information of the target chip is a self-research IP core; the twenty-second mark is a mark of a design company of the target chip and/or a mark representing the design company of the target chip;

a thirteenth classification unit, configured to determine that the IP core determined by the thirty-second part of the third information of the target chip, which is the same as and/or similar to the thirty-first part of the information in the twenty-eighth preset library and/or has a similarity greater than or equal to a fifty-first preset threshold, and/or the content corresponding to the thirty-second part is a self-research IP core; the twenty-eighth preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

wherein, the third information of the target chip includes but is not limited to one or more of the following: the method comprises the following steps of designing a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a transistor-level netlist of the chip, a gate-level netlist of the chip, an RTL code of the chip, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information;

A first score determining unit, configured to determine, for each type of the required fourth information, that a score obtained by the chip is: subtracting the score corresponding to the part of the information to be determined, which is absent in the obtained fourth information, and/or the absent function and/or the absent logic and/or the absent module and/or the absent unit, from the score corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information, and then, remaining the score; and/or determining the score obtained by the chip as: a score corresponding to the fourth information, a score obtained by subtracting a first proportion of scores corresponding to the information part and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit of the chip to be judged which is missing in the fourth information, and a score obtained by subtracting a second proportion of scores corresponding to the non-self-research IP core which is called and/or suspected to be called in the fourth information; wherein, if the part of the information to be determined of the chip and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit in the obtained fourth information have repeated and/or overlapped contents with the non-self-research IP core called and/or suspected to be called in the obtained fourth information, the score is reduced once and/or not repeated and reduced for the repeated and/or overlapped contents; wherein the first score determining unit includes: a first ratio determining subunit configured to determine a first ratio and/or a second ratio, where the first ratio and/or the second ratio are satisfied by one or more of the following conditions: a ratio of less than or equal to 1, a ratio of greater than or equal to 0, a ratio of the missing information portion of the chip to be determined and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit when in country is less than or equal to a ratio when in non-country, a ratio of the called and/or suspected called non-self-study IP cores when in country is less than or equal to a ratio of the non-self-study IP cores when in non-country;

a second requirement determining unit for determining various functions and/or logics and/or modules and/or units required for determining the autonomy and/or controllability of the chip;

a second score distribution unit, configured to distribute, for each of the various required functions and/or logics and/or modules and/or units, a score corresponding to the function and/or logic and/or module and/or unit; wherein the second value assigning unit includes but is not limited to: a second assignment subunit for assigning a score according to the ease and/or criticality of each function and/or logic and/or module and/or unit, implementation and/or design;

A fifth value determining unit, configured to determine, for each of the required functions and/or logics and/or modules and/or units, that the chip does not obtain a score corresponding to the function and/or logic and/or module and/or unit and/or that the chip obtains a score of a third ratio of scores corresponding to the function and/or logic and/or module and/or unit if a non-self-research IP core is called and/or suspected to be called in the function and/or logic and/or module and/or unit of the chip to be determined; wherein, the third proportion is required to satisfy conditions including but not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, and the ratio of the called and/or suspected called non-self-researched IP core when the called and/or suspected called non-self-researched IP core is in a state is greater than or equal to the ratio of the called and/or suspected called non-self-researched IP core when the called and/or suspected called non-self-researched IP core is in a state;

when the scores corresponding to the various functions and/or logics and/or modules and/or units are distributed for the various required functions and/or logics and/or modules and/or units, it is required to ensure that the scores corresponding to the chips with a given function are the same under different schemes and with the same degree of autonomy and/or controllability; the premise that the scores corresponding to the same degree of autonomy and/or controllability are all the same includes but is not limited to: the sum of the scores corresponding to the various functions and/or logics and/or modules and/or units required by a given function chip under different schemes is the same.

Optionally, the first score determining unit is further configured to calculate scores corresponding to the information part of the chip to be determined and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit that are missing in the obtained fourth information, and/or scores corresponding to the non-self-research IP cores called and/or suspected to be called in the obtained fourth information, where the first score determining unit further includes, but is not limited to, one or more of the following:

And the fourth confirming sub-module is used for comparing and/or verifying the acquired information and the information confirmed as the target chip through comparison and/or verification for one time or more times, and if the comparison and/or verification is passed, the acquired information is the information of the target chip.

Optionally, the first acknowledgement unit and/or the second acknowledgement unit and/or the fourth acknowledgement sub-module includes, but is not limited to, one or more of the following:

the first comparison subunit is used for comparing the chip design layout and/or the design layout with the chip real object and/or the real object layout;

a second comparison subunit, for comparing the chip design layout and/or layout diagram with the chip physical and/or physical layout diagram, and after removing the part and/or region and/or module and/or unit of the non-self-researched IP core which is confirmed as the target chip calling or suspected calling, the rest chip design layout and/or layout diagram with the rest chip physical and/or physical layout diagram;

The first verification subunit is used for performing LVS verification on the schematic diagram of the chip and the chip design layout and/or the design layout and wiring diagram;

a second verification subunit, configured to perform LVS verification on the schematic diagram of the remaining chip, and the design layout and/or design layout diagram of the remaining chip after removing the part and/or region and/or module and/or cell and/or design information of the non-self-researched IP core that has been confirmed as a target chip call or suspected call;

the third verification subunit is used for performing LVS verification on the netlist of the chip transistor level and the chip design layout and/or the design layout and wiring diagram;

a fourth verification subunit, configured to perform LVS verification on the remaining netlist of the chip transistor level, and the remaining design layout and/or design layout pattern of the chip transistor level after removing the part and/or region and/or module and/or cell and/or design information of the non-self-researched IP core that has been confirmed as a target chip call or suspected call;

A ninth verification sub-unit, configured to remove the gate-level netlist, the chip design layout and/or design layout, and the portion and/or region and/or module and/or cell and/or design information of the non-self-researched IP core that is identified as the target chip calling or suspected calling, convert the remaining gate-level netlist into a transistor-level netlist, and perform LVS verification on the converted transistor-level netlist and the remaining chip design layout and/or design layout;

the tenth verification subunit is configured to perform formal verification on one gate-level netlist of the chip and another gate-level netlist of the chip;

A thirteenth verification subunit, configured to perform formal verification on the RTL code of the remaining chip and the gate-level netlist of the remaining chip after removing the part and/or region and/or module and/or unit and/or design information of the non-self-developed IP core that has been determined as the target chip call or suspected call;

The layout and/or routings in the preset library, including but not limited to all layers and/or partial layers and/or one layer of the layout and/or routings, for one of the layers, the layout and/or routings in the whole area and/or in a plurality of partial areas and/or one partial layout area; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different; and/or the presence of a gas in the atmosphere,

a schematic diagram of the chip, and/or a region in a schematic diagram of the chip, including but not limited to a chip schematic diagram of an entire region and/or a plurality of partial regions and/or a partial region; and/or the presence of a gas in the gas,

schematic diagrams in the preset library and/or regions in the schematic diagrams, including but not limited to schematic diagrams of the whole region and/or a plurality of local regions and/or one local region; and/or the presence of a gas in the gas,

the chip transistor-level netlist, and/or portions of a transistor-level netlist, include, but are not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level; and/or the presence of a gas in the gas,

The transistor-level netlist, and/or the portion of the transistor-level netlist in the preset library include, but are not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level; and/or the presence of a gas in the atmosphere,

the gate level netlist, and/or portions of the gate level netlist of the chip, include, but are not limited to: the whole gate-level netlist and a part of gate-level netlist; and/or the presence of a gas in the atmosphere,

The chip real object and/or real object layout and/or layout comprises but is not limited to one or more of the following: the annotation and/or the description in the chip real object and/or the real object layout wiring diagram; and/or the presence of a gas in the atmosphere,

the schematic diagram of the chip includes, but is not limited to, one or more of the following: schematic diagram of the chip, comments and/or description in the schematic diagram of the chip; and/or the presence of a gas in the atmosphere,

the netlist at the chip transistor level includes, but is not limited to, one or more of the following: a netlist at the chip transistor level, comments and/or descriptions in the netlist at the chip transistor level; and/or the presence of a gas in the atmosphere,

Referring to fig. 3, fig. 3 is a schematic structural diagram of an electronic device according to a third embodiment of the present invention, where the electronic device 30 includes a processor 31, a memory 32, and a program stored in the memory 32 and capable of running on the processor 31; the processor 31 executes the steps in any of the above detection methods invoked by the IP core, and please refer to the above in detail, which is not described herein again.

A fourth embodiment of the present invention provides a readable storage medium, on which a program is stored, where the program, when executed by a processor, implements the steps in any one of the detection methods for IP core invocation in the foregoing embodiments. Please refer to the above description of the method steps in the corresponding embodiments.

The readable storage medium includes a computer readable storage medium. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A detection method for IP core call is characterized by comprising the following steps:

2. The method of claim 1, wherein the target chip is a whole or partial chip, and the types of the chips include but are not limited to one or more of the following: packaged chips, unpackaged dies, modules in dies, units in dies have been completed.

3. The method of claim 1, wherein the first information is the same as or different from the second information.

4. The method according to claim 1, wherein the determining whether the IP core is called and/or suspected to be called in the target chip and/or the information of the target chip and the determining whether the IP core is called and/or suspected to be called in the information of the target chip and/or the target chip are performed in two steps or performed in one step; the IP core that determines the information call and/or suspected call of the target chip and/or the target chip is also a method for determining whether the IP core is called and/or suspected to be called in the target chip and/or the information of the target chip.

5. The method according to claim 1, wherein the first information comprises a chip design layout and/or design placement and/or layout diagram, and/or a chip physical and/or physical layout and/or physical placement and/or layout diagram;

determining whether to call the IP core and/or suspected to call the IP core in the target chip and/or the information of the target chip according to the first information, wherein the determining includes but is not limited to one or more of the following:

in a chip design layout and/or a design layout, if an empty area and/or an empty area is larger than or equal to a first preset threshold and/or an empty area occupation ratio is larger than or equal to a second preset threshold and/or the empty area is a regular geometric figure, determining that an IP core is called and/or suspected to be called in the target chip and/or the information of the target chip; the blank area occupation ratio refers to a ratio of the blank areas occupying the design layout and/or the design layout, and the regular geometric figures include, but are not limited to, one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc;

Comparing the chip design layout and/or design layout with corresponding chip real objects and/or real object layout and/or layout, if the comparison is inconsistent, determining that the IP core is called and/or the IP core is suspected to be called in the target chip and/or the information of the target chip, wherein the inconsistent comparison condition includes but is not limited to one or more of the following conditions: all layers and/or a part of layers and/or a layer are not in consistent alignment; the whole area and/or a plurality of local areas and/or one local area in all layers and/or part of layers and/or one layer are not consistent in comparison;

if a first identifier exists in the chip design layout and/or design layout, and/or the chip real object and/or real object layout and/or wiring, it is determined that an IP core is called and/or an IP core is suspected to be called in the target chip and/or the information of the target chip; the first identification is an identification of other companies except the design company of the target chip and/or an identification representing other companies except the design company of the target chip;

If a second identifier exists in the chip design layout and/or chip real object and/or real object layout and/or layout, determining that an IP core is called and/or an IP core is suspected to be called in the target chip and/or the information of the target chip; the second identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

comparing the chip design layout and/or design layout with the layout and/or layout in a first preset library, and if a first region in the chip design layout and/or design layout is the same as and/or similar to a second region in the layout and/or layout in the first preset library and/or the similarity is greater than or equal to a third preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; the first preset library does not contain the layout and/or the wiring and/or the layout and wiring diagram designed by the design company of the target chip;

Comparing the chip design layout and/or design layout pattern with a layout and/or layout pattern in a second preset library, and if a third area in the chip design layout and/or design layout pattern is the same as and/or similar to a fourth area in the layout and/or layout pattern in the second preset library and/or the similarity is greater than or equal to a fourth preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core; the second preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring and/or layout and/or wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

the chip real object and/or real object layout wiring diagram, comparing with the layout and/or layout of the chip in the third preset library, if the chip in the fifth area in the real object and/or real object layout and/or layout, the same and/or similar and/or similarity degree with the sixth area of the layout and/or routings layout in the third preset library is larger than or equal to a fifth preset threshold, determining that the IP core is called by the information of the target chip and/or suspected to be called by the information of the target chip; the third preset library does not contain a layout and/or a wiring layout of the design company of the target chip;

The chip real object and/or real object layout and/or wiring diagram, comparing with the layout and/or layout of the chip in the fourth preset library, if the chip in the seventh area in the real object and/or real object layout and/or layout, the same and/or similar and/or similarity degree with the eighth area of the layout and/or place-and-route pattern in the fourth preset library is larger than or equal to a sixth preset threshold, determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core; and the fourth preset library is a layout and/or a wiring layout diagram designed for the design company of the target chip, and/or a layout and/or a wiring layout diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip.

6. The method according to claim 1, wherein the first information comprises a schematic of the chip, and/or a chip design layout and/or a design place and route pattern;

if the third identifier exists in the schematic diagram of the chip, determining that an IP core is called in the target chip and/or in the information of the target chip and/or suspected to call the IP core; the third mark is the mark of other companies except the design company of the target chip and/or marks representing other companies except the design company of the target chip;

if the schematic diagram of the chip has a fourth identifier, determining that an IP core is called in the target chip and/or in the information of the target chip and/or suspected to call the IP core; the fourth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

comparing the schematic diagram of the chip with a schematic diagram in a fifth preset library, and if a ninth area in the schematic diagram of the chip is the same as or similar to a tenth area in the schematic diagram of the fifth preset library and/or the similarity is greater than or equal to a seventh preset threshold, determining that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the fifth preset library does not contain a schematic diagram designed by a design company of the target chip;

Comparing the schematic diagram of the chip with a schematic diagram in a sixth preset library, and if an eleventh area in the schematic diagram of the chip is the same as and/or similar to a twelfth area in the schematic diagram of the sixth preset library and/or the similarity is greater than or equal to an eighth preset threshold, determining that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the sixth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

aiming at the schematic diagram of the chip and the chip design layout and/or design layout and wiring diagram, one or more LVS verification software and/or tools and/or environments are used for performing LVS verification for one time or more times, and if the LVS verification for one time or more times does not pass, the information of the target chip and/or the target chip is determined to call an IP core and/or suspected to call the IP core;

and aiming at the schematic diagram of the chip and the chip design layout and/or layout and wiring diagram, modifying one or part of the number of modules and/or unit names or all the module and/or unit names, performing LVS verification for one time or multiple times by using one or more LVS verification software and/or tools and/or environments after modification, and if the LVS verification for one time or multiple times does not pass, determining that the IP core is called by the target chip and/or the information of the target chip and/or the IP core is suspected to be called.

7. The method of claim 1, wherein the first information comprises a netlist at a chip transistor level, and/or a chip design layout and/or a design place and route graph; the transistor-level netlist includes, but is not limited to, one or more of the following: the analog-digital mixed chip is composed of a transistor-level netlist corresponding to an analog module schematic diagram and/or a transistor-level netlist corresponding to a digital module-finished gate-level netlist of the final design;

determining whether to call an IP core and/or suspected to call the IP core in the target chip and/or the information of the target chip according to the first information, wherein the determining includes but is not limited to one or more of the following:

if a fifth identification exists in the netlist of the chip transistor level, determining that the IP core is called by the target chip and/or the information of the target chip and/or the suspected IP core is called; the fifth identification is an identification of a company other than the design company of the target chip and/or an identification representing the company other than the design company of the target chip;

If the sixth identifier exists in the netlist of the chip transistor level, determining that the IP core is called by the target chip and/or the information of the target chip and/or the suspected IP core is called; the sixth identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

comparing the netlist of the chip transistor level with the netlist of the transistor level in a seventh preset library, and if a first part of the netlist of the chip transistor level is the same as a second part of the netlist of the transistor level in the seventh preset library and/or similar to the first part of the netlist of the transistor level in the seventh preset library and/or the similarity is greater than or equal to a ninth preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core; the seventh preset library does not contain a netlist of a transistor level designed by a design company of the target chip;

comparing the netlist of the chip transistor level with the netlist of the transistor level in an eighth preset library, and if a third part in the netlist of the chip transistor level is the same as a fourth part in the netlist of the transistor level in the eighth preset library and/or is similar to the third part and/or has similarity larger than or equal to a tenth preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core; the eighth preset library is a netlist of a transistor level designed by a design company of the target chip, and/or a netlist IP core library of a transistor level of a design company of the target chip, and/or an IP core library of a design company of the target chip;

Aiming at the netlist of the chip transistor level and the chip design layout and/or layout, one or more LVS verification software and/or tools and/or environments are used for performing one or more LVS verification, and if the one or more LVS verification fails, the target chip and/or the target chip is determined to call an IP core and/or suspected to call an IP core;

and modifying one or part of the number of the modules and/or all the unit names according to the netlist of the chip transistor level and the chip design layout and/or layout, performing LVS verification for one time or multiple times in one or more LVS verification software and/or tools and/or environments after modification, and determining that the IP core is called and/or suspected to be called by the information of the target chip and/or the target chip if the LVS verification for one time or multiple times does not pass.

8. The method of claim 1, wherein the first information comprises a gate level netlist of the chip, and/or a chip design layout and/or a design place and route graph; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip register transmission level RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process are finished; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

if a seventh identifier exists in the gate-level netlist of the chip, determining that the target chip and/or the information of the target chip call an IP core and/or suspected to call the IP core; the seventh mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

if the eighth identifier exists in the gate-level netlist of the chip, determining that the target chip and/or the information of the target chip call an IP core and/or suspected to call the IP core; the eighth mark is a mark of a design company of the target chip and/or a mark representing the design company of the target chip;

comparing the gate-level netlist of the chip with a gate-level netlist in a ninth preset library, and if a fifth part of the gate-level netlist of the chip is the same as and/or similar to a sixth part of the gate-level netlist in the ninth preset library and/or the similarity is greater than or equal to an eleventh preset threshold, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core; the ninth preset library does not contain a gate-level netlist designed by a design company of the target chip;

Comparing the gate-level netlist of the chip with a gate-level netlist in a tenth preset library, and if a seventh part of the gate-level netlist of the chip is the same as and/or similar to an eighth part of the gate-level netlist in the tenth preset library and/or the similarity is greater than or equal to a twelfth preset threshold, determining that the IP core is called by the target chip and/or the information of the target chip and/or the suspected IP core is called; a gate-level netlist designed for a design company of the target chip, and/or a gate-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the tenth preset library;

aiming at the gate-level netlist of the chip and the chip design layout and/or layout, one or more LVS verification software and/or tools and/or environments are used for performing one or more LVS verification, and if the one or more LVS verification fails, the target chip and/or the target chip is determined to call an IP core and/or suspected to call the IP core;

modifying one or part of the number of the modules and/or all the unit names according to the gate-level netlist of the chip and the chip design layout and/or layout, and performing LVS verification for one or more times in one or more LVS verification software and/or tools and/or environments after modification, and if the LVS verification for one or more times fails, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core;

After converting the gate-level netlist of the chip into a chip transistor-level netlist, aiming at the converted chip transistor-level netlist and the chip design layout and/or design layout wiring diagram, performing LVS verification for one time or multiple times by using one or more LVS verification software and/or tools and/or environments, and if the LVS verification for one time or multiple times does not pass, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core;

after converting a gate-level netlist of a chip into a chip transistor-level netlist, modifying one or part of the number of the converted chip transistor-level netlist and the chip design layout and/or design layout wiring diagram, and performing LVS verification for one or more times in one or more LVS verification software and/or tools and/or environments after modification, wherein if the LVS verification for one or more times fails, it is determined that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call an IP core;

Modifying one or part of the gate-level netlist and the chip design layout and/or design layout wiring diagram of the chip or the names of all the modules and/or units, converting the modified gate-level netlist into a chip transistor-level netlist, performing one or more LVS verifications in one or more LVS verification software and/or tools and/or environments aiming at the converted chip transistor-level netlist and the modified chip design layout and/or design layout wiring diagram, and if the one or more LVS verifications do not pass, determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core;

performing formal verification for one or more times by using one or more formal verification software and/or tools and/or environments aiming at two gate-level netlists of the chip, and if the formal verification for one or more times does not pass, determining that the IP core is called and/or the IP core is suspected to be called by the information of the target chip and/or the target chip;

modifying one or partial number of the names of all modules and/or units of the two gate-level netlists of the chip, performing one or more formal verification by using one or more formal verification software and/or tools and/or environments after modification, and determining that the IP core is called and/or suspected to be called by the information of the target chip and/or the target chip if the one or more formal verification is not passed;

When the formal verification is carried out, if the two gate-level netlists have differences in functions and/or logics of auxiliary design and/or auxiliary test, the functions and/or logics corresponding to the differences are not verified or verified; the method for verifying the function and/or logic corresponding to the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

9. The method of claim 1, wherein the first information comprises a chip RTL code, and/or a gate level netlist of a chip; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

if the chip RTL code has a ninth identifier, determining that the target chip and/or the information of the target chip call an IP core and/or suspected to call the IP core; the ninth mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

if the chip RTL code contains a tenth identifier, determining that the target chip and/or the information of the target chip call an IP core and/or suspected to call the IP core; the tenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

if other level descriptions except register transmission level descriptions exist in the chip RTL code, determining that the IP core is called by the target chip and/or the information of the target chip and/or suspected to be called by the target chip; the other level descriptions besides the register transfer level description include, but are not limited to, gate level descriptions; the method for checking whether other level descriptions besides the register transfer level description exist in the chip RTL code includes but is not limited to one or more of the following: carrying out keyword retrieval on the chip RTL code; comparing a chip RTL code with a gate-level netlist of a chip, and if a ninth part of the chip RTL code is the same as and/or similar to a tenth part of the gate-level netlist of the chip and/or the similarity is greater than or equal to a thirteenth preset threshold, determining that other level descriptions except register transmission level descriptions exist in the chip RTL code; the method for searching the keywords of the chip RTL code comprises but is not limited to one or more of the following steps: searching the RTL code by using one or more keywords representing other level descriptions except the register transmission level description, and if the RTL code is found to have one or more keywords and/or the total quantity of the one or more keywords in the RTL code is greater than or equal to a fourteenth preset threshold and/or the proportion of the total quantity of the one or more keywords in the RTL code occupying the whole RTL code word is greater than or equal to a fifteenth preset threshold, determining that other level descriptions except the register transmission level description exist in the chip RTL code; searching the RTL code by using one or more keywords representing register transmission level descriptions, and if various keywords are found not to exist in the RTL code and/or one or more keywords do not exist in the RTL code, determining that other level descriptions except the register transmission level descriptions exist in the chip RTL code; the categories of the keywords include, but are not limited to, one or more of the following: code at a representation description level, words and/or phrases at a representation description level, scripts at a representation description level, programs at a representation description level, RTL code at a representation description level, a netlist at a representation description level, wherein the netlist includes but is not limited to a gate-level netlist;

Comparing the chip RTL code with an RTL code in an eleventh preset library, and if the eleventh part in the chip RTL code is the same as and/or similar to the twelfth part in the RTL code in the eleventh preset library and/or the similarity is greater than or equal to a sixteenth preset threshold, determining that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the eleventh preset library does not contain RTL codes designed by a design company of the target chip;

comparing the chip RTL code with an RTL code in a twelfth preset library, and if a thirteenth part of the chip RTL code is the same as and/or similar to a fourteenth part of the RTL code in the twelfth preset library and/or the similarity is greater than or equal to a seventeenth preset threshold, determining that the IP core is called by the information of the target chip and/or the IP core is suspected to be called; the twelfth preset library is an RTL code designed for the design company of the target chip, and/or an RTL code IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

performing formal verification for one or more times by using one or more formal verification software and/or tools and/or environments aiming at the RTL code of the chip and the gate-level netlist of the chip, and if the formal verification for one or more times fails, determining that the information of the target chip and/or the target chip calls an IP core and/or is suspected to call the IP core;

Modifying one or part of the number of the modules and/or unit names or all the module and/or unit names according to the RTL code of the chip and the gate-level netlist of the chip, performing formal verification for one or more times by using one or more formal verification software and/or tools and/or environments after modification, and determining that the target chip and/or the information of the target chip calls an IP core and/or is suspected to call the IP core if any formal verification for one or more times fails;

when the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the RTL code and the gate level netlist, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the method for not verifying the function and/or logic corresponding to the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

10. The method according to claim 1, wherein the second information comprises a chip design layout and/or design placement and/or layout diagram, and/or a chip physical and/or physical layout and/or physical placement and/or layout diagram;

and determining the information of the target chip and/or the target chip according to the second information, and calling and/or suspected calling IP cores, including but not limited to one or more of the following:

determining a blank area in a chip design layout and/or design layout pattern, and/or a blank area with an area larger than or equal to an eighteenth preset threshold, and/or a blank area with an occupation ratio larger than or equal to a nineteenth preset threshold, and/or a blank area of a regular geometric figure, and determining a module and/or a unit and/or design information corresponding to the blank area, and/or the design layout and/or design layout pattern corresponding to the blank area, and/or the module and/or the unit and/or the design information corresponding to the blank area as an IP core for information calling and/or suspected calling of the target chip and/or the target chip; the occupation ratio refers to the proportion of the blank areas occupying the design layout and/or design layout, and the regular geometric figures include but are not limited to one or more of the following: square, rectangle, rhombus, trapezoid, parallelogram, circle, ellipse, triangle, polygon, bow and arc; the blank area includes, but is not limited to, one or more areas;

Determining the inconsistency between the chip design layout and/or layout and/or physical layout and/or layout of the chip compared with the corresponding chip physical object and/or physical layout and/or physical object, determining the inconsistent positions and/or design layouts and/or design layout wiring diagrams corresponding to the inconsistent positions, and/or chip real objects and/or real object layouts and/or real object layout wiring diagrams corresponding to the inconsistent positions, and/or modules and/or units and/or design information corresponding to the inconsistent positions as IP cores called by the target chip and/or the target chip information and/or suspected to be called; wherein the inconsistency includes, but is not limited to, one or more of the following: all layers and/or part of layers and/or one layer are inconsistent in comparison; all layers and/or part of layers and/or one layer, wherein the whole area and/or a plurality of local areas and/or one local area are in inconsistent alignment; the inconsistency places include but are not limited to one or more places of layout and/or place-and-route patterns;

Determining a chip design layout and/or a design layout, and/or a chip real object and/or a real object layout, wherein the position of an eleventh identifier and/or the area of a eleventh identifier at a distance less than or equal to a twentieth preset threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the area and/or the eleventh identifier is an IP core called by the target chip and/or suspected to be called by the information;

after determining the position and/or area of an eleventh identifier and/or the area of a distance from the eleventh identifier to a twenty-first preset threshold and/or the module and/or unit and/or design information corresponding to the position and/or area of one or more layers and/or the position and/or area of one or more layers is determined as the information of the target chip and/or the target chip, the module and/or unit and/or design information corresponding to the target chip is called and/or the target chip /or an IP core suspected to be invoked; wherein the twenty-first preset threshold is the same as or different from the twentieth preset threshold;

Wherein the eleventh mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

determining a chip design layout and/or a design layout, and/or a chip real object and/or a real object layout, wherein the position of a twelfth identifier and/or the area of the twelfth identifier and/or the area of which the distance from the twelfth identifier is less than or equal to a twenty-second preset threshold, and/or a module and/or a unit and/or design information corresponding to the position and/or the area and/or the twelfth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip;

after determining the position and/or area of a twelfth mark and/or the area of the twelfth mark and/or the area with a distance from the twelfth mark smaller than or equal to a twenty-third preset threshold in a chip design layout and/or physical layout diagram, and/or determining the position and/or area of one or more layers and/or the module and/or unit and/or design information corresponding to the position and/or area of the one or more layers as the information of the target chip and/or the target chip to call and/or design information /or an IP core suspected to be invoked; wherein the twenty-third preset threshold is the same as or different from the twenty-second preset threshold;

determining modules and/or units and/or design information corresponding to a fourteenth area and/or a fourteenth area in the chip design layout and/or design layout, and/or the chip design layout and/or design layout, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-fourth preset threshold with respect to a thirteenth area in a thirteenth preset library, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the thirteenth preset library does not contain the layout and/or layout wiring diagram designed by the design company of the target chip;

determining a module and/or unit and/or design information corresponding to a sixteenth area and/or a sixteenth area in the chip design layout and/or design layout, which is the same as and/or similar to and/or has a similarity greater than or equal to a twenty-fifth preset threshold with respect to a fifteenth area in a fourteenth preset library, as an IP core for information calling and/or suspected calling of the target chip and/or the target chip; the fourteenth preset library is a layout and/or routing and/or layout and/or wiring diagram designed for the design company of the target chip, and/or a layout and/or wiring and/or layout and wiring diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

Determining modules and/or units and/or design information corresponding to eighteenth areas and/or eighteenth areas in the chip real objects and/or real object layout and/or layout, which are the same as and/or similar to and/or have a similarity greater than or equal to a twenty-sixth preset threshold in a fifteenth preset library, as IP cores for information calling and/or suspected calling of the target chip and/or the target chip; the fifteenth preset library does not contain a layout and/or a wiring layout designed by a design company of the target chip;

determining modules and/or units and/or design information corresponding to a twentieth area and/or a twentieth area in the chip real object and/or real object layout, which are the same as and/or similar to and/or have a similarity greater than or equal to a twenty-seventh preset threshold, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the sixteenth preset library is a layout and/or routing and/or layout-wiring pattern designed for the design company of the target chip, and/or a layout and/or layout-wiring pattern IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

Calling and/or suspected to be called chip real objects and/or real object layouts and/or real object layout and/or layout of the IP core determined as the target chip and/or the information of the target chip, and/or modules and/or units and/or design information corresponding to the positions and/or the areas, and determining the position and/or area of the corresponding chip design layout and/or design layout, and/or the module and/or unit and/or design information corresponding to the position and/or area as the IP core called and/or suspected to be called by the information of the target chip and/or the target chip.

11. The method of claim 1, wherein the second information comprises a schematic of the chip, and/or a chip design layout and/or a design place and/or a design layout;

and determining the information of the target chip and/or the target chip and calling and/or suspected calling IP cores according to the second information, wherein the calling and/or suspected calling IP cores comprise but are not limited to one or more of the following:

determining a position of a thirteenth identifier in a schematic diagram of the chip and/or a region of the thirteenth identifier and/or a region whose distance from the thirteenth identifier is less than or equal to a twenty-eighth preset threshold, and/or determining a module and/or a unit and/or design information corresponding to the position and/or the region and/or the thirteenth identifier as an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the thirteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

Determining a position where a fourteenth identification is located and/or an area where the fourteenth identification is located and/or an area where a distance from the fourteenth identification to the fourteenth identification is less than or equal to a twenty-ninth preset threshold in a schematic diagram of the chip, and/or determining that a module and/or a unit and/or design information corresponding to the position and/or the area and/or the fourteenth identification is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the fourteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

determining modules and/or units and/or design information corresponding to a twenty-second area and/or a twenty-second area in the schematic diagram of the chip, which are the same as and/or similar to the twenty-first area of the schematic diagram in a seventeenth preset library and/or have the similarity larger than or equal to a thirty-first preset threshold, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the seventeenth preset library does not contain a schematic diagram designed by a design company of the target chip;

determining modules and/or units and/or design information corresponding to a twenty-fourth area and/or a twenty-fourth area in the schematic diagram of the chip, which are the same as and/or similar to a twenty-third area of the schematic diagram in an eighteenth preset library and/or have a similarity larger than or equal to a thirty-first preset threshold, as the IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; the eighteenth preset library is a schematic diagram designed for the design company of the target chip, and/or a schematic diagram IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

Determining an IP core called by the information and/or suspected to be called of the target chip and/or the target chip according to a schematic diagram of the chip and a chip design layout and/or a design layout diagram, and results and/or reports of LVS verification which is not passed in one or more times of LVS verification by using one or more LVS verification software and/or tools and/or environments; the method of determination includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to failed schematic diagram areas, failed chip design layouts and/or design layout areas, and/or failed areas in verification as IP cores called and/or suspected to be called by the target chips and/or the information of the target chips; determining the difference of the device and/or connection relation in the schematic diagram found in the verification and the device and/or connection relation in the chip design layout and/or design layout and wiring diagram, and/or a schematic diagram area corresponding to the difference, and/or a chip design layout and/or design layout and wiring diagram area, and/or a module, and/or a unit, and/or design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

Determining an IP core called and/or suspected to be called by information of the target chip and/or the target chip according to a schematic diagram of the chip and a chip design layout and/or design layout diagram, after modifying one or a part of the number of modules and/or unit names, performing one or more LVS verification by using one or more LVS verification software and/or tools and/or environments, and determining the result and/or report of failed LVS verification; the method of determination includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to failed schematic diagram areas, failed chip design layouts and/or design layout areas, and/or failed areas in verification as IP cores called and/or suspected to be called by the target chips and/or the information of the target chips; determining the difference of the devices and/or the connection relations in the schematic diagram found in the verification and the device and/or the connection relations in the chip design layout and/or the design layout area, and/or the module, and/or the unit, and/or the design information corresponding to the difference, and/or the schematic diagram area, and/or the chip design layout and/or the design layout area, and/or the module, and/or the unit, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip.

12. The method according to claim 1, wherein the second information comprises a netlist at a chip transistor level, and/or a chip design layout and/or a design place and route pattern; the transistor-level netlist includes, but is not limited to, one or more of the following: the description is a netlist at a transistor level, a netlist at a transistor level corresponding to a chip schematic diagram, a netlist at a transistor level corresponding to a gate-level netlist of a final design completed by a chip, a netlist at a transistor level corresponding to a chip design layout and/or design layout diagram, and a netlist at a transistor level consisting of a netlist at a transistor level corresponding to a gate-level netlist of a final design completed by an analog module schematic diagram and/or a digital module in an analog-digital hybrid chip;

determining a position of a fifteenth identifier in a netlist of a chip transistor level and/or a part of the fifteenth identifier and/or a part of a code length between the fifteenth identifier and the fifteenth identifier which is less than or equal to a thirty-second preset threshold and/or a part of a code length between the fifteenth identifier and the netlist of the chip transistor level which is less than or equal to a first proportional threshold, and/or determining that a module and/or a unit and/or design information corresponding to the position and/or the part and/or the fifteenth identifier calls and/or is suspected to call an IP core of the target chip and/or the information of the target chip; the fifteenth identification is an identification of a company other than the design company of the target chip and/or an identification representing a company other than the design company of the target chip;

Determining a position where a sixteenth identifier is located in the netlist of the chip transistor level and/or a part where the sixteenth identifier is located and/or a part where the code length between the sixteenth identifier and the sixteenth identifier is smaller than or equal to a thirty-third preset threshold and/or a part where the ratio of the code length between the sixteenth identifier and the netlist of the chip transistor level is smaller than or equal to a second ratio threshold, and/or determining that a module and/or a unit and/or design information corresponding to the position and/or the part and/or the sixteenth identifier is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the sixteenth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

determining modules and/or units and/or design information corresponding to a sixteenth part and/or a sixteenth part in the netlist of the chip transistor level, which are the same as and/or similar to a fifteenth part of the netlist of the transistor level in the nineteenth preset library and/or have a similarity greater than or equal to a thirty-fourth preset threshold, as the target chip and/or the IP core called by the information of the target chip; the nineteenth preset library does not contain a transistor-level netlist designed by a design company of the target chip;

Determining modules and/or units and/or design information corresponding to an eighteenth part and/or an eighteenth part in the netlist of the chip transistor level, which are the same as and/or similar to and/or have a similarity greater than or equal to a thirty-fifth preset threshold with respect to a seventeenth part of the netlist of the transistor level in a twentieth preset library, as IP cores called and/or suspected to be called by the information of the target chip and/or the target chip; a transistor-level netlist designed for a design company of the target chip and/or a transistor-level netlist IP core library of the design company of the target chip and/or an IP core library of the design company of the target chip in the twentieth preset library;

determining an IP core called by the information and/or suspected to be called of the target chip and/or the target chip according to the netlist of the chip transistor level and the chip design layout and/or the layout and/or layout and layout of the layout and/or layout and layout of the chip, and the result and/or report of the failed LVS verification in one or more times of LVS verification by using one or more types of LVS verification software and/or tools and/or environments; the method of determination includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to the failed transistor-level netlist part, and/or the failed chip design layout and/or design layout pattern region, and/or the failed part and/or the failed region in verification as the IP core called and/or suspected to be called by the information of the target chip and/or the target chip; determining the device and/or connection relation in the transistor-level netlist found in the verification, and the transistor-level netlist part corresponding to the difference and/or the difference between the device and/or connection relation in the chip design layout and/or design layout area, and/or module, and/or unit, and/or design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

According to the netlist and the chip design layout and/or design layout pattern of a chip transistor level, after one or part of the number or all of the module and/or unit names are modified, one or more types of LVS verification software and/or tools and/or environments are used for performing LVS verification for one or more times, and the result and/or report of failed LVS verification, determining the IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the method of determination includes, but is not limited to, one or more of the following: determining IP cores called and/or suspected to be called for the information of the target chip and/or the target chip by the modules and/or units and/or the design information corresponding to the failed transistor-level netlist part, and/or the failed chip design layout and/or layout area, and/or the failed part and/or the failed area in the verification; determining the device and/or connection relation in the transistor-level netlist found in the verification, the difference between the device and/or connection relation in the chip design layout and/or design placement and routing, and/or the device and/or connection relation in the design placement and routing, and/or the transistor-level netlist part corresponding to the difference, and/or the chip design layout and/or design placement and routing area, and/or the module, and/or the cell, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip.

13. The method of claim 1, wherein the second information comprises a gate level netlist of the chip, and/or a chip design layout and/or a design place and route graph; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: a gate-level netlist, a gate-level netlist corresponding to the chip design layout and/or design layout pattern, a gate-level netlist formed by integrating RTL codes of the chip, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process are finally designed; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

determining a position where a seventeenth identifier is located in the gate-level netlist of the chip and/or a part where the seventeenth identifier is located and/or a part where the code length between the seventeenth identifier and the seventeenth identifier is less than or equal to a thirty-sixth preset threshold and/or a part where the occupation ratio of the code length between the seventeenth identifier and the seventeenth identifier in the gate-level netlist of the chip is less than or equal to a third proportion threshold, and/or determining that a module and/or a unit and/or design information corresponding to the position and/or the part and/or the seventeenth identifier is an IP core called and/or suspected to be called for the information of the target chip and/or the target chip; the seventeenth identification is an identification of a company other than the design company of the target chip and/or an identification representing the company other than the design company of the target chip;

Determining a position of an eighteenth mark in a gate-level netlist of a chip and/or a part of the eighteenth mark and/or a part of a code length between the eighteenth mark and the eighteenth mark which is less than or equal to a thirty-seventh preset threshold and/or a part of a code length between the eighteenth mark and the gate-level netlist of the chip which is less than or equal to a fourth proportion threshold, and/or determining that a module and/or a unit and/or design information corresponding to the position and/or the part and/or the eighteenth mark is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the eighteenth mark is a mark of a design company of the target chip and/or a mark representing the design company of the target chip;

determining modules and/or units and/or design information corresponding to the twentieth part and/or the twentieth part in the gate-level netlist of the chip, which are the same as and/or similar to the nineteenth part and/or have the similarity greater than or equal to a thirty-eighth preset threshold, as the IP cores called by the information and/or suspected to be called by the target chip and/or the target chip; the twenty-first preset library does not contain a gate-level netlist designed by a design company of the target chip;

Determining modules and/or units and/or design information corresponding to a twenty-second part and/or a twenty-second part in the gate-level netlist of the chip, which are the same as and/or similar to a twenty-first part of the gate-level netlist in a twenty-second preset library and/or have a similarity greater than or equal to a thirty-ninth preset threshold, as IP cores called by the information and/or suspected to be called of the target chip and/or the target chip; a gate-level netlist designed for a design company of the target chip, and/or a gate-level netlist IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip in the twenty-second preset library;

determining an IP core called by the information and/or suspected to be called of the target chip and/or the target chip according to a gate-level netlist of the chip and a chip design layout and/or a design layout pattern, and one or more LVS verification software and/or tools and/or environments are used for performing LVS verification for one or more times and a result and/or report of failed LVS verification; the method of determination includes, but is not limited to, one or more of the following: determining modules and/or units and/or design information corresponding to the failed gate-level netlist part, and/or the failed chip design layout and/or design layout pattern area, and/or the failed part and/or the failed area in the verification as the IP core called and/or suspected to be called by the information of the target chip and/or the target chip; determining the difference between the device and/or connection relation in the gate-level netlist found in the verification and the device and/or connection relation in the chip design layout and/or design placement and routing diagram, and/or the gate-level netlist part corresponding to the difference, and/or the chip design layout and/or design placement and routing diagram area, and/or the module, and/or the unit, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

According to the gate-level netlist and the chip design layout and/or design layout pattern of the chip, after one or part of the number of the modules and/or the names of all the units are modified, one or more LVS verification software and/or tools and/or environments are used for performing LVS verification for one or more times, and the result and/or report of failed LVS verification, determining the IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the method of determination includes, but is not limited to, one or more of the following: determining a failed gate-level netlist part in verification, and/or a failed chip design layout and/or design layout pattern area, and/or an IP core called and/or suspected to be called for the information of the target chip and/or the target chip by the module and/or unit and/or design information corresponding to the failed part and/or the failed area; determining the difference between the device and/or connection relation in the gate-level netlist found in the verification and the device and/or connection relation in the chip design layout and/or design layout corresponding to the difference, and/or the gate-level netlist portion corresponding to the difference, and/or the chip design layout and/or design layout area, and/or the module, and/or the cell, and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

After the gate-level netlist of the chip is converted into a chip transistor-level netlist, the converted chip transistor-level netlist and a chip design layout and/or design layout wiring diagram are/is subjected to one or more LVS verification by using one or more LVS verification software and/or tools and/or environments, and the result and/or report of the failed LVS verification is/are obtained, so that the IP core of information calling and/or suspected calling of the target chip and/or the target chip is determined; the method of determination includes, but is not limited to, one or more of the following: determining IP cores called and/or suspected to be called for information of the target chip and/or the target chip by modules and/or units and/or design information corresponding to failed transistor-level netlist parts and/or failed chip design layouts and/or design layout areas and/or failed parts and/or failed areas in verification; determining the difference of the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference and/or the gate-level netlist part corresponding to the transistor-level netlist part, the gate-level netlist part corresponding to the corresponding chip design layout and/or design layout area, and/or a module, and/or a cell, and/or design information corresponding to the transistor-level netlist part, and/or the IP core called and/or suspected to be called for the information of the target chip and/or the target chip;

After the gate-level netlist of the chip is converted into a chip transistor-level netlist, the converted chip transistor-level netlist and a chip design layout and/or design layout wiring diagram are converted, after one or part of the number of the converted netlist or the names of all modules and/or units are modified, one or more LVS verification software and/or tools and/or environments are used for performing LVS verification for one or more times, and the result and/or report of the failed LVS verification determines the IP core of information call and/or suspected call of the target chip and/or the target chip; the method of determination includes, but is not limited to, one or more of the following: determining IP cores called and/or suspected to be called for information of the target chip and/or the target chip by modules and/or units and/or design information corresponding to failed transistor-level netlist parts and/or failed chip design layouts and/or design layout areas and/or failed parts and/or failed areas in verification; determining the difference of the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference and/or the gate-level netlist part corresponding to the transistor-level netlist part, the gate-level netlist part corresponding to the corresponding chip design layout and/or design layout area, and/or a module, and/or a cell, and/or design information corresponding to the transistor-level netlist part, and/or the IP core called and/or suspected to be called for the information of the target chip and/or the target chip;

According to the gate-level netlist of the chip and the chip design layout and/or design place-route graph, after modifying one or part of the number or all the names of the modules and/or units, converting the modified gate-level netlist into a netlist at the level of the chip transistor, determining the IP core of the target chip and/or the information calling and/or suspected calling of the target chip by using the converted netlist of the chip transistor level and the modified chip design layout and/or design layout diagram to perform one or more LVS verification in one or more LVS verification software and/or tools and/or environments and to obtain the result and/or report of the failed LVS verification; the method of determination includes, but is not limited to, one or more of the following: determining IP cores called and/or suspected to be called for the information of the target chip and/or the target chip by modules and/or units and/or design information corresponding to the failed transistor-level netlist part and/or the failed chip design layout and/or design layout area and/or the failed part and/or the failed area in the verification; determining the difference of the device and/or connection relation in the transistor-level netlist found in the verification, the transistor-level netlist part corresponding to the difference, the gate-level netlist part corresponding to the transistor-level netlist part corresponding to the gate-level netlist part, the gate-level netlist part corresponding to the chip design layout and/or design layout pattern region, the module, the cell and/or the design information, and calling and/or suspected calling IP cores for the information of the target chip and/or the target chip;

Determining an IP core called by information and/or suspected to be called by the target chip and/or the target chip according to two gate-level netlists of the chip, and results and/or reports of one or more formal verification methods and/or tools and/or environments for one or more times of formal verification; the method of determination includes, but is not limited to, one or more of the following: determining a failed gate-level netlist part in verification, and/or a module and/or unit and/or design information corresponding to the failed part as an IP core called by the target chip and/or the information of the target chip and/or suspected to be called; determining a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or unit and/or design information corresponding to the part and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining inequivalent parts found in verification, and/or gate-level netlist parts corresponding to the inequivalent parts, and/or modules and/or units and/or design information corresponding to the inequivalent parts as IP cores called and/or suspected to be called by the target chip and/or the information of the target chip; determining the difference of logic and/or functions in the two gate-level netlists found in the verification, and/or the gate-level netlist part corresponding to the difference, and/or the module and/or unit and/or design information as the target chip and/or the IP core called by the information of the target chip and/or the target chip;

Determining the IP core of the target chip and/or the information call and/or suspected call of the target chip according to two gate-level netlists of the chip, after modifying one or partial number of the chip or names of all modules and/or units, and using one or more formal verification software and/or tools and/or environments to perform one or more times of formal verification and fail formal verification results and/or reports; the method of determination includes, but is not limited to, one or more of the following: determining a failed gate-level netlist part in verification, and/or a module and/or unit and/or design information corresponding to the failed part as an IP core called by the target chip and/or suspected to be called; determining a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or a unit and/or design information corresponding to the part and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining inequivalent parts found in verification, and/or gate-level netlist parts corresponding to the inequivalent parts, and/or modules and/or units and/or design information corresponding to the inequivalent parts as IP cores called and/or suspected to be called by the target chip and/or the information of the target chip; determining the difference of logic and/or function in the two gate-level netlists found in the verification, and/or the gate-level netlist part corresponding to the difference, and/or the module and/or unit and/or design information as the target chip and/or the IP core suspected to be called by the information call of the target chip;

When the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the two gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the method for not verifying the function and/or logic corresponding to the difference includes but is not limited to: when the constants are set, the function and/or logic and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the function and/or logic and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logic and/or pins of the auxiliary design and/or auxiliary test include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the enable pin corresponding to the SCAN SCAN chain, the enable pin and/or the enable pin corresponding to the JTAG chain and/or the JTAG chain, and the corresponding pin and/or pin of the chip design for testability and/or design for testability.

14. The method of claim 1, wherein the second information comprises a chip RTL code, and/or a gate level netlist of a chip; the gate-level netlist of the chip includes, but is not limited to, one or more of the following: the final design is finished, and the final design comprises a gate-level netlist, a gate-level netlist corresponding to a chip design layout and/or a design layout pattern, a gate-level netlist formed by integrating chip RTL codes, a front-end gate-level netlist, a rear-end gate-level netlist and a gate-level netlist in the chip design process; the front-end gate-level netlist and/or the back-end gate-level netlist and/or the gate-level netlist in the chip design process comprise but are not limited to one or more gate-level netlists;

determining a position of a nineteenth mark in a chip RTL code and/or a part of the nineteenth mark and/or a part of the chip RTL code, wherein the code length between the nineteenth mark and the nineteenth mark is less than or equal to a forty-first preset threshold and/or a part of the chip RTL code, wherein the proportion of the code length between the nineteenth mark and the nineteenth mark in the chip RTL code is less than or equal to a fifth proportion threshold, and/or determining that a module and/or a unit and/or design information corresponding to the position and/or the part and/or the nineteenth mark is an IP core called and/or suspected to be called by the information of the target chip and/or the target chip; the nineteenth mark is a mark of a company other than the design company of the target chip and/or a mark representing a company other than the design company of the target chip;

determining a position of a twentieth mark in the chip RTL code and/or a part of the twentieth mark and/or a part of the chip RTL code, the code length of which is less than or equal to a forty-first preset threshold, and/or a part of the chip RTL code, the occupation ratio of which is less than or equal to a sixth proportion threshold, and/or a module and/or a unit and/or an IP core, the design information of which is called and/or suspected to be called by the position and/or the part and/or the twentieth mark, of which corresponds to the target chip and/or the target chip; the twentieth identification is an identification of a design company of the target chip and/or an identification of a design company representing the target chip;

Determining the target chip and/or the IP core of information calling and/or suspected calling of the target chip according to the part of other level descriptions except register transmission level descriptions in the chip RTL code; the other level descriptions besides register transfer level description include but are not limited to gate level descriptions; wherein, the determination method includes but is not limited to one or more of the following: determining one or more keywords existing in a chip RTL code, and/or determining that the total number of the one or more keywords existing in the chip RTL code is greater than or equal to a keyword corresponding to a forty-second preset threshold, and/or determining that a proportion of the total number of the one or more keywords existing in the chip RTL code occupying the whole chip RTL code is greater than or equal to a keyword corresponding to a forty-third preset threshold, and determining that the position and/or the part where the keyword is located, and/or a part where the code length between the keyword and the keyword is less than or equal to the forty-fourth preset threshold, and/or a part where the code length between the keyword and the chip RTL code occupying ratio is less than or equal to a seventh proportion threshold, and/or determining that the position and/or the part, and/or a module and/or unit and/or design information corresponding to the keyword are/is the target chip and/or the target chip RTL code And (3) an IP core for information calling and/or suspected calling of the piece, wherein the keywords are keywords representing other level descriptions besides the register transfer level description, and the categories of the keywords include but are not limited to one or more of the following: code at a characterization description level, words and/or phrases at a characterization description level, scripts at a characterization description level, programs at a characterization description level, netlists at a characterization description level, wherein the netlists include, but are not limited to, gate-level netlists; determining modules and/or units and/or design information corresponding to a twenty-fourth part and/or a twenty-fourth part in the RTL code of the chip, which are the same as and/or similar to the twenty-third part of the gate-level netlist of the chip and/or have similarity greater than or equal to a forty-fifth preset threshold, as IP cores called by the information and/or suspected to be called of the target chip and/or the target chip;

Determining modules and/or units and/or design information corresponding to a twenty-sixth part and/or a twenty-sixth part in the chip RTL code, which are the same as and/or similar to and/or have a similarity greater than or equal to a forty-sixth preset threshold with respect to a twenty-fifth part of the RTL code in a twenty-third preset library, as IP cores called and/or suspected to be called by the target chip and/or the target chip; the twenty-third preset library does not contain RTL codes designed by a design company of the target chip;

determining modules and/or units and/or design information corresponding to a twenty-eighth part and/or a twenty-eighth part in the chip RTL code, which are the same as and/or similar to a twenty-seventh part of the RTL code in a twenty-fourth preset library and/or have a similarity greater than or equal to a forty-seventh preset threshold, as IP cores called and/or suspected to be called by the target chip and/or the target chip; an RTL code designed for a design company of the target chip and/or an RTL code IP core library of the design company of the target chip and/or an IP core library of the design company of the target chip in the twenty-fourth preset library;

Determining an IP core called by the information and/or suspected to be called of the target chip and/or the target chip according to a gate-level netlist of a chip and a chip, and a result and/or report of formal verification which is not passed in one or more times of formal verification by using one or more formal verification software and/or tools and/or environments; the method of determination includes, but is not limited to, one or more of the following: determining a failed RTL code part and/or a failed gate-level netlist part in verification, and/or a module and/or a unit and/or design information corresponding to the failed part as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an RTL code part and/or a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or a unit and/or design information corresponding to the part and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an inequivalent part found in verification, and/or an RTL code part corresponding to the inequivalent part, and/or a gate-level netlist part corresponding to the inequivalent part, and/or a module and/or unit and/or design information corresponding to the inequivalent part as an IP core for information call and/or suspected call of the target chip and/or the target chip; determining differences of logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist and/or corresponding RTL code parts, and/or gate-level netlist parts, and/or modules and/or units and/or design information in the verification to be IP cores called and/or suspected to be called by the target chip and/or the information of the target chip;

Determining an information calling and/or suspected calling IP core of the target chip and/or the target chip according to a gate-level netlist of a chip RTL code and the chip, after one or part of the number of the modules and/or units is modified, and the result and/or report of failed formal verification in one or more times of formal verification by using one or more formal verification software and/or tools and/or environments; the method of determination includes, but is not limited to, one or more of the following: determining a failed RTL code part and/or a failed gate-level netlist part in verification, and/or a module and/or a unit and/or design information corresponding to the failed part as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an RTL code part and/or a gate-level netlist part corresponding to a mismatch point found in verification, and/or a module and/or a unit and/or design information corresponding to the part and/or the mismatch point as an IP core called and/or suspected to be called by the target chip and/or the information of the target chip; determining an inequivalent part found in verification, and/or an RTL code part and/or a gate-level netlist part corresponding to the inequivalent part, and/or a module and/or a unit and/or design information corresponding to the inequivalent part as an IP core called and/or suspected to be called by the target chip and/or the target chip; determining differences of logic and/or functions in the RTL code and logic and/or functions in the gate-level netlist and/or corresponding RTL code parts, and/or gate-level netlist parts, and/or modules and/or units and/or design information in the verification to be IP cores called and/or suspected to be called by the target chip and/or the information of the target chip;

When formal verification is carried out, if the functions and/or logics of the auxiliary design and/or auxiliary test are different between the RTL code and the gate-level netlist, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the method for not verifying the function and/or logic corresponding to the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

15. The method according to claim 1, wherein the determining of the information in the target chip and/or the information of the target chip, whether to call the IP core and/or whether to call the IP core is suspected, the used preset threshold and/or identifier and/or preset library and/or the area and/or part thereof according to the first information is the same as or different from the determining of the information of the target chip and/or the target chip, the called and/or suspected IP core, the used preset threshold and/or identifier and/or preset library and/or the area and/or part thereof according to the second information;

16. The method of claim 1, wherein the IP cores include, but are not limited to, non-self-developed IP cores and/or self-developed IP cores;

17. The method of any one of claims 1, or 5-14, further comprising:

determining whether the information of the target chip and/or the target chip, the called and/or suspected called IP core is a non-self-researched IP core and/or a self-researched IP core according to the first information and/or the second information and/or the information of the target chip and/or the design file of the target chip and/or the authorization data of the target chip; and/or

Determining the information of the target chip and/or the target chip according to second information, calling and/or suspected calling IP cores, and simultaneously determining whether the IP cores are non-self-grinding IP cores and/or self-grinding IP cores;

the method for determining that the target chip and/or the information, calling and/or suspected calling IP core of the target chip are/is a non-self-research IP core includes but is not limited to one or more of the following:

Determining the IP core as a non-self-research IP core according to the content corresponding to the blank area and/or the blank area in the chip design layout and/or layout;

determining the IP core as a non-self-research IP core according to the inconsistency of the chip design layout and/or the comparison of the chip real object and/or the real object layout and/or the comparison of the real object layout and/or the content corresponding to the inconsistency;

the IP core determined by the twenty-first identifier in the third information of the target chip is a non-self-research IP core; the twenty-first mark is a mark of a company other than the design company of the target chip and/or a mark representing the company other than the design company of the target chip;

determining that the IP core is a non-self-research IP core according to the twenty-sixth area in the third information of the target chip, which is the same as and/or similar to the twenty-fifth area of the information in the twenty-fifth preset library and/or has the similarity larger than or equal to a forty-eighth preset threshold, and/or the content corresponding to the twenty-sixth area; the twenty-fifth preset library does not contain the information designed by the design company of the target chip;

The IP core determined by the content corresponding to the thirtieth part and/or the thirtieth part in the third information of the target chip, which is the same as and/or similar to the twenty-ninth part of the information in the twenty-sixth preset library and/or has the similarity larger than or equal to the forty-ninth preset threshold, is a non-self-research IP core; the twenty-sixth preset library does not contain information designed by a design company of the target chip;

determining the IP core as a non-self-research IP core by determining the positions and/or areas of chip real objects and/or real object layouts and/or real object layout and/real object layout and/real object layout real object and/real object layout and/real object layout real object and/real object layout real object of the real object and/real object of the IP chip of the IP core;

performing one or more LVS verification according to one or more LVS verification software and/or tools and/or environments, and reporting the result of failed LVS verification and/or reporting that the determined IP core is a non-self-developed IP core;

Performing one or more formal verification according to one or more formal verification software and/or tools and/or environments, wherein the determined IP core is a non-self-developed IP core according to the results and/or reports of failed formal verification;

determining that the IP core is a non-self-developed IP core according to the other level descriptions except the register transmission level description in the chip RTL code;

aiming at the information calling and/or suspected calling IP core of the target chip and/or the target chip, if the IP core is determined not to be the information calling and/or suspected calling self-research IP core of the target chip and/or the target chip, the IP core is a non-self-research IP core called and/or suspected calling information calling and/or the target chip in the target chip;

the method for determining the target chip and/or the information, calling and/or suspected calling IP core of the target chip as the self-research IP core includes but is not limited to one or more of the following:

the IP core determined by the twenty-second identifier in the third information of the target chip is a self-research IP core; the twenty-second identifier is an identifier of a design company of the target chip and/or an identifier of a design company representing the target chip;

Determining that the IP core is a self-research IP core according to the content corresponding to the twenty-eighth area and/or the twenty-eighth area in the third information of the target chip, which is the same as and/or similar to the twenty-seventh area of the information in the twenty-seventh preset library and/or has the similarity larger than or equal to the fifty-fifth preset threshold; the twenty-seventh preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

the IP core determined by the content corresponding to the thirty-second part and/or the thirty-second part in the third information of the target chip, which is the same as and/or similar to the thirty-first part of the information in the twenty-eighth preset library and/or has the similarity larger than or equal to the fifty-first preset threshold, is a self-research IP core; the twenty-eighth preset library is information designed for a design company of the target chip, and/or an information IP core library of the design company of the target chip, and/or an IP core library of the design company of the target chip;

determining a chip design layout and/or design information corresponding to a position and/or area of a chip real object and/or a real object layout and/or layout pattern of a self-research IP core, and determining the IP core as the position and/or area of the chip design layout and/or design layout pattern corresponding to the IP core, and/or the module and/or unit and/or design information corresponding to the position and/or area;

Aiming at the information calling and/or suspected calling IP core of the target chip and/or the target chip, if the IP core is determined not to be the information calling and/or suspected calling non-self-research IP core of the target chip and/or the target chip, the IP core is the information calling and/or suspected calling self-research IP core of the target chip and/or the target chip;

wherein, the third information of the target chip includes but is not limited to one or more of the following: the method comprises the following steps of designing a chip, designing a layout and/or a layout and/or a layout pattern, a chip real object and/or a real object layout pattern, a schematic diagram of the chip, a netlist of a chip transistor level, a gate-level netlist of the chip, a chip RTL code, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information;

the twenty-fifth preset library and/or the twenty-sixth preset library and/or the twenty-seventh preset library and/or the twenty-eighth preset library and/or the information designed by the design company of the target chip, and/or the information in the information IP core library of the design company of the target chip, include but are not limited to one or more of the following types of information: layout and/or place-and-route patterns, schematic diagrams, transistor-level netlists, gate-level netlists, RTL codes.

18. The method of claim 1 or 16, further comprising: judging the autonomy and/or controllability of the chip; the method of the determination includes, but is not limited to, one or more of the following:

determining one or more fourth information required for determining the autonomy and/or controllability of the chip, the fourth information including, but not limited to, one or more of: the chip comprises a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a chip transistor-level netlist, a chip gate-level netlist, a chip RTL code, all or part information of one or more kinds of information in first information, all or part information of one or more kinds of information in second information, and other information of the chip except the first information and the second information;

distributing a score corresponding to each kind of the required one or more kinds of fourth information; the method for assigning the score includes but is not limited to: assigning a score according to the difficulty and/or criticality of the implementation and/or design of each fourth information;

For each kind of the required fourth information, if the obtained kind of fourth information does not include all the kind of information of the chip to be determined, and/or does not include all functions and/or all logics and/or all modules and/or all units of the chip to be determined, and/or if the obtained kind of fourth information calls a non-self-research IP core and/or is suspected to call a non-self-research IP core, the chip obtains a score as: subtracting the score corresponding to the part of the information to be determined, which is absent in the obtained fourth information, and/or the absent function and/or the absent logic and/or the absent module and/or the absent unit, from the score corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information, and then, remaining the score; and/or the chip obtains the score as follows: a score corresponding to the fourth information, a score obtained by subtracting a first proportion of scores corresponding to the information part and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit of the chip to be judged which is missing in the fourth information, and a score obtained by subtracting a second proportion of scores corresponding to the non-self-research IP core which is called and/or suspected to be called in the fourth information; wherein, if the part of the information to be determined of the chip and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit in the obtained fourth information have repeated and/or overlapped contents with the non-self-research IP core called and/or suspected to be called in the obtained fourth information, the score is reduced once and/or not repeated and reduced for the repeated and/or overlapped contents; wherein, the determination method of the first proportion and/or the second proportion comprises but is not limited to one or more of the following: a ratio of less than or equal to 1, a ratio of greater than or equal to 0, a ratio of the missing information portion of the chip to be determined and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit when in country is less than or equal to a ratio when in non-country, a ratio of the called and/or suspected called non-self-study IP cores when in country is less than or equal to a ratio of the non-self-study IP cores when in non-country;

For each kind of the required fourth information, if the obtained kind of fourth information includes all the kind of information of the chip to be determined and/or includes all functions and/or all logics and/or all modules and/or all units of the chip to be determined, and the obtained kind of fourth information does not call a non-self-research IP core and is not suspected to call a non-self-research IP core, the chip obtains a score as: the score corresponding to the fourth information;

for each type of the required fourth information, if the type of the fourth information is not acquired and/or the acquired type of the fourth information cannot be confirmed to be the fourth information of the chip, the chip does not acquire a score under the type of the fourth information;

summing the actual scores obtained by the chip aiming at each of the one or more kinds of required fourth information to serve as the total score of the chip, and judging the autonomy and/or the controllability of the chip through the total score;

wherein, in a case that the obtained fourth information does not include all of the information of the chip to be determined and/or does not include all of the functions and/or all of the logics and/or all of the modules and/or all of the units of the chip to be determined, the non-self-developed IP core is called in other information after the design of the fourth information is completed, and the function and/or the logic and/or the module and/or the unit corresponding to the IP core is not designed in the fourth information;

When the required one or more fourth information is assigned with the scores corresponding to the various fourth information, it is required to ensure that the scores corresponding to the same degree of autonomy and/or controllability of a chip with a given function are the same under different schemes; the implementation method for ensuring that the scores corresponding to the same degree of autonomy and/or controllability are the same includes but is not limited to: under different schemes, the sum of the scores corresponding to the required various fourth information of a chip with a given function is the same;

determining various functions and/or logics and/or modules and/or units required for determining the autonomy and/or controllability of the chip;

assigning, for each of the various functions and/or logics and/or modules and/or units of need, a score corresponding to that function and/or logic and/or module and/or unit; the method for assigning the score includes but is not limited to: assigning a score based on the ease and/or criticality of each function and/or logic and/or module and/or unit, implementation and/or design;

for each required function and/or logic and/or module and/or unit, if the chip has no non-self-research IP core called and is not suspected to call in the function and/or logic and/or module and/or unit, the chip obtains a corresponding score value of the function and/or logic and/or module and/or unit;

For each of said required functions and/or logic and/or modules and/or units, if a non-self-developed IP core is called and/or suspected to be called in the function and/or logic and/or module and/or unit of said chip to be determined, said chip does not obtain a score corresponding to the function and/or logic and/or module and/or unit and/or said chip obtains a score corresponding to the function and/or logic and/or module and/or unit at a third ratio of scores; wherein, the determination method of the third proportion includes but is not limited to one or more of the following: the ratio is less than or equal to 1, the ratio is greater than or equal to 0, and the ratio of the called and/or suspected called non-self-researched IP core when the called and/or suspected called non-self-researched IP core is in a state is greater than or equal to the ratio of the called and/or suspected called non-self-researched IP core when the called and/or suspected called non-self-researched IP core is in a state;

for each of said required functions and/or logics and/or modules and/or units, if said chip is to be determined to lack such function and/or logic and/or module and/or unit, said chip does not obtain a score under such function and/or logic and/or module and/or unit;

summing the actual scores obtained by the chip aiming at each function and/or logic and/or module and/or unit in the various required functions and/or logics and/or modules and/or units to serve as the total score of the chip, and judging the autonomy and/or controllability of the chip through the total score;

When the scores corresponding to the various functions and/or logics and/or modules and/or units are distributed for the various required functions and/or logics and/or modules and/or units, it is required to ensure that the scores corresponding to the chips with a given function are the same under different schemes and with the same degree of autonomy and/or controllability; the implementation method for ensuring that the scores corresponding to the same degree of autonomy and/or controllability are the same includes but is not limited to: the sum of the scores corresponding to the various functions and/or logics and/or modules and/or units required by a given function chip under different schemes is the same.

19. The method according to claim 18, wherein the score corresponding to the part of the information to be determined chip and/or the missing function and/or the missing logic and/or the missing module and/or the missing unit that is missing in the obtained fourth information, and/or the score corresponding to the non-self-research IP core called and/or suspected to be called in the obtained fourth information, comprises but is not limited to one or more of the following:

for the needed fourth information, the scores corresponding to various functions and/or logics and/or modules and/or units are distributed for the various functions and/or logics and/or modules and/or units, and the sum of the scores corresponding to the various functions and/or logics and/or modules and/or units is the score corresponding to the fourth information; the method for assigning the score includes but is not limited to: assigning a score based on the ease and/or criticality of each function and/or logic and/or module and/or unit, implementation and/or design;

Finding out the information part and/or function and/or logic and/or module and/or unit of the chip to be judged which is lacked in the obtained fourth information from various functions and/or logics and/or modules and/or units in the needed fourth information, wherein the sum of the scores or scores distributed by the part of the functions and/or logics and/or modules and/or units is the score corresponding to the information part of the chip to be judged which is lacked in the obtained fourth information and/or the lacked function and/or logic and/or module and/or unit;

and finding out functions and/or logics and/or modules and/or units corresponding to the called and/or suspected called non-self-researched IP cores in the obtained fourth information from various functions and/or logics and/or modules and/or units in the required fourth information, wherein the sum of the scores or the scores distributed by the parts of the functions and/or logics and/or modules and/or units is the score corresponding to the called and/or suspected called non-self-researched IP cores in the obtained fourth information.

20. The method of claim 1, further comprising confirming that the obtained information is information of the target chip; the information includes, but is not limited to, one or more of the following: the method comprises the following steps of designing a chip design layout and/or a chip real object and/or a real object layout, a schematic diagram of the chip, a transistor-level netlist of the chip, a gate-level netlist of the chip, an RTL code of the chip, all or part information of one or more kinds of information in first information, and all or part information of one or more kinds of information in second information; other information of the chip except the first information and the second information; the method of confirmation includes, but is not limited to, one or more of the following:

The acquired information, which is declared or identified as the information of the target chip;

determining the obtained chip real object and/or real object layout and/or layout and layout as the information of the target chip;

comparing and/or verifying the acquired information to determine whether the information is the information of the target chip, including but not limited to one or more of the following: comparing and/or verifying the acquired information with information which is declared or identified as the target chip for one or more times, wherein if the comparison and/or verification is passed, the acquired information is the information of the target chip; comparing and/or verifying the acquired information with a chip real object and/or a real object layout, wherein if the comparison and/or verification is passed, the acquired information is the information of the target chip;

and comparing and/or verifying the acquired information with the information which is confirmed to be the target chip through comparison and/or verification for one time or more times, wherein if the comparison and/or verification is passed, the acquired information is the information of the target chip.

21. The method of claim 20, wherein the alignment and/or validation includes, but is not limited to, one or more of:

comparing the chip design layout and/or design layout wiring diagram with the chip real object and/or real object layout wiring diagram;

comparing the chip design layout and/or design layout wiring diagram with the chip real object and/or real object layout wiring and/or remaining chip real object and/or real object layout wiring and/or real object layout wiring and/or unit of the non-self-researched IP core after removing the part and/or area and/or module and/or unit of the non-self-researched IP core which is confirmed as calling or calling of the target chip;

performing LVS verification on a schematic diagram of a chip and a chip design layout and/or a design layout and wiring diagram;

After the schematic diagram of the chip, and the chip design layout and/or design layout diagram are removed, the schematic diagram of the rest chip, and the rest chip design layout and/or design layout diagram are subjected to LVS verification after the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip is removed;

performing LVS verification on the netlist of the chip transistor level and a chip design layout and/or a design layout wiring diagram;

after the netlist of the chip transistor level, and the chip design layout and/or design layout are removed, and parts and/or regions and/or modules and/or units and/or design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip are removed, performing LVS verification on the netlist of the rest chip transistor level, and the rest chip design layout and/or design layout;

performing LVS verification on the gate-level netlist of the chip and a chip design layout and/or a design layout pattern;

After removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip, the gate-level netlist of the chip, and the design layout and/or the design layout are subjected to LVS verification;

after converting the gate-level netlist of the chip into a chip transistor-level netlist, performing LVS verification on the converted chip transistor-level netlist and a chip design layout and/or a design layout pattern;

after the gate-level netlist of the chip is converted into a chip transistor-level netlist, the converted chip transistor-level netlist and a chip design layout and/or design layout wiring pattern are removed, and after parts and/or regions and/or modules and/or units and/or design information of a non-self-researched IP core which is confirmed to be called or suspected to be called by a target chip is removed, LVS verification is carried out on the rest chip transistor-level netlist and the rest chip design layout and/or design layout wiring pattern;

After removing the part and/or area and/or module and/or unit and/or design information of the non-self-grinding IP core which is confirmed to be called or suspected to be called by the target chip, converting the rest gate-level netlist into a transistor-level netlist, and performing LVS verification on the converted transistor-level netlist and the rest chip design layout and/or design layout;

performing formal verification on one gate-level netlist of the chip and the other gate-level netlist of the chip;

after removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip, performing formal verification on the one-level netlist of the rest chip and the other-level netlist of the rest chip;

performing formal verification on a RTL code of the chip and a gate-level netlist of the chip;

after removing the part and/or the area and/or the module and/or the unit and/or the design information of the non-self-researched IP core which is confirmed to be called or suspected to be called by the target chip, performing formal verification on the RTL code of the rest chip and the gate-level netlist of the rest chip;

When the formal verification is carried out, if the functions and/or logics of the auxiliary design and/or the auxiliary test are different between the two verified gate-level netlists and/or between the verified RTL code and the gate-level netlists, the functions and/or logics corresponding to the differences are not verified or verified; wherein, the method for not verifying the function and/or logic corresponding to the difference includes but is not limited to: when the constants are set, the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are forbidden and/or the functions and/or logics and/or pins of the auxiliary design and/or auxiliary test are set to be invalid; the functional and/or logical and/or pins of the design and/or test aids include, but are not limited to, one or more of the following: the SCAN SCAN chain and/or the SCAN SCAN chain correspond to the enable pins and/or the enable pins, the JTAG chain and/or the JTAG chain correspond to the enable pins and/or the enable pins, and the chip testability design and/or the testability design correspond to the pins and/or the pins.

22. The method of any one of claims 1-15, including but not limited to one or more of:

the chip design layout and/or design place-and-route pattern, and/or the chip design layout and/or design place-and-route pattern, including but not limited to all layers and/or part of layers and/or one layer of the chip design layout and/or design place-and-route pattern, for one layer, the chip design layout and/or design place-and-route pattern includes, but is not limited to, a chip design layout and/or design place-and-route pattern for an entire area and/or for a plurality of local areas and/or for one local area; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different;

The chip entity and/or entity layout pattern, and/or the chip entity and/or entity layout pattern in the region, including but not limited to all layers and/or part layers and/or one layer of chip entity and/or entity layout pattern, for one layer, the chip entity and/or entity layout pattern includes but not limited to the chip entity and/or entity layout pattern of the whole region and/or a plurality of local regions and/or one local region An object layout wiring and/or a physical layout wiring diagram; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different;

the layout and/or place-and-route patterns, and/or the regions in the layout and/or place-and-route patterns in the preset library, including but not limited to all layers and/or partial layers and/or one layer of layout and/or place-and-route patterns, for one of the layers, the layout and/or place-and-route patterns include but not limited to the layout and/or place-and-route patterns of the whole region and/or a plurality of partial regions and/or one partial region; wherein the position and/or the range of the whole area and/or a plurality of local areas and/or a local area of different layers are the same or different;

A schematic diagram of the chip, and/or a region in the schematic diagram of the chip, including but not limited to the whole region and/or a plurality of partial regions and/or a chip schematic diagram of a partial region;

schematic diagrams in the preset library and/or areas in the schematic diagrams, including but not limited to schematic diagrams of the whole area and/or a plurality of local areas and/or one local area;

the chip transistor-level netlist, and/or portions of a transistor-level netlist, include, but are not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level;

the transistor-level netlist, and/or the portions of the transistor-level netlist in the preset library include, but are not limited to: a netlist of a whole transistor level, a netlist of a partial transistor level;

the gate level netlist, and/or portions of the gate level netlist of the chip, include, but are not limited to: the whole gate-level netlist and a part of gate-level netlist;

the gate level netlist in the preset library, and/or the portion of the gate level netlist, include but are not limited to: the whole gate-level netlist and a part of gate-level netlist;

the chip RTL code, and/or portions of RTL code, include, but are not limited to, one or more of: the whole RTL code, part of the RTL code, the RTL code claimed by the design company of the target chip, and the code designed by the design company of the target chip in the RTL design stage;

The RTL code in the preset library, and/or portions of the RTL code, include but are not limited to: the whole RTL code and part of the RTL code;

the chip design layout and/or design place-and-route patterns include, but are not limited to, one or more of the following: a comment and/or description in the chip design layout and/or design layout pattern;

the chip real object and/or real object layout and/or layout of the chip real object and/or real object layout and/or layout of the chip real object and/or real object layout and/or layout of the chip real object layout and/or layout of the chip real object and/or the chip real object layout of the chip real object layout and/or the layout of the chip of the: annotation and/or description in chip real object and/or real object layout wiring diagram;

the schematic diagram of the chip includes, but is not limited to, one or more of the following: schematic diagram of the chip, comments and/or explanations in the schematic diagram of the chip;

the netlist at the chip transistor level includes, but is not limited to, one or more of the following: a netlist at the chip transistor level, comments and/or descriptions in the netlist at the chip transistor level;

The gate-level netlist of the chip includes, but is not limited to, one or more of the following: a gate-level netlist of the chip, comments and/or descriptions in the gate-level netlist of the chip;

the chip RTL code includes but is not limited to one or more of the following: chip RTL code, comments and/or descriptions in the chip RTL code;

23. An apparatus for detecting an IP core call, comprising:

24. An electronic device comprising a memory, a processor, and a program stored on the memory and executable on the processor; characterized in that the processor implements the steps in the detection method of an IP core call according to any one of claims 1 to 22 when executing said program.

25. A readable storage medium on which a program is stored, the program, when executed by a processor, implementing the steps in the method of detection of an IP core call according to any one of claims 1 to 22.