CN114647604A - DMA data transmission method, system, electronic equipment and readable storage medium - Google Patents
DMA data transmission method, system, electronic equipment and readable storage medium Download PDFInfo
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- CN114647604A CN114647604A CN202210537252.2A CN202210537252A CN114647604A CN 114647604 A CN114647604 A CN 114647604A CN 202210537252 A CN202210537252 A CN 202210537252A CN 114647604 A CN114647604 A CN 114647604A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/282—Cycle stealing DMA
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The invention relates to the technical field of data transmission, and discloses a DMA (direct memory access) data transmission method, a system, an electronic device and a readable storage medium.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a DMA data transmission method, a system, electronic equipment and a readable storage medium.
Background
In the design process of the MCU chip, direct data transmission of peripheral modules such as ADC/SPI/UART and the like and a memory (such as SRAM) requires a core of the MCU to execute a section of program to realize data transmission, for example, the MCU core reads the result of the ADC and puts the result into the SRAM. When a large amount of data needs to be transmitted from the peripheral module to the SRAM, the MCU core can only perform the data transmission task, thereby terminating other tasks such as operation and the like.
Therefore, people design a DMA module, the DMA is short for Direct Memory Access, the Chinese name is generally Direct Memory storage, and data transmission between the peripheral module and the SRAM can be automatically completed without the intervention of an MCU core. When data transmission is needed, a request is sent to terminate the operation of the MCU core, the peripheral module and the SRAM are controlled to carry out data transmission once, and after the transmission is finished, an ending command is sent to enable the MCU core to continue to control the bus to enter other operations, so that a large amount of time spent on inquiring the peripheral module by the MCU core is saved. However, according to the above technical solutions, the DMA still needs to suspend the operation of the MCU core, thereby occupying the bus, and the two cores cannot operate simultaneously, which still loses the operating efficiency.
Disclosure of Invention
The invention aims to overcome the problem of low efficiency of the existing DMA transmission method, and provides a DMA data transmission method, a system, electronic equipment and a readable storage medium.
In order to achieve the above object, the present invention provides a DMA data transmission method, which includes the following steps:
acquiring an instruction sent by an MCU (microprogrammed control Unit), acquiring the number of clock cycles executed by the instruction and whether each corresponding clock cycle occupies a bus according to the instruction, and calculating the maximum total number of continuous clock cycles continuously occupying the bus in all clock cycles according to an instruction running sequence, wherein at least one clock cycle does not occupy the bus in all clock cycles; when the clock period of instruction execution does not occupy the bus, the MCU controller sends an idle indication to the DMA controller;
the DMA controller judges whether a peripheral module generates new data or not, and when the peripheral module generates new data and the DMA controller receives an idle instruction, the DMA controller controls the peripheral module and the memory to complete data transmission, wherein the number of data output clock cycles of the peripheral module which generates data once is adjusted according to the maximum total number of continuous clock cycles, so that the data generated by the peripheral module every time can be transmitted.
As an implementation, the peripheral module includes one or more of an ADC module/SPI module/UART module/I2C module/USB interface/external storage, and the memory includes SRAM.
As an implementation manner, the adjustment rule for adjusting the number of data output clock cycles of the peripheral module per output of data according to the maximum total number of consecutive clock cycles includes: and setting the number of data output time periods of the data output twice by the peripheral module to be larger than the maximum total number of continuous clock periods.
As an implementation manner, the rule for adjusting the number of data output clock cycles of the peripheral module per output of data according to the maximum total number of consecutive clock cycles further includes: and setting the number of data output time periods of the data output by the peripheral module for outputting the data once to be less than or equal to the maximum total number of continuous clock periods.
As an implementable embodiment, when the MCU controller is specifically of the 8051-MCU type, the instructions include one or more of an immediate data addressing instruction, including ADD a, # data, a jump instruction, MOV direct, a, ADD a, Rn, ADD a, @ Ri, the immediate data addressing instruction including SJMP rel; wherein, the clock cycle for executing ADD A, # data is 2 and none of the 2 clock cycles occupies the bus, the clock cycle for executing SJMP rel is 2 and none of the 2 clock cycles occupies the bus, the clock cycle for executing ADD A, Rn is 1 and the clock cycle occupies the bus; executing MOV direct, wherein the clock period of A is 2, the first clock period occupies the bus and the second clock period does not occupy the bus in the 2 clock periods; ADD A is executed with 2 clock cycles of @ Ri and all 2 clock cycles occupy the bus.
As an implementation mode, when the sequentially executed instructions are ADD A, Rn, MOV direct, A, ADD A, @ Ri, ADD A, # data and SJMP rel, the maximum continuous clock period total number of the continuously occupied bus is 2, and the data output time period of the peripheral module is set to be 2.
Correspondingly, the invention also provides a DMA data transmission system, which comprises the following modules:
an idle instruction sending module: acquiring an instruction sent by an MCU (microprogrammed control Unit), acquiring the number of clock cycles executed by the instruction and whether each corresponding clock cycle occupies a bus according to the instruction, and calculating the maximum total number of continuous clock cycles continuously occupying the bus in all clock cycles according to an instruction running sequence, wherein at least one clock cycle does not occupy the bus in all clock cycles; when the clock period of instruction execution does not occupy the bus, the MCU controller sends an idle indication to the DMA controller;
a data transmission module: the DMA controller judges whether a peripheral module generates new data or not, and when the peripheral module generates new data and the DMA controller receives an idle instruction, the DMA controller controls the peripheral module and the memory to complete data transmission, wherein the number of data output clock cycles of the peripheral module which generates data once is adjusted according to the maximum total number of continuous clock cycles, so that the data generated by the peripheral module every time can be transmitted.
As an implementation manner, the adjustment rule for adjusting the number of data output clock cycles of the peripheral module per output of data according to the maximum total number of consecutive clock cycles includes: and setting the number of data output time periods of the data output twice by the peripheral module to be larger than the maximum total number of continuous clock periods.
Accordingly, the present invention provides an electronic device comprising: at least one processor, a memory communicatively coupled to at least one of the processors; at least one of the processors is configured to read a program in the memory for performing any of the methods.
Accordingly, the present invention provides a computer-readable storage medium having stored thereon instructions which, when executed on a computer, cause the computer to perform the method.
The invention has the beneficial effects that: the invention provides a DMA data transmission method, a system, an electronic device and a readable storage medium, when a clock cycle executed by an instruction does not occupy a bus, an MCU (micro control unit) controller sends an idle indication to a DMA controller, the DMA controller judges whether a peripheral module has new data output, and when the peripheral module has the new data and the DMA controller receives the idle indication, the DMA controller controls the peripheral module and a memory to complete data transmission, so that the DMA controller performs data transmission of a chip memory and the peripheral module while the MCU controller works normally, the working efficiency is greatly improved, and simultaneously, the data transmission of the chip memory and the peripheral module can be automatically completed without omission by setting a data output time period of the peripheral module.
Drawings
FIG. 1 is a block diagram illustrating a DMA data transfer method according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of an MCU controller, a DMA controller, a peripheral module, and a memory in the DMA data transmission method according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present embodiment provides a technical solution: a DMA data transfer method comprising the steps of:
step S100, acquiring an instruction sent by the MCU controller, obtaining the number of clock cycles executed by the instruction and whether each corresponding clock cycle occupies the bus according to the instruction, and calculating the maximum total number of continuous clock cycles continuously occupying the bus in all clock cycles according to an instruction running sequence, wherein at least one clock cycle does not occupy the bus; when the clock period of instruction execution does not occupy the bus, the MCU controller sends an idle indication to the DMA controller;
step S200, the DMA controller judges whether a peripheral module generates new data or not, and when the peripheral module generates new data and the DMA controller receives an idle instruction, the DMA controller controls the peripheral module and a memory to complete data transmission, wherein the number of data output clock cycles of the peripheral module which generates data once is adjusted according to the maximum total number of continuous clock cycles, so that the data generated by the peripheral module each time can be transmitted.
It should be noted that: the method is suitable for various MCU designs, and can be adopted no matter the MCU of RISC or CISC instruction, as long as the instruction incompletely occupies the bus in the instruction execution process.
Step S100 is executed, the peripheral module includes one or more of an ADC module/SPI module/UART module/I2C module/USB interface/external memory, and the memory includes an SRAM, as shown in fig. 2, the MCU controller, the DMA controller, the peripheral module, and the memory are all connected to the bus, and the MCU controller sends an idle indication to the DMA controller when the clock cycle of instruction execution does not occupy the bus.
In this embodiment, when the model of the MCU controller is specifically 8051-MCU, the instruction includes one or more of an immediate data addressing instruction, a jump instruction, MOV direct, a, ADD a, Rn, ADD a, @ Ri, the immediate data addressing instruction includes ADD a, # data, and the jump instruction includes SJMP rel; wherein, the clock cycle for executing ADD A, # data is 2 and none of the 2 clock cycles occupies the bus, the clock cycle for executing SJMP rel is 2 and none of the 2 clock cycles occupies the bus, the clock cycle for executing ADD A, Rn is 1 and the clock cycle occupies the bus; executing MOV direct, wherein the clock period of A is 2, the first clock period occupies the bus and the second clock period does not occupy the bus in the 2 clock periods; the clock period for executing ADD A, @ Ri is 2 and the 2 clock periods do not occupy the bus, but when other instructions are executed or the MCU controller is of other types, the execution is carried out according to the actually executed instructions.
Specifically, some of the instructions sent by the MCU controller do not need bus support to operate, for example, when the instruction is ADD a, # DATA of an immediate address instruction, the instruction indicates an a register and an immediate DATA operation, and the result is written back to the a register, the clock cycle of the corresponding instruction execution is 2 and the 2 clock cycles do not occupy the bus; for example, when the instruction is an SJMP rel of a jump instruction, the instruction jumps to a relative address in short, rel represents-128 to +127 bytes, the clock cycle of the corresponding instruction execution is 2, and the 2 clock cycles do not occupy the bus; some instructions require multiple clock cycles during execution, some clock cycles do not occupy the bus, and other clock cycles occupy the bus, such as: MOV direct, a; when the instruction is MOV direct, A, the clock cycle executed by the corresponding instruction is 2, and the first clock cycle occupies the bus and the second clock cycle does not occupy the bus in the 2 clock cycles; of course, there are other instructions with clock cycles occupying the bus, for example, when the instruction is ADD a, Rn, the corresponding instruction executes 1 clock cycle and the clock cycle occupies the bus, and when the instruction is ADD a, @ Ri, the corresponding instruction executes 2 clock cycles and the 2 clock cycles all occupy the bus.
Step S200 is executed, and it should be noted that, in the prior art, for the peripheral module, the data generated last time is eliminated every time the peripheral module generates new data, and the number of data generation clock cycles of the peripheral module per data generation is adjustable, so that in order to implement the non-missing transmission of the data generated by the peripheral module, the number of data generation clock cycles of the peripheral module per data generation needs to be adjusted according to the maximum number of consecutive clock cycles.
In order to complete the data transmission of the memory and the peripheral module without omission, the adjustment rule that the number of data output clock cycles of data output by the peripheral module every time is adjusted according to the maximum total number of continuous clock cycles comprises the following steps: and setting the number of data output time periods of the data output twice by the peripheral module to be larger than the maximum total number of continuous clock periods.
Further, in order to maximize the efficiency of data transmission, the adjustment rule for adjusting the number of data output clock cycles of the peripheral module, which outputs data once, according to the maximum total number of consecutive clock cycles further includes: and setting the number of data output time periods of the data output by the peripheral module for outputting the data once to be less than or equal to the maximum total number of continuous clock periods.
For example: when the 5 instructions of ADD a, Rn, MOV direct, a, ADD a, @ Ri, ADD a, # data, SJMP rel are sequentially and circularly executed, the maximum total number of continuous clock cycles of the continuously occupied bus is 2, specifically as shown in table 1, when the 5 instructions of ADD a, Rn, MOV direct, a, ADD a, # data, SJMP 1 are sequentially and circularly executed, it can be seen that the maximum total number of continuous clock cycles of the continuously occupied bus is 2, that is, the bus time of 2 clock cycles is occupied by the third instruction between the 2 instructions and the fourth instruction, then in order to ensure that the data generated by the peripheral module can be exchanged without omission, the number of clock cycles of the data generated by the peripheral module twice is greater than 2, because if the number of clock cycles of the data generated by the peripheral module twice is less than or equal to 2, specifically, the peripheral module forms a new data in each of two clock cycles of a continuously occupied bus, and after the peripheral module forms the new data in the first clock cycle of the occupied bus, the MCU controller still cannot send an idle indication to the DMA controller because the bus is still in an busy state, and before the data generated in the first clock cycle is completely transmitted, the peripheral module continues to generate the new data again in the second clock cycle, and at this time, since the new data is formed again, the data generated in the first clock cycle by the peripheral module is to be eliminated, but the data generated in the first clock cycle is not transmitted to the memory, therefore, the missing condition is generated, and the data output time period number of the data output twice by the peripheral module is set to be larger than the maximum continuous clock period total number, so that the data output every time by the peripheral module can be transmitted, and the condition that the data generated last time is not transmitted and is eliminated after new data is generated is avoided.
Further, in order to ensure the maximum rate of data transmission, when the maximum total number of consecutive clock cycles is 2, the number of clock cycles of the data generated by the peripheral module at one time may be set to be less than or equal to 2; and on the premise of ensuring that the data output by the peripheral module at each time can be transmitted, the number of data output clock cycles of the data output by the peripheral module at one time can only be 2.
| Serial number | Instruction | Clock cycles for instruction execution | Bus occupation |
| 1 | ADD A, Rn | 1 | Occupancy |
| 2 | MOV direct，A | 2 | The second clock cycle does not occupy |
| 3 | ADD A,@Ri | 2 | Occupancy of |
| 4 | ADD A,#data | 2 | Is not occupied |
| 5 | SJMP 1 (jump to instruction 1) | 2 | Is not occupied |
TABLE 1
According to the invention, the number of data output time periods of the data output twice by the peripheral module is set to be larger than the maximum continuous clock period total number, so that the peripheral module is ensured to output while the formed new data can be transmitted in time during the busy period, and the data output last time before exchange is prevented from being eliminated because of the generation of the new data; and the maximum efficiency of data transmission is ensured by setting the number of data output time periods of the data output once by the peripheral module to be less than or equal to the maximum total number of continuous clock periods.
In addition, it should be noted that, in this embodiment, when a clock cycle of instruction execution does not occupy a bus, the MCU controller sends an idle indication to the DMA controller, and the DMA controller is limited by a data output clock cycle of the peripheral module, and does not perform data exchange when receiving the idle indication each time, but first determines whether there is new data output from the peripheral module, and when there is new data in the peripheral module and receives the idle indication, the DMA controller controls the peripheral module and the memory to complete data exchange; because there may be a case that new data of the peripheral module is not generated and the MCU controller sends an idle indication to the DMA controller after the DMA controller completes data exchange, and there is no need to exchange data generated by the peripheral module again if the data has already been exchanged, the DMA controller will determine whether the data in the peripheral module belongs to the new data, and will control the exchange again if the data belongs to the new data.
The invention provides a DMA implementation mode, which can enable a DMA controller to carry out data transmission of a chip memory and a peripheral module while an MCU controller works normally, greatly improves the working efficiency, and can also automatically complete the data transmission of the chip memory and the peripheral module without omission by setting the data output time period of the peripheral module.
Based on the same inventive concept, the embodiment of the present invention further provides a DMA data transmission system, which includes the following modules:
an idle instruction sending module: acquiring an instruction sent by an MCU (microprogrammed control Unit), acquiring the number of clock cycles executed by the instruction and whether each corresponding clock cycle occupies a bus according to the instruction, and calculating the maximum total number of continuous clock cycles continuously occupying the bus in all clock cycles according to an instruction running sequence, wherein at least one clock cycle does not occupy the bus in all clock cycles; when the clock period of instruction execution does not occupy the bus, the MCU controller sends an idle indication to the DMA controller;
a data transmission module: the DMA controller judges whether a peripheral module generates new data or not, and when the peripheral module generates new data and the DMA controller receives an idle instruction, the DMA controller controls the peripheral module and the memory to complete data transmission, wherein the number of data output clock cycles of the peripheral module which generates data once is adjusted according to the maximum total number of continuous clock cycles, so that the data generated by the peripheral module every time can be transmitted.
The adjustment rule that the number of data output clock cycles of the data output by the peripheral module once is adjusted according to the maximum total number of continuous clock cycles comprises the following steps: and setting the number of data output time periods of the data output twice by the peripheral module to be larger than the maximum total number of continuous clock periods.
Based on the same inventive concept, embodiments of the present invention further provide an electronic device, which can refer to the foregoing related descriptions for components, and repeated parts are not described redundantly, including: at least one processor, a memory communicatively coupled to the at least one processor; the at least one processor is configured to read a program in the memory for performing the above-described method.
Based on the same inventive concept, embodiments of the present invention further provide a computer-readable storage medium, which can refer to the related description above for components, and the repetition of which is not repeated, wherein the medium stores instructions that, when executed on a computer, cause the computer to execute the method described above.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (10)
1. A DMA data transmission method is characterized by comprising the following steps:
acquiring an instruction sent by an MCU (microprogrammed control Unit), acquiring the number of clock cycles executed by the instruction and whether each corresponding clock cycle occupies a bus according to the instruction, and calculating the maximum total number of continuous clock cycles continuously occupying the bus in all clock cycles according to an instruction running sequence, wherein at least one clock cycle does not occupy the bus in all clock cycles; when the clock period of instruction execution does not occupy the bus, the MCU controller sends an idle indication to the DMA controller;
the DMA controller judges whether a peripheral module generates new data or not, and when the peripheral module generates new data and the DMA controller receives an idle instruction, the DMA controller controls the peripheral module and the memory to complete data transmission, wherein the number of data output clock cycles of the peripheral module which generates data once is adjusted according to the maximum total number of continuous clock cycles, so that the data generated by the peripheral module every time can be transmitted.
2. The method according to claim 1, wherein the peripheral module comprises one or more of ADC module/SPI module/UART module/I2C module/USB interface/external memory, and the memory comprises SRAM.
3. The DMA data transfer method of claim 1, wherein the adjustment rule for adjusting the number of data output clock cycles of the peripheral module per output of data according to the maximum number of consecutive clock cycles comprises: and setting the number of data output time periods of the data output twice by the peripheral module to be larger than the maximum total number of continuous clock periods.
4. The DMA data transfer method of claim 3, wherein the adjustment rule for adjusting the number of data-out clock cycles of the peripheral module per data-out according to the maximum total number of consecutive clock cycles further comprises: and setting the number of data output time periods of the data output by the peripheral module for outputting the data once to be less than or equal to the maximum total number of continuous clock periods.
5. The DMA data transmission method of claim 4, wherein when the MCU controller is specifically 8051-MCU, the instructions include one or more of immediate number addressing instructions, jump instructions, MOV direct, A, ADD A, Rn, ADD A, @ Ri, the immediate number addressing instructions include ADD A, # data, the jump instructions include SJMP rel; wherein, the clock cycle for executing ADD A, # data is 2 and none of the 2 clock cycles occupies the bus, the clock cycle for executing SJMP rel is 2 and none of the 2 clock cycles occupies the bus, the clock cycle for executing ADD A, Rn is 1 and the clock cycle occupies the bus; executing MOV direct, wherein the clock period of A is 2, the first clock period occupies the bus and the second clock period does not occupy the bus in the 2 clock periods; ADD A is executed with 2 clock cycles of @ Ri and all 2 clock cycles occupy the bus.
6. The DMA data transmission method of claim 5, wherein when the sequentially executed commands are ADD A, Rn, MOV direct, A, ADD A, @ Ri, ADD A, # data, SJMP rel, the maximum number of consecutive clock cycles continuously occupying the bus is 2, and the data-out time period of the peripheral module is set to 2.
7. A DMA data transfer system, comprising the following modules:
an idle instruction sending module: acquiring an instruction sent by an MCU (microprogrammed control Unit), acquiring the number of clock cycles executed by the instruction and whether each corresponding clock cycle occupies a bus according to the instruction, and calculating the maximum total number of continuous clock cycles continuously occupying the bus in all clock cycles according to an instruction running sequence, wherein at least one clock cycle does not occupy the bus in all clock cycles; when the clock period of instruction execution does not occupy the bus, the MCU controller sends an idle indication to the DMA controller;
a data transmission module: the DMA controller judges whether a peripheral module generates new data or not, and when the peripheral module generates new data and the DMA controller receives an idle instruction, the DMA controller controls the peripheral module and the memory to complete data transmission, wherein the number of data output clock cycles of the peripheral module which generates data once is adjusted according to the maximum total number of continuous clock cycles, so that the data generated by the peripheral module every time can be transmitted.
8. The DMA data transfer system of claim 7, wherein the adjustment rule for adjusting the number of data-out clock cycles of the peripheral module per data-out according to the maximum total number of consecutive clock cycles comprises: and setting the number of data output time periods of the data output twice by the peripheral module to be larger than the maximum total number of continuous clock periods.
9. An electronic device, comprising: at least one processor, a memory communicatively coupled to at least one of the processors; at least one of the processors is adapted to read a program in the memory for performing the method of any of claims 1-6.
10. A computer-readable storage medium having stored thereon instructions which, when executed on a computer, cause the computer to perform the method of any one of claims 1-6.
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