CN114641136A - Method for manufacturing copper layer boss of circuit board and circuit board - Google Patents
Method for manufacturing copper layer boss of circuit board and circuit board Download PDFInfo
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- CN114641136A CN114641136A CN202011493467.6A CN202011493467A CN114641136A CN 114641136 A CN114641136 A CN 114641136A CN 202011493467 A CN202011493467 A CN 202011493467A CN 114641136 A CN114641136 A CN 114641136A
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- layer
- copper layer
- copper
- circuit board
- initial position
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 253
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 253
- 239000010949 copper Substances 0.000 title claims abstract description 253
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 230000007704 transition Effects 0.000 claims abstract description 62
- 239000004020 conductor Substances 0.000 claims abstract description 57
- 238000009713 electroplating Methods 0.000 claims abstract description 35
- 230000008719 thickening Effects 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 11
- 238000012546 transfer Methods 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 4
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The application discloses a method for manufacturing a copper layer boss of a circuit board and the circuit board. The transition conductor layer is formed on the surface of the dielectric layer with the copper layer removed, so that the copper layer is conducted into a whole when the subsequent electroplating thickening is carried out; meanwhile, a photosensitive film is covered on the circuit board, so that the high-density pattern can be directionally thickened after being manufactured, a copper layer boss is manufactured, and efficient heat dissipation is performed through the copper layer boss in chip packaging and using.
Description
Technical Field
The application relates to the technical field of printed circuit boards, in particular to a method for manufacturing a copper layer boss of a circuit board and the circuit board.
Background
Electronic products tend to be miniaturized and multifunctional, which requires that PCB products are also continuously miniaturized and multifunctional.
At present, the manufacturing scheme of the copper layer lug boss of the circuit board is as follows: firstly, after the pattern of the circuit board is etched, covering the position of a boss of a copper layer to be formed by using a dry film, and performing micro-etching copper reduction on other positions which are not covered by the dry film; and in the second scheme, the whole pattern of the copper layer of the circuit board is completely exposed, and the copper plating is carried out to increase the height. After the pattern etching in the first scheme is finished, when a dry film is used for covering the position where a copper layer boss needs to be formed, when impedance design is carried out, microetching is carried out to reduce copper after etching, line width or etching factor fluctuation can be caused, impedance stability of a circuit board is influenced, and the side of the copper layer boss forms lateral erosion in different degrees due to microetching; in the second scheme, the whole pattern of the copper layer is completely exposed for copper plating increase, the manufacturing cost is high, and the local position increase cannot be selectively realized.
Disclosure of Invention
The application provides a method for manufacturing a copper layer boss of a circuit board and the circuit board, which are used for solving the problems that directional thickening cannot be realized in the prior art, and the impedance stability of the circuit board is influenced by etching and copper reduction during high-density wiring.
In order to solve the technical problem, the application adopts a technical scheme that: the manufacturing method of the copper layer boss of the circuit board comprises the following steps: electroplating copper on holes at set positions of a dielectric layer of the circuit board; copper layers are covered on two sides of the dielectric layer; carrying out image transfer processing on the circuit board coated with the copper, and removing a copper layer on a part of the dielectric layer to determine the initial position of a copper layer boss; removing the surface of the copper layer from the dielectric layer to form a transition conductor layer; covering a photosensitive film on the circuit board, and removing at least a part of the photosensitive film including the initial position to expose the copper layer on at least one side of the initial position; electroplating and thickening the copper layer on at least one side of the initial position; and removing the residual photosensitive film and the transition conductor layer to form a copper layer boss at the initial position.
The step of covering the circuit board with the photosensitive film to remove at least a part of the photosensitive film including the initial position so as to expose the copper layer on at least one side of the initial position specifically comprises the following steps: covering photosensitive films on the surfaces of the copper layer and the transition conductor layer of the circuit board; exposing a portion of the photosensitive film including at least the initial position; and developing the exposed photosensitive film to remove the exposed photosensitive film so as to retain the copper layer on at least one side of the initial position.
The step of electroplating thickening of the copper layer on at least one side of the initial position comprises the following steps: and conducting the transition conductor layer and the copper layer, and electroplating and thickening the copper layer on at least one side of the initial position in an electroplating mode.
The step of removing the surface of the copper layer from the dielectric layer to form the transition conductor layer comprises the following steps: and carrying out a shadow or black hole process on the surface of the dielectric layer with the copper layer removed to form a transition conductor layer, wherein the transition conductor layer is a carbonized layer.
The step of removing the surface of the copper layer from the dielectric layer to form the transition conductor layer comprises the following steps: and carrying out a copper deposition process on the surface of the dielectric layer with the copper layer removed to form a transition conductor layer, wherein the transition conductor layer is a transition copper layer.
The step of removing the remaining photosensitive film and the transition conductor layer specifically includes: exposing the rest photosensitive film; developing the exposed photosensitive film to remove the residual photosensitive film; and carrying out micro-etching or flash etching on the circuit board with the rest photosensitive film removed to remove the transition conductor layer.
The photosensitive film comprises a photosensitive anti-plating film and a photosensitive anti-corrosion film.
The method comprises the following steps of carrying out image transfer processing on a circuit board coated with copper, removing a copper layer on a part of dielectric layer to determine the initial position of a copper layer boss, and comprises the following steps: pasting a dry film on the surface of the circuit board coated with the copper; exposing and developing the dry film on the surface of the circuit board to expose a copper layer on a part of the dielectric layer; and etching the copper layer on the exposed part of the dielectric layer, and removing the copper layer on the part of the dielectric layer to determine the initial position of the copper layer boss.
The method comprises the following steps of electroplating copper on holes at set positions of a dielectric layer of a circuit board: laser drilling is carried out on a dielectric layer of a circuit board to form a hole with a set position
In order to solve the above technical problem, another technical solution adopted by the present application is: the circuit board comprises a hole and a copper layer boss, wherein the copper layer boss penetrates through the hole, and the copper layer boss is manufactured by the method for manufacturing the copper layer boss of the circuit board.
The beneficial effect of this application is: different from the situation of the prior art, the application provides a method for manufacturing a copper layer boss of a circuit board and the circuit board. The transition conductor layer is formed on the surface of the dielectric layer with the copper layer removed, so that the copper layer is conducted into a whole when the subsequent electroplating thickening is carried out; meanwhile, a photosensitive film is covered on the circuit board, so that the high-density pattern can be directionally thickened after being manufactured, a copper layer boss is manufactured, and efficient heat dissipation is performed through the copper layer boss in chip packaging and using.
Drawings
FIG. 1 is a schematic flow chart illustrating a first embodiment of a method for fabricating a copper layer bump of a circuit board according to the present invention;
FIG. 2 is a schematic flow chart diagram illustrating an embodiment of specific steps of step S102 in FIG. 1;
FIG. 3 is a schematic flow chart diagram illustrating an embodiment of specific steps of step S104 in FIG. 1;
FIG. 4 is a schematic flow chart diagram illustrating an embodiment of specific steps of step S106 in FIG. 1;
FIG. 5 is a schematic flow chart diagram illustrating a second embodiment of a method for fabricating a copper layer bump of a circuit board according to the present application;
FIG. 6 is a schematic flow chart illustrating a third embodiment of a method for fabricating a copper layer bump of a circuit board according to the present application;
fig. 7 is a schematic structural diagram of an embodiment of a circuit board according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a copper layer bump of a circuit board according to a first embodiment of the present invention.
Step S101: and electroplating copper on the holes at the set positions of the dielectric layer of the circuit board.
In this embodiment, the circuit board includes a dielectric layer, and both sides of the dielectric layer are covered with copper layers. The dielectric layer plays an insulating role in the circuit board, and the material of the dielectric layer comprises epoxy resin, polyimide, BT, ABF, ceramic and the like. A plurality of holes are formed in a dielectric layer of the circuit board, each hole comprises a through hole and a micro blind hole, and the through holes and the micro blind holes are formed by drilling holes in the dielectric layer through laser.
In this embodiment, the holes at the set positions of the dielectric layer of the circuit board are plated with copper, the holes at the set positions are metalized, copper is fully filled in the holes, and the height of the copper coated in the holes is the same as the height of the copper layers at two sides of the dielectric layer.
Step S102: and carrying out image transfer treatment on the circuit board coated with the copper, and removing a copper layer on part of the dielectric layer to determine the initial position of a copper layer boss.
In this embodiment, the circuit board coated with copper is subjected to image transfer processing, and the copper layers on both sides of the dielectric layer are etched by the image transfer processing, so as to remove a part of the copper layer on the dielectric layer, and further determine the initial position of the copper layer boss.
Referring to fig. 2, fig. 2 is a schematic flowchart illustrating an embodiment of the specific step of step S102 in fig. 1.
Step S201: and pasting a dry film on the surface of the circuit board coated with the copper.
In this embodiment, after copper is plated through holes at a set position of a dielectric layer of a circuit board, two side surfaces of the dielectric layer are covered with copper layers, and a dry film is laminated on the surfaces of the copper layers at two sides of the dielectric layer through a laminating process.
Step S202: and exposing and developing the dry film on the surface of the circuit board to expose a copper layer on part of the dielectric layer.
In this embodiment, the surface of the copper layer of the circuit board is covered by the dry film, the dry film is exposed and developed according to a preset requirement, and the image on the dry film is transferred to the copper layer, so that part of the copper layer on the dielectric layer is exposed, and the copper layer on the exposed part of the dielectric layer is etched and removed in a subsequent step.
Step S203: and etching the copper layer on the exposed part of the dielectric layer, and removing the copper layer on the part of the dielectric layer to determine the initial position of the copper layer boss.
In this embodiment, after the predetermined image on the dry film on the surface of the circuit board is transferred to the copper layer, the copper layer on the exposed dielectric layer is etched, so as to remove a portion of the copper layer on the dielectric layer, and further determine the initial position of the copper layer boss, where the copper layer at the initial position is still covered by the unexposed dry film. After the initial position of the copper layer boss is determined, the residual dry films on the surface of the circuit board are continuously exposed and developed, all the dry films on the surface of the circuit board are removed, and the copper layer of the preset pattern on the circuit board is exposed.
Step S103: and removing the surface of the copper layer from the dielectric layer to form a transition conductor layer.
In this embodiment, after the copper layer on the surface of the dielectric layer of the circuit board is removed, the copper layer remained on the surface of the dielectric layer is not completely conducted, and at this time, electroplating is performed, and the copper layer cannot be electroplated and deposited on the surface of the copper layer at the non-conducted portion to be thickened. And forming a transition conductor layer on the surface of the dielectric layer with the copper layer removed, and conducting the copper layer on the surface of the circuit board into a whole through the transition conductor layer, so that the initial position of the copper layer can be electrified to carry out electroplating copper deposition.
Step S104: covering the circuit board with a photosensitive film, and removing at least a part of the photosensitive film including the initial position to expose the copper layer on at least one side of the initial position.
In this embodiment, both sides of the circuit board are covered with photosensitive films, and the photosensitive films are developed by exposure to remove at least a portion of the photosensitive films including the initial position, thereby exposing the copper layer on at least one side of the initial position. The photosensitive film comprises a photosensitive anti-plating film and a photosensitive anti-corrosion film.
Referring to fig. 3, fig. 3 is a flowchart illustrating an embodiment of the specific step of step S104 in fig. 1.
Step S301: and covering the surfaces of the copper layer and the transition conductor layer of the circuit board with photosensitive films.
In this embodiment, the surfaces of the copper layer and the transition conductor layer of the circuit board are covered with the photosensitive film, and the photosensitive film can be pressed on the surfaces of the copper layer and the transition conductor layer of the circuit board through a pressing process. Wherein the photosensitive film comprises a photosensitive plating resist film and a photosensitive resist film. The photosensitive film can generate a polymerization reaction after being irradiated by a specific light source to form a stable substance to be attached to the surface of the circuit board.
Step S302: the photosensitive film including at least the initial position is exposed.
In this embodiment, at least a portion of the photosensitive film including the initial position is subjected to irradiation exposure by a specific light source, and the pattern of at least a portion of the photosensitive film including the initial position is transferred onto the copper layer on at least one side of the circuit board by the exposure.
Step S303: and developing the exposed photosensitive film to remove the exposed photosensitive film so as to retain the copper layer on at least one side of the initial position.
In this embodiment, the exposed photosensitive film is developed, and the photosensitive film that has not undergone polymerization is removed by the chemical solution, so that the copper layer on at least one side of the initial position is retained, and the copper layer and the transition conductor layer outside the initial position are still covered by the photosensitive film. In the subsequent electroplating process, due to the existence of the photosensitive film, copper is only deposited at the initial position, so that the copper layer boss with the preset height can be directionally thickened at the initial position.
Step S105: and electroplating to thicken the copper layer on at least one side of the initial position.
In this embodiment, the copper layer on at least one side of the initial position is subjected to copper deposition by an electroplating process, so that the copper layer on the initial position is raised to a predetermined height. Specifically, the transition conductor layer is conducted with the copper layer, so that the copper layer is conducted to be a finished conductor, and electroplating copper deposition can be carried out on the surfaces of the copper layer at all initial positions during electroplating. And electroplating the circuit board to increase the thickness of the copper layer on at least one side of the initial position, and optionally, thickening the copper layer until the photosensitive resist coating is consistent in height.
Step S106: and removing the residual photosensitive film and the transition conductor layer to form a copper layer boss at the initial position.
In this embodiment, after the copper layer on at least one side of the initial position is thickened to a predetermined thickness, the remaining photosensitive film and the transition conductor layer are removed. Specifically, the residual photosensitive film of the thickened circuit board is exposed and developed, and the residual photosensitive anti-plating film is removed through liquid medicine; and removing the transition conductor layer by micro-etching or flash etching so as to form a copper layer boss at the initial position. The copper layer boss can be arranged at a designated position according to the requirements of customers, and the thickness of the copper layer boss can also be set according to the requirements of customers.
Referring further to fig. 4, fig. 4 is a schematic flowchart illustrating an embodiment of step S106 in fig. 1.
Step S401: the remaining photosensitive film is exposed.
In the present embodiment, the remaining photosensitive films on both sides of the circuit board are irradiated by a specific light source to expose the remaining photosensitive films.
Step S402: the exposed photosensitive film is developed to remove the remaining photosensitive film.
In this embodiment, the exposed remaining photosensitive film is developed, and the remaining photosensitive film is removed by using a chemical solution to expose all the copper layers and the transition conductor layer.
Step S403: and carrying out micro-etching or flash etching on the circuit board with the rest photosensitive film removed to remove the transition conductor layer.
In this embodiment, the exposed transition conductor layer is subjected to microetching or flash etching, and the transition conductor layer on the surface of the dielectric layer is removed by an etching solution to re-partition the copper layer into copper layers with predetermined patterns. When the transition conductor layer is a carbonized layer, the carbonized layer is rapidly removed through micro-etching or flash etching; when the transition conductor layer is a transition copper layer, the copper layer is quickly removed through microetching or flash etching, wherein the copper loss amount of the copper layer is less than or equal to 5 micrometers, so that the transition copper layer is completely etched, and no transition copper layer is reserved on the dielectric layer.
Different from the prior art, the application provides a method for manufacturing a copper layer boss of a circuit board and the circuit board. The transition conductor layer is formed on the surface of the dielectric layer with the copper layer removed, so that the copper layer is conducted into a whole when the subsequent electroplating thickening is carried out; meanwhile, a photosensitive film is covered on the circuit board, so that the high-density pattern can be directionally thickened after being manufactured, a copper layer boss is manufactured, and efficient heat dissipation is performed through the copper layer boss in chip packaging and using.
Referring to fig. 5, fig. 5 is a schematic flow chart illustrating a method for manufacturing a copper layer bump of a circuit board according to a second embodiment of the present disclosure.
Step S501: and carrying out laser drilling on the dielectric layer of the circuit board to form holes at set positions.
In this embodiment, the circuit board includes a dielectric layer and copper layers laminated on both sides of the dielectric layer, and a high power density laser beam is irradiated on a set position of the circuit board, and holes are drilled on the set position. Wherein, the hole can be a through hole or a micro blind hole.
Step S502: and electroplating copper on the holes at the set positions of the dielectric layer of the circuit board.
Step S503: and carrying out image transfer treatment on the circuit board coated with the copper, and removing a copper layer on part of the dielectric layer to determine the initial position of a copper layer boss.
Steps S502 and S503 are the same as steps S101 and S102 described above, and are not described again here.
Step S504: and carrying out a shadow or black hole process on the surface of the dielectric layer with the copper layer removed to form a transition conductor layer.
In this embodiment, after the copper layer on the surface of the dielectric layer of the circuit board is removed, the copper layer remained on the surface of the dielectric layer is not completely conducted, and at this time, electroplating is performed, and the copper layer cannot be electroplated and deposited on the surface of the copper layer at the non-conducted portion to be thickened. And forming a transition conductor layer on the surface of the dielectric layer with the copper layer removed, and conducting the copper layer on the surface of the circuit board into a whole through the transition conductor layer, so that the initial position of the copper layer can be electrified to carry out electroplating copper deposition.
Specifically, a shadow or black hole process is carried out on the circuit board, and a carbide layer is covered on the surface of a dielectric layer which is not covered by a copper layer on the circuit board to form a carbide layer. The carbonized layer is arranged on the surface of the dielectric layer and is mutually connected with the copper layer, so that the copper layer is connected into a complete conductor, and a layer of copper can be deposited on the surface of the copper layer at the initial position in the subsequent electroplating copper deposition process.
Step S505: covering the circuit board with photosensitive film, and removing part of the photosensitive film including at least the initial position to expose the copper layer on at least one side of the initial position.
Step S506: and electroplating to thicken the copper layer on at least one side of the initial position.
Step S507: and removing the residual photosensitive film and the transition conductor layer to form a copper layer boss at the initial position.
Steps S505, S506, and S507 are the same as steps S104, S105, and S106 described above, and are not described herein again.
Different from the prior art, the application provides a method for manufacturing a copper layer boss of a circuit board and the circuit board. The transition conductor layer is formed on the surface of the dielectric layer with the copper layer removed, so that the copper layer is conducted into a whole when the subsequent electroplating thickening is carried out; meanwhile, a photosensitive film is covered on the circuit board, so that the high-density pattern can be directionally thickened after being manufactured, a copper layer boss is manufactured, and efficient heat dissipation is performed through the copper layer boss in chip packaging and using.
Further, referring to fig. 6, fig. 6 is a schematic flow chart illustrating a third embodiment of a method for manufacturing a copper layer bump of a circuit board according to the present application. The method for manufacturing the copper layer boss of the circuit board in the embodiment also includes the steps S101 to S102 and the steps S104 to S106 as described above. The manufacturing method of the circuit board in the embodiment is different from the manufacturing method of the copper layer boss of the circuit board in the foregoing, in that: after step S102, the method for manufacturing a copper layer boss of a circuit board in the embodiment further includes:
step S603: and carrying out a copper deposition process on the surface of the dielectric layer with the copper layer removed to form a transition conductor layer.
In this embodiment, after the copper layer on the surface of the dielectric layer of the circuit board is removed, the copper layer remained on the surface of the dielectric layer is not completely conducted, and at this time, electroplating is performed, and the copper layer cannot be electroplated and deposited on the surface of the copper layer at the non-conducted portion to be thickened. And forming a transition conductor layer on the surface of the dielectric layer with the copper layer removed, and conducting the copper layer on the surface of the circuit board into a whole through the transition conductor layer, so that the initial position of the copper layer can be electrified to carry out electroplating copper deposition.
Specifically, the circuit board is subjected to an electroplating copper deposition process or a chemical copper deposition process, and a copper layer is covered on the surface of a dielectric layer which is not covered by the copper layer on the circuit board to form a transition copper layer. The transition copper layer is arranged on the surface of the dielectric layer and is mutually connected with the copper layer, so that the copper layer is connected into a complete conductor, and a layer of copper can be deposited on the surface of the copper layer at the initial position in the subsequent electroplating copper deposition process. Wherein the transition copper layer has a thickness in the range of 0.2 microns to 2.0 microns.
Different from the prior art, the application provides a method for manufacturing a copper layer boss of a circuit board and the circuit board. The transition conductor layer is formed on the surface of the dielectric layer with the copper layer removed, so that the copper layer is conducted into a whole when the subsequent electroplating thickening is carried out; meanwhile, the circuit board is covered with a photosensitive film, so that the manufactured high-density pattern can be directionally thickened, a copper layer boss is manufactured, and efficient heat dissipation is performed through the copper layer boss in chip packaging and using.
Further, please refer to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of the circuit board of the present application. The application also provides a circuit board 10, the circuit board 10 comprises a hole 101 and a copper layer boss 102, the copper layer boss 102 penetrates through the hole 101, and the copper layer boss 102 is made by the method for making the copper layer boss of the circuit board.
In summary, the application provides a method for manufacturing a copper layer boss of a circuit board and the circuit board. The transition conductor layer is formed on the surface of the dielectric layer with the copper layer removed, so that the copper layer is conducted into a whole when the subsequent electroplating thickening is carried out; meanwhile, a photosensitive film is covered on the circuit board, so that the high-density pattern can be directionally thickened after being manufactured, a copper layer boss is manufactured, and efficient heat dissipation is performed through the copper layer boss in chip packaging and using.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method for manufacturing a copper layer boss of a circuit board is characterized by comprising the following steps:
electroplating copper on holes at set positions of the dielectric layer of the circuit board; copper layers are covered on two sides of the dielectric layer;
carrying out image transfer processing on the circuit board coated with the copper, and removing part of the copper layer on the dielectric layer to determine the initial position of a copper layer boss;
removing the surface of the copper layer from the dielectric layer to form a transition conductor layer;
covering a photosensitive film on the circuit board, and removing at least a part of the photosensitive film including the initial position to expose the copper layer on at least one side of the initial position;
electroplating thickening of the copper layer on at least one side of the initial position;
and removing the residual photosensitive film and the transition conductor layer to form the copper layer boss at the initial position.
2. The method of claim 1, wherein the step of covering the circuit board with a photosensitive film and removing at least a portion of the photosensitive film including the initial position to expose the copper layer on at least one side of the initial position comprises:
covering the surfaces of the copper layer and the transition conductor layer of the circuit board with the photosensitive film;
exposing a portion of the photosensitive film including at least the initial position;
and developing the exposed photosensitive film to remove the exposed photosensitive film so as to retain the copper layer on at least one side of the initial position.
3. The method of claim 1, wherein the step of thickening the copper layer on at least one side of the initial position by electroplating comprises:
and conducting the transition conductor layer and the copper layer, and electroplating the copper layer on at least one side of the initial position in an electroplating mode to thicken.
4. The method for manufacturing the copper layer boss according to any one of claims 1 to 3, wherein the step of removing the surface of the copper layer from the dielectric layer to form the transition conductor layer comprises:
and carrying out a shadow or black hole process on the surface of the dielectric layer with the copper layer removed to form the transition conductor layer, wherein the transition conductor layer is a carbonized layer.
5. The method for manufacturing the copper layer boss according to any one of claims 1 to 3, wherein the step of removing the surface of the copper layer from the dielectric layer to form the transition conductor layer comprises the steps of:
and carrying out a copper deposition process on the surface of the dielectric layer with the copper layer removed to form a transition conductor layer, wherein the transition conductor layer is a transition copper layer.
6. The method of claim 1, wherein the step of removing the remaining photosensitive film and the transition conductor layer comprises:
exposing the rest of the photosensitive film;
developing the exposed photosensitive film to remove the residual photosensitive film;
and carrying out micro-etching or flash etching on the circuit board with the rest photosensitive film removed to remove the transition conductor layer.
7. The method of claim 1, wherein the photosensitive film comprises a photosensitive resist film and a photosensitive resist film.
8. The method for manufacturing the copper layer boss according to claim 1, wherein the step of performing image transfer processing on the circuit board coated with copper to remove a part of the copper layer on the dielectric layer so as to determine the initial position of the copper layer boss comprises the steps of:
pasting a dry film on the surface of the circuit board coated with the copper;
exposing and developing the dry film on the surface of the circuit board to expose the copper layer on the partial dielectric layer;
and etching the copper layer on the exposed part of the dielectric layer, and removing the copper layer on the part of the dielectric layer to determine the initial position of the copper layer boss.
9. The method for manufacturing a copper layer boss according to claim 1, wherein the step of plating copper on the hole at the set position of the dielectric layer of the circuit board comprises:
and carrying out laser drilling on the dielectric layer of the circuit board to form the hole at the set position.
10. A circuit board comprising a hole and a copper layer projection, wherein the copper layer projection penetrates through the hole, and the copper layer projection is manufactured by the method of manufacturing the copper layer projection of the circuit board according to any one of claims 1 to 9.
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| CN202011493467.6A CN114641136B (en) | 2020-12-16 | 2020-12-16 | Manufacturing method of copper layer boss of circuit board and circuit board |
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Also Published As
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| CN114641136B (en) | 2024-05-14 |
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