CN114627941A

CN114627941A - Memory management method, memory storage device and memory control circuit unit

Info

Publication number: CN114627941A
Application number: CN202210268410.9A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2022-03-18
Filing date: 2022-03-18
Publication date: 2022-06-14

Abstract

The invention provides a memory management method for a rewritable nonvolatile memory module, a memory storage device and a memory control circuit unit. The rewritable nonvolatile memory module comprises a plurality of crystal grains, each crystal grain comprises a plurality of planes, each plane comprises a plurality of entity erasing units, and the number of the planes included in the rewritable nonvolatile memory module is combined into a first number. The method comprises the following steps: combining the plurality of entity erasing units into a plurality of management units. Each management unit comprises a plurality of entity erasing units, each entity erasing unit belongs to different planes, and each management unit has a second number of entity erasing units, wherein the second number is smaller than the first number.

Description

Memory management method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.

Background

In general, a memory storage device may operate a plurality of blocks belonging to different operating units (e.g., planes, channels, or dies) into a block group. The memory storage device reserves spare blocks in advance for replacement when Bad Block (Bad Block) management detects and marks a defective Block in the Block group. This prevents data from being written again into the defective block. However, when the block for replacement belongs to another operation unit, the data access speed is severely slowed down. If the data in the block group is accessed by skipping the faulty block without replacing the block when the faulty block is detected, additional processing is required to move the data due to the different number of blocks included in each block group. Such bad block management methods will cause the memory storage device to run at erratic speeds.

Disclosure of Invention

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the speed stability of the memory storage device.

An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of crystal grains, each crystal grain comprises a plurality of planes, each plane comprises a plurality of entity erasing units, and the number of the planes included in the rewritable nonvolatile memory module is a first number in total. The memory management method comprises the following steps: and combining the plurality of entity erasing units into a plurality of management units. Each of the plurality of physically erased cells included in each of the plurality of management units belongs to a different one of the plurality of planes, and each of the plurality of management units has a second number of the plurality of physically erased cells. The second number is less than the first number.

In an exemplary embodiment of the invention, the management unit includes a first management unit. The method further comprises the following steps: in response to detecting that the first management unit includes a first bad-entity-erased cell, extracting a first replacement-entity-erased cell to replace the first bad-entity-erased cell. The first replacement solid erased unit and the first bad solid erased unit belong to the same plane.

In an exemplary embodiment of the invention, the method further includes: and recording the replacement information of the first bad entity erasure unit and the first replacement entity erasure unit in a first management table.

In an exemplary embodiment of the invention, the method further includes: and accessing the first replacement entity erasing unit when accessing the first management unit according to the first management table.

In an exemplary embodiment of the invention, the first management table records replacement information of all bad erase units and replacement erase units in the plurality of erase units.

In an exemplary embodiment of the invention, each of the management units has the same number of the plurality of physically erased units.

In an exemplary embodiment of the invention, the step of combining the plurality of physical erase units into the plurality of management units comprises: and combining the entity erasing units into a plurality of management units according to a second management table, wherein the second management table records all bad entity erasing units in the rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The rewritable nonvolatile memory module comprises a plurality of crystal grains, each crystal grain comprises a plurality of planes, each plane comprises a plurality of entity erasing units, and the number of the planes included in the rewritable nonvolatile memory module is a first number in total. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for combining the plurality of entity erasing units into a plurality of management units. Each of the plurality of physically erased cells included in each of the plurality of management units belongs to a different one of the plurality of planes, and each of the plurality of management units has a second number of the plurality of physically erased cells. The second number is less than the first number.

In an exemplary embodiment of the invention, the management unit includes a first management unit. And in response to detecting that the first management unit includes a first bad-entity-erased cell, the memory control circuit unit is further configured to extract a first replacement-entity-erased cell to replace the first bad-entity-erased cell. The first replacement solid erased unit and the first bad solid erased unit belong to the same plane.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to record replacement information of the first bad erase unit and the first replacement erase unit in a first management table.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to access the first replacement physical erase unit when accessing the first management unit according to the first management table.

In an exemplary embodiment of the invention, the operation of combining the plurality of physical erase units into the plurality of management units comprises: and combining the entity erasing units into a plurality of management units according to a second management table, wherein the second management table records all bad entity erasing units in the rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of crystal grains, each crystal grain comprises a plurality of planes, each plane comprises a plurality of entity erasing units, and the number of the planes included in the rewritable nonvolatile memory module is a first number in total. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to couple to a host system. The memory interface is used for being coupled to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used for combining the plurality of entity erasing units into a plurality of management units. Each of the plurality of physically erased cells included in each of the plurality of management units belongs to a different one of the plurality of planes, and each of the plurality of management units has a second number of the plurality of physically erased cells. The second number is less than the first number.

In an exemplary embodiment of the invention, the management unit includes a first management unit. And in response to detecting that the first management unit includes a first bad-entity-erased cell, the memory management circuit is further configured to extract a first replacement-entity-erased cell to replace the first bad-entity-erased cell. The first replacement physically-erased cell and the first bad physically-erased cell belong to the same plane.

In an exemplary embodiment of the invention, the memory management circuit is further configured to record replacement information of the first bad erase unit and the first replacement erase unit in a first management table.

In an exemplary embodiment of the invention, the memory management circuit is further configured to access the first replacement physical erase unit when accessing the first management unit according to the first management table.

Based on the above, the memory control circuit unit forms the management unit with the number of the entity erasing units smaller than the total number of the planes of the rewritable nonvolatile memory module to operate. The management units comprise the entity erasing units which belong to different planes respectively, so that the entity erasing units contained in each management unit do not correspond to all the planes. In addition, the memory control circuit unit may replace the bad block in the management unit with a physically erased unit belonging to the same plane. Therefore, the speed stability and the operation flexibility of the memory storage device can be improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating a memory control circuit unit coupled to a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 8A is a diagram illustrating a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 8B is a diagram illustrating a rewritable nonvolatile memory module according to an example embodiment of the present invention;

FIG. 9 is a flowchart illustrating a memory management method according to an example embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is coupled to the I/O devices 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 may be coupled to the memory storage device 10 via a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage 204 can be a memory Storage based on various wireless Communication technologies, such as Near Field Communication (NFC) memory Storage, wireless facsimile (WiFi) memory Storage, Bluetooth (Bluetooth) memory Storage, or Bluetooth low energy (low) memory Storage (e.g., iBeacon). The main board 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33 or an embedded storage device 34 used therein. The embedded memory device 34 includes embedded Multi Media Card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) 342, which couple the memory module directly to the embedded memory device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used for coupling the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High-Speed Peripheral Component connection interface (PCI) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-I) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, eMMC interface standard, Universal Flash (Flash) interface standard, CP interface standard, CF interface standard, Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND-type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, the memory cells of the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or more or less physical fans may be included in the data bit region, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module) by using a program code. Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or scripts and are used to instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is coupled to the memory management circuit 502. The memory management circuitry 502 may communicate with the host system 11 via a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include script or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.

The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is coupled to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable nonvolatile memory module 406 of fig. 4 is also referred to as a flash (flash) memory module, the memory control circuit unit 404 is also referred to as a flash controller for controlling the flash memory module, and/or the memory management circuit 502 of fig. 5 is also referred to as a flash management circuit.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0) - (610D) of the rewritable nonvolatile memory module 406 into a memory area 601, an idle (spare) area 602, a replacement area 603, and a system area 604. In the present exemplary embodiment, each physical cell may refer to one or more physical erase cells.

It should be understood that the operation of the memory storage device described herein using the terms "fetch," "move," "swap," "replace," "rotate," "partition," etc. to operate the physical units of the rewritable nonvolatile memory module 406 is a logical concept. That is, the physical location of the physical unit of the rewritable nonvolatile memory module 406 is not changed, but the physical unit of the rewritable nonvolatile memory module 406 is logically operated.

The entity units 610(0) to 610(a) in the storage area 601 store data. For example, entity units 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 are not yet used to store data (e.g., valid data). When data is to be stored, the memory management circuit 502 selects one entity unit from the entity units 610(a +1) to 610(B) in the idle area 602, and stores the data from the host system 11 or at least one entity unit in the storage area 601 into the selected entity unit. At the same time, the selected physical unit is associated to the storage area 601. In addition, after erasing a physical unit in the storage area 601, the erased physical unit is re-associated with the idle area 602.

The physical units 610(B +1) to 610(C) in the replacement area 603 are used to replace the damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit (also called a bad physical erase unit). In addition, if there are no physical erase units available in the replacement area 603, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written. The physical units 610(C +1) -610 (D) in the system area 604 are used to store system data, such as a logical-to-physical mapping table, a bad block management table, a device model, or other types of management data.

Memory management circuitry 502 configures logical units 612(0) - (612 (E) to map physical units 610(0) - (610 (A)) in memory area 601. Each of logic cells 612(0) -612 (E) may be mapped to one or more physical cells. The memory management circuit 502 records the mapping relationship between the logical units and the physical units (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. The logical-to-physical mapping table may be stored in the physical units 610(C +1) -610 (D) of the system area 604. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations to the memory storage device 10 according to the logical-to-physical mapping table.

In an example embodiment, the rewritable nonvolatile memory module 406 may include a plurality of dies (die) and have a plurality of planes (planes), each plane belonging to one die. The rewritable non-volatile memory module 406 can include a plurality of planes that sum to a first number. In the present exemplary embodiment, the number of planes may be greater than the number of dies. That is, two or more planes may belong to one grain. Each plane may include a plurality of physically erased cells and a plurality of physically programmed cells, and the plurality of physically programmed cells may be combined into one physically erased cell.

FIG. 7 is a diagram illustrating a memory control circuit unit coupled to a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 7, the rewritable nonvolatile memory module 406 includes two dies D0 and D1, and each die includes two planes P0 and P1. In the present exemplary embodiment, the rewritable nonvolatile memory module 406 includes four planes, and thus has a total number of planes of 4 (i.e., the first number is 4). Each of the planes P0 and P1 includes a plurality of physically erased cells, each of which is formed by a combination of a plurality of physically programmed cells. However, in different embodiments, the rewritable non-volatile memory module 406 may include more or less dies, and each die may include more or less planes, and the invention is not limited thereto.

In the present exemplary embodiment, die D0 and die D1 are coupled to memory control circuit unit 404 via chip enable pins, respectively. Memory control circuit unit 404 may send enable signals to the chip enable pins of die D0 and die D1 to enable die D0 and die D1, respectively. When the die is enabled, the memory control circuitry 404 may access data via a channel 408 (e.g., a data bus). The channels 408 may include one or more channels. That is, the physical program units included in plane P0 and plane P1 of die D0 and plane P0 and plane P1 of die D1 are accessed via channel 408. In an example embodiment, data stored in planes P0 and P1 may be accessed via channel 408 using single plane access operations or multiple plane access operations, wherein data stored in planes P0 and P1 may be accessed in parallel using multiple plane access operations.

In this exemplary embodiment, the memory control circuit unit 404 may also enable a plurality of dies simultaneously by one enable signal, or enable a plurality of dies respectively by a plurality of enable signals. Also, data stored in different dies may be accessed via different channels. Taking fig. 7 as an example, data stored in plane P0 and plane P1 of die D0 can be accessed via one channel, while data stored in plane P0 and plane P1 of die D1 can be accessed via another channel.

In an exemplary embodiment, the memory control circuit unit 404 combines a plurality of physical erase units into a management unit, and the rewritable nonvolatile memory module 406 includes a plurality of management units. Each management unit comprises a plurality of physically erased cells, each of which belongs to a different plane, and each management unit has a fixed number (also called a second number) of the plurality of physically erased cells. In the present exemplary embodiment, the second number is smaller than the sum of the number of planes (i.e., the first number) included in the rewritable nonvolatile memory module 406. In an exemplary embodiment, each of the plurality of management units has the same number of physically erased cells.

In an example embodiment, when the memory control circuit unit 404 combines the plurality of physical erase units into the management unit, the plurality of physical erase units can be combined into one management unit according to a bad Block record management table (also referred to as a second management table, e.g., dbt (defect Block table) for recording a bad Block). The bad block record management table records all bad erase units in the rewritable nonvolatile memory module 406. Specifically, bad erase units may occur in the rewritable non-volatile memory module 406 due to a bad process. The memory control circuit unit 404 can eliminate the bad erase units according to the bad block record management table and combine the normal erase units into management units when the organizer unit is initialized.

FIG. 8A is a diagram illustrating a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 8A, the rewritable nonvolatile memory module 406 includes four planes (plane P0 and plane P1 of die D0, and plane P0 and plane P1 of die D1). The plane P0 of the die D0 includes the physical erase units 810(0) -810 (M), the plane P1 of the die D0 includes the physical erase units 820(0) -820 (M), the plane P0 of the die D1 includes the physical erase units 830(0) -830 (M), and the plane P1 of the die D1 includes the physical erase units 840(0) -840 (M). For convenience of explanation, it is assumed that the rewritable nonvolatile memory module 406 includes the management units 81(0) to 81(3), but the number of the management units is not limited in the present invention. Each management unit comprises three physical erasing units. As shown in FIG. 8A, each management unit includes a number of physically erased cells that is less than the sum of the number of planes included in the rewritable non-volatile memory module 406.

In an exemplary embodiment, when the physically erased cells normally used by the rewritable nonvolatile memory module 406 are damaged, the physically erased block is regarded as a bad physically erased cell. The damage may occur during a bad process or may occur after multiple erasures, which may cause the data read from the physically erased cells to contain too many errors to be corrected. When a defect occurs, the memory control circuit unit 404 can extract the physical erase unit from the replacement area 603 to replace the defective physical erase unit in the storage area 601.

FIG. 8B is a diagram illustrating a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 8B, it is assumed that the physical erase unit 840(0) (the bad physical erase unit in the example embodiment) is damaged. In response to detecting that the management unit 81(1) (also referred to as the first management unit) includes the physical erase unit 840(0) (also referred to as the first bad physical erase unit), the memory control circuit unit 404 extracts the replacement physical erase unit (also referred to as the first replacement physical erase unit) to replace the physical erase unit 840 (0). In the exemplary embodiment, the replacement physically erased cells and the bad physically erased cells belong to the same plane. As shown in FIG. 8B, the memory control circuit unit 404 extracts the physically erased cells 840(P) belonging to the same plane as the physically erased cells 840(0) to replace the bad physically erased cells 840 (0).

In an exemplary embodiment, the memory control circuit Unit 404 records the replacement information of the bad erase Unit and the replacement erase Unit in a bad block replacement management table (also referred to as a first management table, e.g., a run (replace Unit table) for managing the replacement of the bad block). The bad block replacement management table records replacement information of all bad erase units and replacement erase units. Taking fig. 8B as an example, the memory control circuit unit 404 records the replacement information of the bad-entity-erasure unit 840(0) and the replacement-entity-erasure unit 840(P) in the bad-block replacement management table. When the memory control circuit unit 404 accesses the management unit 81(1), if the accessed address is the original address of the physical erase unit 840(0), the memory control circuit unit 404 will change to access the physical erase unit 840(P) according to the bad block replacement management table. That is, if the memory control circuit unit 404 accesses the management unit 81(1), the memory control circuit unit 404 accesses the physical erasing unit 840(P) according to the first management table when accessing the management unit 81 (1).

FIG. 9 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention. Referring to FIG. 9, in step S902, a plurality of entity erasing units are combined into a plurality of management units. Each management unit comprises a plurality of entity erasing units, each entity erasing unit belongs to a different plane, and each management unit has a second number of entity erasing units.

In summary, the exemplary embodiments of the invention provide a management unit that is composed of the physical erase units with a number smaller than the total number of planes of the rewritable nonvolatile memory module, and the physical erase units belong to different planes respectively. Therefore, each management unit comprises a physical erasing unit which does not correspond to all planes. Therefore, the probability of the depletion of normal solid erasing units of the same plane when the number of the bad blocks is too large can be reduced, the tolerance of each plane to the bad blocks is improved, and the probability that the solid erasing units of another operation unit are required to replace the bad blocks when the solid erasing units of the same operation unit are depleted is reduced. In addition, by replacing the bad block, the number of the entity erasing units included in each management unit can be kept the same without performing additional processing in the data moving operation. Therefore, the speed stability and the operation flexibility of the memory storage device can be effectively improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of dies, each of the plurality of dies comprises a plurality of planes, each of the plurality of planes comprises a plurality of physically erased units, and the number of the plurality of planes included in the rewritable nonvolatile memory module is a first number, the memory management method comprising:

combining the plurality of physical erasure units into a plurality of management units,

wherein each of the plurality of physically erased cells included in each of the plurality of management units belongs to a different one of the plurality of planes, and each of the plurality of management units has a second number of the plurality of physically erased cells,

wherein the second number is smaller than the first number.

2. The memory management method of claim 1, wherein the plurality of management units comprises a first management unit, the method further comprising:

in response to detecting that the first management unit includes a first bad-entity-erased cell, extracting a first replacement-entity-erased cell to replace the first bad-entity-erased cell,

wherein the first replacement physically-erased cell and the first bad physically-erased cell belong to the same plane.

3. The memory management method of claim 2, further comprising:

and recording the replacement information of the first bad entity erasure unit and the first replacement entity erasure unit in a first management table.

4. The memory management method of claim 3, further comprising:

and accessing the first replacement entity erasing unit when accessing the first management unit according to the first management table.

5. The method according to claim 3, wherein the first management table records replacement information of all bad erase units and replacement erase units in the plurality of erase units.

6. The method according to claim 1, wherein each of the plurality of management units has the same number of the plurality of physically erased cells.

7. The method according to claim 1, wherein the step of combining the plurality of physical erase units into the plurality of management units comprises:

and combining the plurality of entity erasing units into a plurality of management units according to a second management table, wherein the second management table records all the bad entity erasing units in the rewritable nonvolatile memory module.

8. A memory storage device, comprising:

the connection interface unit is used for being coupled to a host system;

the memory module comprises a plurality of crystal grains, each crystal grain comprises a plurality of planes, each plane comprises a plurality of entity erasing units, and the total number of the planes in the memory module is a first number; and

a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for combining the plurality of physical erasing units into a plurality of management units,

wherein each of the plurality of management units comprises a plurality of physically erasable units belonging to different planes, and each of the plurality of management units has a second number of the plurality of physically erasable units,

wherein the second number is less than the first number.

9. The memory storage device of claim 8, wherein the plurality of management units includes a first management unit, and in response to detecting that the first management unit includes a first bad-entity-erased cell, the memory control circuit unit is further configured to retrieve a first replacement-entity-erased cell to replace the first bad-entity-erased cell,

wherein the first replacement solid erased unit and the first bad solid erased unit belong to the same plane.

10. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to record the replacement information of the first bad physical erase unit and the first replacement physical erase unit in the first management table.

11. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to access the first replacement physical erase unit when accessing the first management unit according to the first management table.

12. The memory storage device of claim 10, wherein the first management table records replacement information for all bad physically erased cells and replacement physically erased cells in the plurality of physically erased cells.

13. The memory storage device of claim 8, wherein each of said plurality of management units has the same number of said plurality of physically erased cells.

14. The memory storage device of claim 8, wherein the operation of combining the plurality of physically erased units into the plurality of management units comprises:

and combining the entity erasing units into a plurality of management units according to a second management table, wherein the second management table records all bad entity erasing units in the rewritable nonvolatile memory module.

15. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of dies, each of the plurality of dies includes a plurality of planes, each of the plurality of planes includes a plurality of physical erase units, and the number of the plurality of planes included in the rewritable nonvolatile memory module is summed to a first number, the memory control circuit unit comprising:

a host interface for coupling to a host system;

a memory interface to couple to the rewritable non-volatile memory module; and

memory management circuitry coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to combine the plurality of physically erased cells into a plurality of management cells,

wherein the second number is less than the first number.

16. The memory control circuit unit of claim 15, wherein the plurality of management units includes a first management unit, and in response to detecting that the first management unit includes a first bad-entity-erased cell, the memory management circuit is further configured to retrieve a first replacement-entity-erased cell to replace the first bad-entity-erased cell,

17. The memory control circuit unit of claim 16, wherein the memory management circuit is further configured to record replacement information of the first bad erase unit and the first replacement erase unit in a first management table.

18. The memory control circuit unit of claim 17, wherein the memory management circuit is further configured to access the first replacement physical erase unit when accessing the first management unit according to the first management table.

19. The memory control circuit unit of claim 17, wherein the first management table records replacement information of all bad erase units and replacement erase units of the plurality of erase units.

20. The memory control circuit unit of claim 15, wherein each of the plurality of management units has the same number of the plurality of physically erased cells.

21. The memory control circuit unit of claim 15, wherein the operation of combining the plurality of physically erased units into the plurality of managing units comprises: