CN114613420A - Coding control method, memory storage device and memory control circuit unit - Google Patents

Coding control method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN114613420A
CN114613420A CN202210240997.2A CN202210240997A CN114613420A CN 114613420 A CN114613420 A CN 114613420A CN 202210240997 A CN202210240997 A CN 202210240997A CN 114613420 A CN114613420 A CN 114613420A
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circuit
data
encoding
sub
matrix
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林玉祥
黄柏纶
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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Abstract

The invention provides a coding control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: performing, by an encoding circuit, a first encoding operation according to the write data, a first sub-matrix and a second sub-matrix of the parity check matrix to generate first parity data; performing, by the encoding circuit, a second encoding operation according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix, and a fifth sub-matrix of the parity check matrices to generate second parity data; and sending a first write command sequence to instruct to store the write data, the first parity data and the second parity data into a rewritable non-volatile memory module. Therefore, the operation flexibility of the memory storage device during data access can be improved.

Description

Coding control method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a coding control technology, and more particularly, to a coding control method, a memory storage device and a memory control circuit unit.
Background
Generally, to maintain the reliability of data, the data is encoded to generate corresponding error correction codes before being stored in the rewritable nonvolatile memory module. Then, the ECC is stored in the rewritable nonvolatile memory module with the corresponding data. Thereafter, when the data is read from the rewritable nonvolatile memory module, the corresponding error correction code can be used to correct the possible errors in the data. However, the data length of the error correction code generated by a single encoding circuit cannot be dynamically adjusted, and the use of the error correction code is not flexible. If it is necessary to generate error correction codes with different data lengths, a plurality of coding circuits are required, which is not cost-effective.
Disclosure of Invention
The invention provides a coding control method, a memory storage device and a memory control circuit unit, which can generate parity data with different data lengths by a single coding circuit.
An exemplary embodiment of the present invention provides a code control method for a rewritable nonvolatile memory module. The encoding control method comprises the following steps: receiving write data from a host system; performing, by an encoding circuit, a first encoding operation according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate first parity data; performing, by the encoding circuit, a second encoding operation according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate second parity data; and sending a first write command sequence to instruct to store the write data, the first parity data and the second parity data into the rewritable non-volatile memory module.
In an exemplary embodiment of the present invention, the first encoding operation includes: providing, by a first channel switching circuit of the encoding circuits, the write data to a first encoding circuit of the encoding circuits; generating, by the first encoding circuit, first transient data from the write data and the first sub-matrix; providing, by a second channel switching circuit of the encoding circuits, the first transient data to a second encoding circuit of the encoding circuits; and generating, by the second encoding circuit, the first parity data according to the first transient data and the second sub-matrix.
In an exemplary embodiment of the present invention, the second encoding operation includes: providing, by a first channel switching circuit of the encoding circuits, the write data to a first encoding circuit of the encoding circuits; feeding back, by the first channel switching circuit, the first parity data to the first encoding circuit; generating, by the first encoding circuit, second transient data according to the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix; providing, by a second channel switching circuit of the encoding circuits, the second transient data to a second encoding circuit of the encoding circuits; and generating, by the second encoding circuit, the second parity data according to the second transient data and the fifth sub-matrix.
In an exemplary embodiment of the present invention, the step of generating the second transient data by the first encoding circuit according to the write data, the first parity data, the third sub-matrix and the fourth sub-matrix comprises: generating, by a first matrix operation circuit in the first encoding circuit, first sub-transient data according to the write data and the third sub-matrix; generating, by the first matrix operation circuit, second sub-transient data according to the first parity data and the fourth sub-matrix; and generating, by an addition circuit in the first encoding circuit, the second transient data from the first sub-transient data and the second sub-transient data.
In an exemplary embodiment of the present invention, the encoding control method further includes: performing, by the encoding circuit, a third encoding operation according to the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity check matrices, a seventh sub-matrix of the parity check matrices, and an eighth sub-matrix of the parity check matrices to generate third parity data; and sending a second write command sequence to instruct to store the third parity data into the rewritable non-volatile memory module.
In an exemplary embodiment of the present invention, the third encoding operation includes: providing, by a first channel switching circuit of the encoding circuits, the write data to a first encoding circuit of the encoding circuits; feeding back, by the first channel switching circuit, the first parity data and the second parity data to the first encoding circuit; generating, by the first encoding circuit, third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix; providing, by a second channel switching circuit of the encoding circuits, the third transient data to a second encoding circuit of the encoding circuits; and generating, by the second encoding circuit, the third parity data from the third transient data and the eighth sub-matrix.
In an exemplary embodiment of the invention, the step of generating the third transient data by the first encoding circuit in the encoding circuit according to the write data, the first parity data, the second parity data, the sixth sub-matrix and the seventh sub-matrix comprises: generating, by a first matrix operation circuit in the first encoding circuit, third sub-transient data according to the write data and the sixth sub-matrix; generating, by the first matrix operation circuit, fourth sub-transient data according to the first parity data, the second parity data, and the seventh sub-matrix; and generating, by an addition circuit in the first encoding circuit, the third transient data from the third sub-transient data and the fourth sub-transient data.
In an exemplary embodiment of the invention, the step of generating the third transient data by the first encoding circuit in the encoding circuit according to the write data, the first parity data, the second parity data, the sixth sub-matrix and the seventh sub-matrix further includes: providing, by a third channel switching circuit in the first encoding circuit, the third sub-transient data and the fourth sub-transient data to the summing circuit.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: receiving write data from the host system; and sending a first write command sequence to indicate that the write data, the first parity data and the second parity data are stored in the rewritable non-volatile memory module. The memory control circuit unit includes an encoding circuit, and the encoding circuit is to: performing a first encoding operation according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate the first parity data; and performing a second encoding operation according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate the second parity data.
In an exemplary embodiment of the present invention, the encoding circuit includes a first channel switching circuit, a first encoding circuit, a second channel switching circuit, and a second encoding circuit. The first encoding circuit is connected to the first channel switching circuit. The second channel switching circuit is connected to the first encoding circuit. The second encoding circuit is connected to the second channel switching circuit and the first channel switching circuit. In the first encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit. The first encoding circuit is used for generating first transient data according to the write data and the first sub-matrix. The second channel switching circuit is used for providing the first transient data to the second encoding circuit. The second encoding circuit is configured to generate the first parity data according to the first transient data and the second sub-matrix.
In an exemplary embodiment of the present invention, the encoding circuit includes a first channel switching circuit, a first encoding circuit, a second channel switching circuit, and a second encoding circuit. The first encoding circuit is connected to the first channel switching circuit. The second channel switching circuit is connected to the first encoding circuit. The second encoding circuit is connected to the second channel switching circuit and the first channel switching circuit. In the second encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit. The first channel switching circuit is further configured to feed back the first parity data to the first encoding circuit. The first encoding circuit is configured to generate second transient data according to the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix. The second channel switching circuit is configured to provide the second transient data to the second encoding circuit. The second encoding circuit is configured to generate the second parity data according to the second transient data and the fifth sub-matrix.
In an exemplary embodiment of the present invention, the first encoding circuit includes a first matrix operation circuit and an addition circuit. The first matrix operation circuit is connected to the first channel switching circuit. The addition circuit is connected to the first matrix operation circuit and the second channel switching circuit. In the second encoding operation, the first matrix operation circuit is configured to generate first sub-transient data according to the write data and the third sub-matrix and generate second sub-transient data according to the first parity data and the fourth sub-matrix. The adder circuit is configured to generate the second transient data according to the first sub-transient data and the second sub-transient data.
In an exemplary embodiment of the invention, the encoding circuit is further configured to perform a third encoding operation according to the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity check matrices, a seventh sub-matrix of the parity check matrices, and an eighth sub-matrix of the parity check matrices to generate third parity data. The memory control circuit unit is further configured to send a second write command sequence to instruct to store the third parity data into the rewritable non-volatile memory module.
In an exemplary embodiment of the present invention, the encoding circuit includes a first channel switching circuit, a first encoding circuit, a second channel switching circuit, and a second encoding circuit. The first encoding circuit is connected to the first channel switching circuit. The second channel switching circuit is connected to the first encoding circuit. The second encoding circuit is connected to the second channel switching circuit and the first channel switching circuit. In the third encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit. The first channel switching circuit is further configured to feed back the first parity data and the second parity data to the first encoding circuit. The first encoding circuit is configured to generate third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix. The second channel switching circuit is configured to provide the third transient data to the second encoding circuit. The second encoding circuit is configured to generate the third parity data according to the third transient data and the eighth sub-matrix.
In an exemplary embodiment of the present invention, the first encoding circuit includes a first matrix operation circuit and an addition circuit. The first matrix operation circuit is connected to the first channel switching circuit. The addition circuit is connected to the first matrix operation circuit and the second channel switching circuit. In the third encoding operation, the first matrix operation circuit is configured to generate third sub-transient data according to the write data and the sixth sub-matrix and generate fourth sub-transient data according to the first parity data, the second parity data and the seventh sub-matrix. The adder circuit is configured to generate the third transient data according to the third sub-transient data and the fourth sub-transient data.
In an exemplary embodiment of the present invention, the first encoding circuit further includes a third channel switching circuit connected between the first matrix operation circuit and the addition circuit. In the third encoding operation, the third channel switching circuit is to provide the third sub-transient data and the fourth sub-transient data to the summing circuit.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface, a coding circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the encoding circuit. The memory management circuitry to: receiving write data from the host system; sending a first write command sequence to instruct to store the write data, the first parity data and the second parity data into the rewritable non-volatile memory module. The encoding circuit to perform a first encoding operation according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate the first parity data; and performing a second encoding operation according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate the second parity data.
In an exemplary embodiment of the invention, the encoding circuit is further configured to perform a third encoding operation according to the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity check matrices, a seventh sub-matrix of the parity check matrices, and an eighth sub-matrix of the parity check matrices to generate third parity data. The memory management circuit is further configured to send a second write command sequence to instruct the third parity data to be stored in the rewritable non-volatile memory module.
Based on the above, after receiving the write data, the encoding circuit may dynamically generate the first parity data and the second parity data according to different sub-matrices in the same parity check matrix. Thereafter, the first parity data may be used alone or in conjunction with the second parity data to decode the write data, depending on the operating conditions. Therefore, the operation flexibility of the memory storage device during data access can be improved.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;
FIG. 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;
FIG. 7B is a schematic diagram of an encoding circuit according to an exemplary embodiment of the present invention;
FIG. 8A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;
FIG. 8B is a schematic diagram of an encoding circuit according to an exemplary embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a decoding flow according to an exemplary embodiment of the present invention;
fig. 10 is a flowchart illustrating an encoding control method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.
In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner.
In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.
FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.
The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Flash) interface standard, CF interface standard, Device interface standard, and Electronic drive interface (Electronic interface), IDE) standard or other suitable standard. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands of the host system 11.
The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 5 is a diagram illustrating a memory control circuit unit according to an exemplary embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, a memory interface 53 and an error checking and correcting circuit 54.
The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, it is equivalent to the operation of the memory control circuit unit 42.
In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 43 so as to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.
The host interface 52 is connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.
The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are/is read at the same time, and the error checking and correcting circuit 54 performs the error checking and correcting operation on the read data according to the error correction code and/or the error check code.
In an exemplary embodiment, the error checking and correction circuit 54 may support low-density parity-check (LDPC) codes. For example, the error checking and correcting circuit 508 may utilize low density parity check codes for encoding and decoding. In an exemplary embodiment, the error checking and correcting circuit 54 may also employ other types of coding algorithms, such as BCH or Reed-Solomon (RS) codes, and the invention is not limited thereto.
In an exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56. The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is a power supply connected to the memory management circuit 51 and used to control the memory storage device 10.
In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.
FIG. 6 is a diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable nonvolatile memory module 43 into a storage area 601 and an idle (spare) area 602.
In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also refer to a Virtual Block (VB). A virtual block may include a plurality of physical addresses or a plurality of physical programming units.
Physical units 610(0) -610 (A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG. 1). For example, entity units 610(0) -610 (A) in memory area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When new data is written, one or more physical units may be fetched from the idle region 602 to store the new data. In an exemplary embodiment, the idle region 602 is also referred to as a free pool.
Memory management circuitry 51 may configure logic units 612(0) - (612 (C) to map physical units 610(0) - (610 (A) in memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic program unit or be composed of a plurality of continuous or discontinuous logic addresses.
It is noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, it indicates that the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not currently mapped by any logic unit, it indicates that the data currently stored in the entity unit is invalid.
The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing mapping relationships between the logical units and the physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.
In low density parity check codes, a check matrix (also called parity check matrix) is used to define the valid code words. The parity check matrix is hereinafter labeled as matrix M and a codeword is labeled as V. According to the following procedure (1), if the multiplication of the parity check matrix M and the codeword V is a zero vector, it indicates that the codeword V is a valid codeword. Where operator x represents a matrix multiplication modulo 2(mod 2). In other words, the null space (null space) of the matrix M contains all valid codewords (valid codewords). However, the invention does not limit the content of the codeword V. For example, the codeword V may also comprise an error correction code or an error check code generated by any algorithm.
V×MT＝0 (1)
The codeword V may comprise information bits and parity bits, i.e. the codeword V may be denoted [ U P ]. The vector U is composed of information bits. The vector P is composed of parity bits. The vector U is also referred to as write data (or data to be encoded). The vector P is also referred to as parity data.
In a codeword, parity bits (i.e., parity data) are used to protect information bits (i.e., write data) and may be considered to be an error correction code or error check code generated corresponding to the information bits. Protecting the information bits means, for example, maintaining the correctness of the information bits. For example, when reading information bits from the rewritable nonvolatile memory module 43, the parity bits corresponding to the information bits can be used to correct errors that may exist in the information bits.
In decoding a codeword V, a parity check operation is performed on the codeword V, such as multiplying the matrix M by the codeword V to generate a vector (denoted S below, as shown in the following procedure (2)). Each element in the vector S is also referred to as a syndrome. The vector S is also referred to as syndrome data. If the vector S is a zero vector (i.e., every element in the vector S is zero), the codeword V can be directly output. If vector S is not a zero vector (i.e., at least one element in vector S is not zero), it indicates that there is at least one error in codeword V and that codeword V is not a valid codeword. If the codeword V is not a valid codeword, the error checking and correcting circuit 54 may perform a decoding operation to attempt to correct the error in the codeword V.
V×HT＝S (2)
In an exemplary embodiment, the error checking and correcting circuit 54 may include an encoding circuit 541 and a decoding circuit 542. The encoding circuit 541 encodes data. The decoding circuit 542 is used for decoding data. In an exemplary embodiment, the encoding circuit 541 and the decoding circuit 542 may be combined into a single encoding/decoding circuit.
The memory management circuit 51 may receive write data from the host system 11. The encoding circuit 541 may perform an encoding operation (also referred to as a first encoding operation) according to the write data and a plurality of sub-matrices (also referred to as a first sub-matrix and a second sub-matrix) in the matrix M to generate parity data (also referred to as first parity data). After generating the first parity data, the encoding circuit 541 may perform another encoding operation (also referred to as a second encoding operation) according to the write data, the first parity data, and a plurality of sub-matrices (also referred to as a third sub-matrix, a fourth sub-matrix, and a fifth sub-matrix) in the matrix M to generate parity data (also referred to as second parity data). The first parity data is different from the second parity data. Further, the first parity data may decode the write data alone or in conjunction with the second parity data.
After encoding the write data, the memory management circuit 51 may send a write command sequence (also referred to as a first write command sequence) to the rewritable nonvolatile memory module 43. The first write command sequence can be used to instruct the rewritable non-volatile memory module 43 to store the write data, the first parity data, and the second parity data into the rewritable non-volatile memory module 43. Thereafter, when the write data is read from the rewritable non-volatile memory module 43, the memory management circuit 51 may read the first parity data (and the second parity data) from the rewritable non-volatile memory module 43 together. The decoding circuit 542 can decode the write data read from the rewritable non-volatile memory module 43 according to the first parity data (and the second parity data) to detect and correct errors in the write data.
Fig. 7A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention. Referring to FIG. 7A, in an exemplary embodiment, the structure of matrix M (i.e., parity check matrix) is shown as matrix 701. Matrix 701 includes sub-matrices A-E and X. The submatrix X is a zero matrix, and the submatrices A-E are not zero matrices. The sub-matrix a may be an m × k matrix. The submatrix B may be an m × m matrix. The sub-matrix C may be an x × k matrix. The sub-matrix D may be an x × m matrix. The sub-matrix E may be an x matrix. The submatrix X may be an mxx matrix. k. m and x are both positive integers, k can be greater than m, and m can be greater than x. The arrangement of the sub-matrices a to E and X in the matrix 701 is as shown in fig. 7A, but is not limited thereto.
In an exemplary embodiment, the first parity data may be generated according to the following procedure (3). In square procedure (3), U represents the write data to be encoded, a and B represent the sub-matrices a and B, respectively, in matrix 701, and P (1) represents the first parity data. In addition, the process (3) can be further broken down into the following processes (3.1) and (3.2). In equations (3.1) and (3.2), Q (1) represents the transient data (also referred to as first transient data) used in generating the first parity data.
P(1)＝(BT)-1×(AT×U) (3)
Q(1)＝AT×U (3.1)
P(1)＝(BT)-1×Q(1) (3.2)
In an exemplary embodiment, the second parity data may be generated according to the following procedure (4). In equation (4), C, D and E represent sub-matrices C, D and E, respectively, in matrix 701, and P (2) represents the second parity data. In addition, the process (4) can be further broken down into the following processes (4.1) to (4.5). In equations (4.1) and (4.2), Q (2) represents the transient data (also referred to as second transient data) used in generating the second parity data. In the square procedures (4.3) to (4.5), R (1) and R (2) represent sub-transient data (also referred to as first sub-transient data and second sub-transient data) used in the process of generating the second transient data, respectively.
P(2)＝(ET)-1×(CT×U+DT×P(1)) (4)
Q(2)＝CT×U+DT×P(1) (4.1)
P(2)＝(ET)-1×Q(2) (4.2)
R(1)＝CT×U (4.3)
R(2)＝DT×P(1) (4.4)
Q(2)＝R(1)+R(2) (4.5)
FIG. 7B is a diagram illustrating an encoding circuit according to an exemplary embodiment of the invention. Referring to fig. 7A and 7B, the encoding circuit 541 may include a channel switching circuit (also referred to as a first channel switching circuit) 71, an encoding circuit (also referred to as a first encoding circuit) 72, a channel switching circuit (also referred to as a second channel switching circuit) 73, and an encoding circuit (also referred to as a second encoding circuit) 74. The encoding circuit 72 is connected to the channel switching circuits 71 and 73. The encoding circuit 74 is connected to the channel switching circuits 71 and 73.
The encoding circuit 541 may perform a first encoding operation to generate parity data P (1). In the first encoding operation, the channel switching circuit 71 may supply the write data U to the encoding circuit 72. The encoding circuit 72 may perform operations corresponding to the equation sequence (3.1) according to the write data U and the sub-matrix a to generate the transient data Q (1). The channel switching circuit 73 may provide the transient data Q (1) to the encoding circuit 74. The encoding circuit 74 may perform operations corresponding to the equation sequence (3.2) according to the transient data Q (1) and the submatrix B to generate the parity data P (1).
After performing the first encoding operation, the encoding circuit 541 may perform a second encoding operation to generate parity data P (2). In the second encoding operation, the channel switching circuit 71 may provide the write data U to the encoding circuit 72 and feed back the parity data P (1) generated by the first encoding operation to the encoding circuit 72. The encoding circuit 72 may perform operations corresponding to the equation sequence (4.1) according to the write data U, the parity data P (1), the sub-matrix C, and the sub-matrix D to generate the transient data Q (2). The channel switching circuit 73 may provide the transient data Q (2) to the encoding circuit 74. The encoding circuit 74 may perform operations corresponding to the equation (4.2) according to the transient data Q (2) and the sub-matrix E to generate the parity data P (2).
Both channel switching circuits 71 and 73 may include a Multiplexer (Multiplexer). The encoding circuit 72 may include a table circuit 721, a matrix operation circuit (also referred to as a first matrix operation circuit) 722, and an addition circuit 723. The matrix operation circuit 722 is connected to the channel switching circuit 71, the table circuit 721, and the addition circuit 723. The table circuit 721 stores information of the submatrices A, C and D. The matrix operation circuit 722 may include at least one shifter, at least one Exclusive OR (XOR) circuit, and at least one register to perform a desired operation function. The adder 723 may comprise at least one xor circuit and at least one register to perform a desired operation function.
The encoding circuit 74 may include a table circuit 741 and a matrix operation circuit (also referred to as a second matrix operation circuit) 742. The matrix operation circuit 742 is connected to the channel switching circuit 73, the table circuit 741, and the channel switching circuit 71. The table circuit 741 stores information of the sub-matrices B and E. The matrix operation circuit 742 may include the same or similar circuit structure as the matrix operation circuit 722 to perform the desired operation function.
In the first encoding operation, the matrix operation circuit 722 may obtain information of the sub-matrix a from the table circuit 721 and receive the write data U via the channel switching circuit 71. The matrix operation circuit 722 may perform a matrix operation corresponding to the equation (3.1) according to the write data U and the sub-matrix a to generate the transient data Q (1). The matrix operation circuit 742 may obtain information of the sub-matrix B (e.g., information of an inverse matrix of the sub-matrix B) from the table circuit 741 and receive the transient data Q (1) via the channel switching circuit 73. The matrix operation circuit 742 may perform a matrix operation corresponding to the equation sequence (3.2) according to the transient data Q (1) and the sub-matrix B (i.e., an inverse matrix of the sub-matrix B) to generate the parity data P (1).
In the second encoding operation, the matrix operation circuit 722 may receive the information of the sub-matrices C and D from the table circuit 721 and the write data U and the parity data P (1) through the channel switching circuit 71. The matrix operation circuit 722 may perform operations corresponding to the equation (4.3) according to the write data U and the sub-matrix C to generate the sub-transient data R (1) and perform operations corresponding to the equation (4.4) according to the parity data P (1) and the sub-matrix D to generate the sub-transient data R (2). The adder circuit 723 may perform operations corresponding to the equation (4.5) according to the sub-transient data R (1) and R (2) to generate the transient data Q (2). The matrix operation circuit 742 may obtain information of the sub-matrix E (e.g., information of an inverse matrix of the sub-matrix E) from the table circuit 741 and receive the transient data Q (2) via the channel switching circuit 73. The matrix operation circuit 742 may perform a matrix operation corresponding to the equation (4.2) according to the transient data Q (2) and the sub-matrix E (i.e., an inverse matrix of the sub-matrix E) to generate the parity data P (2).
In other words, in the exemplary embodiments of fig. 7A and 7B, the parity data P (1) and P (2) can be sequentially generated by the same encoding circuit 541. Thus, the utilization efficiency of the encoding circuit 541 can be effectively improved.
In an example embodiment, the encoding circuit 541 may further perform another encoding operation (also referred to as a third encoding operation) according to the write data, the first parity data, the second parity data, and a plurality of sub-matrices (also referred to as a sixth sub-matrix, a seventh sub-matrix, and an eighth sub-matrix) in the matrix M to generate parity data (also referred to as third parity data). The first parity data, the second parity data, and the third parity data are different from each other. In addition, the first parity data may decode the write data alone, in conjunction with the second parity data, or in conjunction with the second parity data and the third parity data.
After generating the third parity data, the memory management circuit 51 may also send a write command sequence (also referred to as a second write command sequence) to the rewritable non-volatile memory module 43. The second write command sequence can be used to instruct the rewritable non-volatile memory module 43 to store the third parity data into the rewritable non-volatile memory module 43. Thereafter, when the write data is read from the rewritable non-volatile memory module 43, the memory management circuit 51 may also read the third parity data from the rewritable non-volatile memory module 43 together. The decoding circuit 542 can also decode the write data read from the rewritable non-volatile memory module 43 according to the first parity data, the second parity data and the third parity data to detect and correct errors in the write data.
Fig. 8A is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention. Referring to FIG. 8A, in an exemplary embodiment, matrix M (i.e., parity check matrix) is structured as matrix 801. The matrix 801 includes the matrix 701 of FIG. 7A, the sub-matrices F-H and Y. The sub-matrix Y is a zero matrix and the sub-matrices F-H are not zero matrices. The sub-matrix F may be a y × k matrix. The sub-matrix G may be a y (m + x) matrix. The sub-matrix H may be a y x y matrix. The sub-matrix Y may be an (m + x) × Y matrix. k. m, x and y are all positive integers, k can be greater than m, and m can be greater than x and y. The matrix 701 and the sub-matrices F to H and Y are arranged in the matrix 801 as shown in fig. 8A, but not limited thereto. In other words, matrix 801 may be expanded by matrix 701 (plus sub-matrices F H and Y).
In an exemplary embodiment, the third parity data may be generated according to the following procedure (5). In equation 5, F, G and H represent submatrices F, G and H, respectively, in matrix 801, and P (3) represents third parity data. In addition, the process (5) can be further broken down into the following processes (5.1) to (5.5). In equations (5.1) and (5.2), Q (3) represents the transient data used in generating the third parity data (also referred to as third transient data). In the square procedures (5.3) to (5.5), R (3) and R (4) represent sub-transient data (also referred to as third sub-transient data and fourth sub-transient data) used in the process of generating the third transient data, respectively.
P(3)＝(HT)-1×(FT×U+GT×{P(1),P(2)}) (5)
Q(3)＝FT×U+GT×{P(1),P(2)} (5.1)
P(3)＝(HT)-1×Q(3) (5.2)
R(3)＝FT×U (5.3)
R(4)＝GT×{P(1),P(2)} (5.4)
Q(3)＝R(3)+R(4) (5.5)
FIG. 8B is a diagram illustrating an encoding circuit according to an exemplary embodiment of the invention. Referring to fig. 8A and 8B, the encoding circuit 541 includes a channel switching circuit (i.e., a first channel switching circuit) 81, an encoding circuit (i.e., a first encoding circuit) 82, a channel switching circuit (i.e., a second channel switching circuit) 83, and an encoding circuit (i.e., a second encoding circuit) 84. The encoding circuit 82 is connected to the channel switching circuits 81 and 83. The encoding circuit 84 is connected to the channel switching circuits 81 and 83.
The encoding circuit 541 may perform a first encoding operation to generate parity data P (1). In the first encoding operation, the channel switching circuit 81 may supply the write data U to the encoding circuit 82. The encoding circuit 82 may perform operations corresponding to the equation (3.1) according to the write data U and the sub-matrix a to generate the transient data Q (1). The channel switching circuit 83 may provide the transient data Q (1) to the encoding circuit 84. The encoding circuit 84 may perform operations corresponding to the equation (3.2) according to the transient data Q (1) and the submatrix B to generate the parity data P (1).
After performing the first encoding operation, the encoding circuit 541 may perform a second encoding operation to generate parity data P (2). In the second encoding operation, the channel switching circuit 81 may provide the write data U to the encoding circuit 82 and feed back the parity data P (1) generated by the first encoding operation to the encoding circuit 82. The encoding circuit 82 may perform operations corresponding to the equation sequence (4.1) according to the write data U, the parity data P (1), the sub-matrix C, and the sub-matrix D to generate the transient data Q (2). The channel switching circuit 83 may provide the transient data Q (2) to the encoding circuit 84. The encoding circuit 84 may perform operations corresponding to the equation (4.2) according to the transient data Q (2) and the sub-matrix E to generate the parity data P (2).
After performing the second encoding operation, the encoding circuit 541 may perform a third encoding operation to generate parity data P (3). In the third encoding operation, the channel switching circuit 81 may supply the write data U to the encoding circuit 82, feed back the parity data P (1) generated by the first encoding operation to the encoding circuit 82, and feed back the parity data P (2) generated by the second encoding operation to the encoding circuit 82. The encoding circuit 82 may perform operations corresponding to the equation sequence (5.1) according to the write data U, the parity data P (1), the parity data P (2), the sub-matrix F, and the sub-matrix G to generate the transient data Q (3). The channel switching circuit 83 may provide the transient data Q (3) to the encoding circuit 84. The encoding circuit 84 may perform the operation corresponding to the equation (5.2) according to the transient data Q (3) and the submatrix H to generate the parity data P (3).
Both channel switching circuits 81 and 83 may include multiplexers. It should be noted that the encoding circuit 82 may include a table circuit 821, a matrix operation circuit (i.e., a first matrix operation circuit) 822, a channel switching circuit (also referred to as a third channel switching circuit) 823, and an adding circuit 824. The channel switching circuit 823 is connected between the matrix operation circuit 822 and the addition circuit 824. The channel switching circuit 823 may include a multiplexer. The table circuit 821 stores information of the submatrices A, C, D, F and G. The matrix operation circuit 822 may include at least one shifter, at least one exclusive-or circuit, and at least one register to perform the desired operation function. The adder 824 may include at least one XOR circuit and at least one register to perform the desired operation.
The encoding circuit 84 may include a table circuit 841 and a matrix operation circuit (i.e., a second matrix operation circuit) 842. The table circuit 841 stores information of the submatrices B, E and H. The matrix operation circuit 842 may include the same or similar circuit structure as the matrix operation circuit 822 to perform the required operation function.
In the first encoding operation, the matrix operation circuit 822 may obtain information of the sub-matrix a from the table circuit 821 and receive the write data U via the channel switching circuit 81. The matrix operation circuit 822 can perform a matrix operation corresponding to the equation (3.1) according to the write data U and the sub-matrix a to generate the transient data Q (1). The matrix operation circuit 842 can obtain the information of the sub-matrix B (e.g. the information of the inverse matrix of the sub-matrix B) from the table circuit 841 and receive the transient data Q (1) via the channel switching circuit 83. The matrix operation circuit 842 may perform a matrix operation corresponding to the equation order (3.2) according to the transient data Q (1) and the sub-matrix B (i.e., an inverse matrix of the sub-matrix B) to generate the parity data P (1).
In the second encoding operation, the matrix operation circuit 822 may receive the information of the sub-matrices C and D from the table circuit 821 and the write data U and the parity data P (1) through the channel switching circuit 81. The matrix operation circuit 822 may perform operations corresponding to the equation (4.3) according to the write data U and the sub-matrix C to generate the sub-transient data R (1) and perform operations corresponding to the equation (4.4) according to the parity data P (1) and the sub-matrix D to generate the sub-transient data R (2). The channel switching circuit 823 may provide the sub-transient data R (1) and R (2) to the addition circuit 824. The adder circuit 824 may perform operations corresponding to the equation (4.5) according to the sub-transient data R (1) and R (2) to generate the transient data Q (2). The matrix operation circuit 842 can obtain the information of the sub-matrix E (e.g. the information of the inverse matrix of the sub-matrix E) from the table circuit 841 and receive the transient data Q (2) via the channel switching circuit 83. The matrix operation circuit 842 may perform a matrix operation corresponding to the equation order (4.2) according to the transient data Q (2) and the sub-matrix E (i.e., an inverse matrix of the sub-matrix E) to generate the parity data P (2).
In the third encoding operation, the matrix operation circuit 822 may receive the information of the sub-matrices F and G from the table circuit 821 and the write data U, the parity data P (1) and the parity data P (2) through the channel switching circuit 81. The matrix operation circuit 822 can perform operations corresponding to the equation (5.3) according to the write data U and the sub-matrix F to generate the sub-transient data R (3) and perform operations corresponding to the equation (5.4) according to the parity data P (1), the parity data P (2) and the sub-matrix G to generate the sub-transient data R (4). The channel switching circuit 823 may provide the sub-transient data R (3) and R (4) to the addition circuit 824. The adder circuit 824 may perform an operation corresponding to the square procedure (5.5) according to the sub-transient data R (3) and R (4) to generate the transient data Q (3). The matrix operation circuit 842 can obtain the information of the submatrix H (e.g. the information of the inverse matrix of the submatrix H) from the table circuit 841 and receive the transient data Q (3) via the channel switching circuit 83. The matrix operation circuit 842 may perform a matrix operation corresponding to the equation sequence (5.2) according to the transient data Q (3) and the sub-matrix H (i.e., an inverse matrix of the sub-matrix H) to generate the parity data P (3).
In other words, in the example embodiments of fig. 8A and 8B, the parity data P (1), P (2), and P (3) may be sequentially generated by the same encoding circuit 541. Thus, the utilization efficiency of the encoding circuit 541 can be further improved.
Fig. 9 is a diagram illustrating a decoding process according to an exemplary embodiment of the present invention. Referring to fig. 9, it is assumed that parity data P (1) to P (3) are generated by encoding write data 901 stored in the rewritable nonvolatile memory module 43. The details of the related operations are described above, and are not repeated herein.
After the write data 901 is read from the rewritable nonvolatile memory module 43, the parity data P (1) can be read from the rewritable nonvolatile memory module 43 at the same time. The decoding circuit 542 may use the parity data P (1) to decode the write data 901. If the write data 901 can be successfully decoded according to the parity data P (1) (e.g., all errors in the read write data 901 are corrected), the decoding of the write data 901 can be ended.
However, if the write data 901 cannot be successfully decoded according to the parity data P (1) (e.g., all errors in the read write data 901 cannot be corrected), the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to read the parity data P (2). The decoding circuit 542 can use the parity data P (1) and P (2) to decode the write data 901. For example, the parity data P (1) and P (2) can be combined into parity data P (12) having a longer data length to decode the write data 901. In particular, the data length of the parity data P (12) is longer than the data length of the parity data P (1), so the error correction capability of the parity data P (12) can be higher than that of the parity data P (1). Therefore, the decoding success rate for decoding the write data 901 using the parity data P (12) can be higher than the decoding success rate for decoding the write data 901 using the parity data P (1).
However, if the write data 901 still cannot be successfully decoded according to the parity data P (12), the memory management circuit 51 may further instruct the rewritable non-volatile memory module 43 to read the parity data P (3). The decoding circuit 542 may use the parity data P (1), P (2), and P (3) to decode the write data 901. For example, the parity data P (1), P (2), and P (3) can be combined into parity data P (13) with a longer data length to decode the write data 901. In particular, the data length of the parity data P (13) is longer than the data length of the parity data P (12), so the error correction capability of the parity data P (13) can be higher than that of the parity data P (12). Therefore, the decoding success rate for decoding the write data 901 using the parity data P (13) can be higher than the decoding success rate for decoding the write data 901 using the parity data P (12). In an exemplary embodiment, the decoding circuit 542 can gradually improve the error correction capability of the write data 901 by gradually increasing the data length of the parity data during the decoding process.
In the example embodiment of FIG. 9, the parity data P (1), P (12), and P (13) can be used separately to decode the write data 901. However, the parity data P (2) and P (3) cannot be used alone to decode the write data 901.
In an exemplary embodiment, by expanding the matrix 801 (e.g., adding more sub-matrices to the matrix 801), the encoding circuit 541 can encode the same write data according to the expanded matrix 801 to generate more parity data P (4) -P (n). In response to a decoding failure, parity data P (4) -P (n) may be sequentially used to extend the data length of the original parity data P (1) when the write data is subsequently decoded. Therefore, the success rate of decoding the written data can be effectively improved.
Fig. 10 is a flowchart illustrating an encoding control method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, write data is received from a host system. In step S1002, a first encoding operation is performed by an encoding circuit according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate first parity data. In step S1003, a second encoding operation is performed by the encoding circuit according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate second parity data. The first parity data is used to decode the write data alone or in conjunction with the second parity data. In step S1004, a first write command sequence is sent to instruct the write data, the first parity data and the second parity data to be stored in the rewritable non-volatile memory module.
However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, the exemplary embodiments of the present invention provide a method for generating parity data by encoding the same write data according to different sub-matrices of the same parity check matrix by the same encoding circuit. Such parity data may then be used, either alone or in combination, as desired, to decode the write data. Therefore, the decoding efficiency of the written data and the use flexibility of the coding circuit can be effectively improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (24)

1. An encoding control method for a rewritable nonvolatile memory module, the encoding control method comprising:
receiving write data from a host system;
performing, by an encoding circuit, a first encoding operation according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate first parity data;
performing, by the encoding circuit, a second encoding operation according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate second parity data; and
sending a first write command sequence to instruct storage of the write data, the first parity data, and the second parity data in the rewritable non-volatile memory module.
2. The encoding control method of claim 1, wherein the first encoding operation comprises:
providing, by a first channel switching circuit of the encoding circuits, the write data to a first encoding circuit of the encoding circuits;
generating, by the first encoding circuit, first transient data from the write data and the first sub-matrix;
providing, by a second channel switching circuit of the encoding circuits, the first transient data to a second encoding circuit of the encoding circuits; and
generating, by the second encoding circuit, the first parity data from the first transient data and the second sub-matrix.
3. The encoding control method of claim 1, wherein the second encoding operation comprises:
providing, by a first channel switching circuit of the encoding circuits, the write data to a first encoding circuit of the encoding circuits;
feeding back, by the first channel switching circuit, the first parity data to the first encoding circuit;
generating, by the first encoding circuit, second transient data according to the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix;
providing, by a second channel switching circuit of the encoding circuits, the second transient data to a second encoding circuit of the encoding circuits; and
generating, by the second encoding circuit, the second parity data according to the second transient data and the fifth sub-matrix.
4. The encoding control method of claim 3, wherein the step of generating, by the first encoding circuit, the second transient data according to the write data, the first parity data, the third sub-matrix, and the fourth sub-matrix comprises:
generating, by a first matrix operation circuit in the first encoding circuit, first sub-transient data according to the write data and the third sub-matrix;
generating, by the first matrix operation circuit, second sub-transient data according to the first parity data and the fourth sub-matrix; and
generating, by a summing circuit in the first encoding circuit, the second transient data from the first sub-transient data and the second sub-transient data.
5. The encoding control method of claim 1, further comprising:
performing, by the encoding circuit, a third encoding operation according to the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity check matrices, a seventh sub-matrix of the parity check matrices, and an eighth sub-matrix of the parity check matrices to generate third parity data; and
sending a second write command sequence to instruct to store the third parity data into the rewritable non-volatile memory module.
6. The encoding control method of claim 5, wherein the third encoding operation comprises:
providing, by a first channel switching circuit of the encoding circuits, the write data to a first encoding circuit of the encoding circuits;
feeding back, by the first channel switching circuit, the first parity data and the second parity data to the first encoding circuit;
generating, by the first encoding circuit, third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix;
providing, by a second channel switching circuit of the encoding circuits, the third transient data to a second encoding circuit of the encoding circuits; and
generating, by the second encoding circuit, the third parity data from the third transient data and the eighth sub-matrix.
7. The encoding control method of claim 6, wherein the step of generating, by the first one of the encoding circuits, the third transient data from the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix comprises:
generating, by a first matrix operation circuit in the first encoding circuit, third sub-transient data according to the write data and the sixth sub-matrix;
generating, by the first matrix operation circuit, fourth sub-transient data according to the first parity data, the second parity data, and the seventh sub-matrix; and
generating, by an addition circuit in the first encoding circuit, the third transient data from the third sub-transient data and the fourth sub-transient data.
8. The encoding control method of claim 7, wherein the step of generating, by the first one of the encoding circuits, the third transient data from the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix further comprises:
providing, by a third channel switching circuit in the first encoding circuit, the third sub-transient data and the fourth sub-transient data to the summing circuit.
9. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is to:
receiving write data from the host system;
sending a first write command sequence to instruct storage of the write data, first parity data, and second parity data into the rewritable non-volatile memory module,
the memory control circuit unit includes an encoding circuit, and the encoding circuit is to:
performing a first encoding operation according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate the first parity data; and
performing a second encoding operation according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate the second parity data.
10. The memory storage device of claim 9, wherein the encoding circuit comprises:
a first channel switching circuit;
a first encoding circuit connected to the first channel switching circuit;
a second channel switching circuit connected to the first encoding circuit; and
a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit,
in the first encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit,
the first encoding circuit is used for generating first transient data according to the write data and the first sub-matrix,
the second channel switching circuit is used for providing the first transient data to the second coding circuit, and
the second encoding circuit is configured to generate the first parity data according to the first transient data and the second sub-matrix.
11. The memory storage device of claim 9, wherein the encoding circuit comprises:
a first channel switching circuit;
a first encoding circuit connected to the first channel switching circuit;
a second channel switching circuit connected to the first encoding circuit; and
a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit,
in the second encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit,
the first channel switching circuit is further configured to feed back the first parity data to the first encoding circuit,
the first encoding circuit is used for generating second transient data according to the write data, the first parity data, the third sub-matrix and the fourth sub-matrix,
the second channel switching circuit is used for providing the second transient data to the second coding circuit, and
the second encoding circuit is configured to generate the second parity data according to the second transient data and the fifth sub-matrix.
12. The memory storage device of claim 11, wherein the first encoding circuit comprises:
a first matrix operation circuit connected to the first channel switching circuit; and
an addition circuit connected to the first matrix operation circuit and the second channel switching circuit,
in the second encoding operation, the first matrix operation circuit is configured to generate first sub-transient data according to the write data and the third sub-matrix and generate second sub-transient data according to the first parity data and the fourth sub-matrix, and
the adder circuit is configured to generate the second transient data according to the first sub-transient data and the second sub-transient data.
13. The memory storage device of claim 9, wherein the encoding circuitry is further to perform a third encoding operation based on the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity check matrices, a seventh sub-matrix of the parity check matrices, and an eighth sub-matrix of the parity check matrices to generate third parity data,
the memory control circuit unit is further configured to send a second write command sequence to instruct to store the third parity data into the rewritable non-volatile memory module.
14. The memory storage device of claim 13, wherein the encoding circuit comprises:
a first channel switching circuit;
a first encoding circuit connected to the first channel switching circuit;
a second channel switching circuit connected to the first encoding circuit; and
a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit,
in the third encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit,
the first channel switching circuit is further configured to feed back the first parity data and the second parity data to the first encoding circuit,
the first encoding circuit to generate third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix,
the second channel switching circuit is used for providing the third transient data to the second encoding circuit, and
the second encoding circuit is configured to generate the third parity data according to the third transient data and the eighth sub-matrix.
15. The memory storage device of claim 14, wherein the first encoding circuit comprises:
a first matrix operation circuit connected to the first channel switching circuit; and
an addition circuit connected to the first matrix operation circuit and the second channel switching circuit,
in the third encoding operation, the first matrix operation circuit is configured to generate third sub-transient data according to the write data and the sixth sub-matrix and fourth sub-transient data according to the first parity data, the second parity data and the seventh sub-matrix, and
the adder circuit is configured to generate the third transient data according to the third sub-transient data and the fourth sub-transient data.
16. The memory storage device of claim 15, wherein the first encoding circuit further comprises:
a third channel switching circuit connected between the first matrix operation circuit and the addition circuit,
in the third encoding operation, the third channel switching circuit is to provide the third sub-transient data and the fourth sub-transient data to the summing circuit.
17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module;
an encoding circuit; and
memory management circuitry connected to the host interface, the memory interface, and the encoding circuitry,
wherein the memory management circuitry is to:
receiving write data from the host system;
sending a first write command sequence to instruct storage of the write data, first parity data, and second parity data into the rewritable non-volatile memory module,
the encoding circuit is configured to:
performing a first encoding operation according to the write data, a first sub-matrix of parity check matrices, and a second sub-matrix of the parity check matrices to generate the first parity data; and
performing a second encoding operation according to the write data, the first parity data, a third sub-matrix of the parity check matrices, a fourth sub-matrix of the parity check matrices, and a fifth sub-matrix of the parity check matrices to generate the second parity data.
18. The memory control circuit cell of claim 17, wherein the encoding circuit comprises:
a first channel switching circuit;
a first encoding circuit connected to the first channel switching circuit;
a second channel switching circuit connected to the first encoding circuit; and
a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit,
in the first encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit,
the first encoding circuit is used for generating first transient data according to the write data and the first sub-matrix,
the second channel switching circuit is used for providing the first transient data to the second coding circuit, and
the second encoding circuit is used for generating the first parity data according to the first transient data and the second sub-matrix.
19. The memory control circuit cell of claim 17, wherein the encoding circuit comprises:
a first channel switching circuit;
a first encoding circuit connected to the first channel switching circuit;
a second channel switching circuit connected to the first encoding circuit; and
a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit,
in the second encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit,
the first channel switching circuit is further configured to feed back the first parity data to the first encoding circuit,
the first encoding circuit is used for generating second transient data according to the write data, the first parity data, the third sub-matrix and the fourth sub-matrix,
the second channel switching circuit is configured to provide the second transient data to the second encoding circuit, and
the second encoding circuit is configured to generate the second parity data according to the second transient data and the fifth sub-matrix.
20. The memory control circuit cell of claim 19, wherein the first encoding circuit comprises:
a first matrix operation circuit connected to the first channel switching circuit; and
an addition circuit connected to the first matrix operation circuit and the second channel switching circuit,
in the second encoding operation, the first matrix operation circuit is configured to generate first sub-transient data according to the write data and the third sub-matrix and generate second sub-transient data according to the first parity data and the fourth sub-matrix, and
the adder circuit is configured to generate the second transient data according to the first sub-transient data and the second sub-transient data.
21. The memory control circuit unit of claim 17, wherein the encoding circuit is further to perform a third encoding operation to generate third parity data according to the write data, the first parity data, the second parity data, a sixth sub-matrix of the parity check matrices, a seventh sub-matrix of the parity check matrices, and an eighth sub-matrix of the parity check matrices,
the memory management circuit is further configured to send a second write command sequence to instruct the third parity data to be stored in the rewritable non-volatile memory module.
22. The memory control circuit cell of claim 21, wherein the encoding circuit comprises:
a first channel switching circuit;
a first encoding circuit connected to the first channel switching circuit;
a second channel switching circuit connected to the first encoding circuit; and
a second encoding circuit connected to the second channel switching circuit and the first channel switching circuit,
in the third encoding operation, the first channel switching circuit is configured to provide the write data to the first encoding circuit,
the first channel switching circuit is further configured to feed back the first parity data and the second parity data to the first encoding circuit,
the first encoding circuit to generate third transient data according to the write data, the first parity data, the second parity data, the sixth sub-matrix, and the seventh sub-matrix,
the second channel switching circuit is used for providing the third transient data to the second encoding circuit, and
the second encoding circuit is configured to generate the third parity data according to the third transient data and the eighth sub-matrix.
23. The memory control circuit cell of claim 22, wherein the first encoding circuit comprises:
a first matrix operation circuit connected to the first channel switching circuit; and
an addition circuit connected to the first matrix operation circuit and the second channel switching circuit,
in the third encoding operation, the first matrix operation circuit is configured to generate third sub-transient data according to the write data and the sixth sub-matrix and fourth sub-transient data according to the first parity data, the second parity data and the seventh sub-matrix, and
the adder circuit is configured to generate the third transient data according to the third sub-transient data and the fourth sub-transient data.
24. The memory control circuit cell of claim 23, wherein the first encoding circuit further comprises:
a third channel switching circuit connected between the first matrix operation circuit and the addition circuit,
in the third encoding operation, the third channel switching circuit is to provide the third sub-transient data and the fourth sub-transient data to the summing circuit.
CN202210240997.2A 2022-03-10 2022-03-10 Coding control method, memory storage device and memory control circuit unit Pending CN114613420A (en)

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Application Number Priority Date Filing Date Title
CN202210240997.2A CN114613420A (en) 2022-03-10 2022-03-10 Coding control method, memory storage device and memory control circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210240997.2A CN114613420A (en) 2022-03-10 2022-03-10 Coding control method, memory storage device and memory control circuit unit

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