CN114595102A

CN114595102A - Authentication method, electronic device, and storage medium

Info

Publication number: CN114595102A
Application number: CN202210230179.4A
Authority: CN
Inventors: 赵雅
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-03-10
Filing date: 2022-03-10
Publication date: 2022-06-07

Abstract

The present disclosure provides a verification method, an electronic device, and a storage medium, the verification method including: providing a plurality of chipsets, wherein an interconnection module of each chipset comprises at least one of a physical layer, a link layer and a network layer; selecting a first chipset from a plurality of chipsets; selecting a second chipset from the plurality of chipsets, the second chipset comprising a select interconnect layer and the select interconnect layer being one of a physical layer and a link layer; selecting a first interconnect module from at least one interconnect module in a first chipset; selecting one of a physical layer and a link layer of the first interconnection module as a target interconnection layer; the first interconnect module and the selective interconnect layer are interconnected, whereby the selective interconnect layer provides a verification path such that the target interconnect layer transmits a verification stimulus or verification output to verify the first chipset. The verification method adopts layered modeling verification, so that the scale of a verification platform can be reduced, and the simulation speed is increased.

Description

Authentication method, electronic device, and storage medium

Technical Field

Embodiments of the present disclosure relate to a verification method, an electronic device, and a storage medium.

Background

A System on Chip (SoC) is also called a System on Chip. As process technology advances, a large SoC is split into different chip sets (chiplets), for example, according to functions. These chip sets are fabricated as individual dies (Die) using different process flow sheets, and these dies are packaged together into a system-on-a-chip. The importance of interconnection between different chipsets is gradually highlighted, interconnection technology is also in updating iteration, and interconnection verification is increasingly important. However, a chip set is large in scale and slow in simulation, different products have different chip set combination schemes, and verification needs to cover different product combinations, and due to the reasons, interactive verification among the chip sets is more and more complex and difficult.

Disclosure of Invention

At least one embodiment of the present disclosure provides a verification method, including: providing a plurality of chipsets, wherein each of the plurality of chipsets respectively comprises at least one interconnect module, each of the at least one interconnect module comprising at least one of a physical layer, a link layer, and a network layer; selecting a first chipset from the plurality of chipsets, wherein the first chipset is a chipset to be tested; selecting a second chipset from the plurality of chipsets, wherein the interconnect module of the second chipset includes a select interconnect layer configured as one of a physical layer and a link layer of the interconnect module of the second chipset; selecting a first interconnect module from at least one interconnect module in the first chipset; selecting one of a physical layer and a link layer of the first interconnect module as a target interconnect layer; interconnecting a first interconnect module of the first chipset and a select interconnect layer of the second chipset, whereby the select interconnect layer in the second chipset provides a verification path such that the target interconnect layer of the first chipset transmits a verification stimulus or verification output to verify the first chipset.

For example, at least one embodiment of the present disclosure provides a verification method further including: providing the verification stimulus to the target interconnect layer and receiving the verification output from the target interconnect layer through a selected interconnect layer in the second chipset using a verification system, or receiving the verification stimulus from the target interconnect layer and providing the verification output to the target interconnect layer through a selected interconnect layer in the second chipset using a verification system.

For example, in an authentication method provided in at least one embodiment of the present disclosure, the authentication system includes a universal authentication module.

For example, in an authentication method provided in at least one embodiment of the present disclosure, the selective interconnection layer of the second chipset is directly interconnected with the authentication system.

For example, in a verification method provided in at least one embodiment of the present disclosure, selecting one of a physical layer and a link layer of the first interconnect module as a target interconnect layer includes: selecting a link layer of the first interconnect module as the target interconnect layer.

For example, in a verification method provided in at least one embodiment of the present disclosure, interconnecting a first interconnect module of the first chipset and a selected interconnect layer of the second chipset includes: in response to the select interconnect layer of the second chipset being a link layer, directly interconnecting the link layer of the second chipset with the link layer of the first interconnect module and disconnecting the link layer of the first interconnect module from the physical layer of the first interconnect module.

For example, in an authentication method provided in at least one embodiment of the present disclosure, a link layer of the second chipset is directly interconnected with the authentication system.

For example, in a verification method provided in at least one embodiment of the present disclosure, selecting one of a physical layer and a link layer of the first interconnect module as a target interconnect layer includes: selecting a physical layer of the first interconnect module as the target interconnect layer.

For example, in a verification method provided in at least one embodiment of the present disclosure, interconnecting a first interconnect module of the first chipset and a selected interconnect layer of the second chipset includes: in response to the selection of the interconnect layer of the second chipset to be a physical layer, the second chipset including a physical layer and directly interconnecting the physical layer of the second chipset with the physical layer of the first interconnect module and the authentication system, respectively; in response to the second chipset selecting the interconnect layer to be a link layer, the second chipset includes a physical layer and a link layer, and the second chipset further includes a physical layer interconnecting the physical layer of the second chipset with the link layer of the second chipset and directly interconnecting the physical layer of the second chipset with the physical layer of the first interconnect module.

For example, in a verification method provided in at least one embodiment of the present disclosure, in response to the selection of the interconnect layer of the second chipset as a physical layer, the physical layer of the second chipset is directly interconnected with the verification system; in response to the selection of the interconnect layer of the second chipset to be a link layer, the link layer of the second chipset directly interconnects with the authentication system.

For example, in a verification method provided in at least one embodiment of the present disclosure, providing the verification stimulus to the target interconnect layer and receiving the verification output from the target interconnect layer through a selected interconnect layer in the second chipset using a verification system includes: the verification system sending the verification stimulus to the select interconnect layer; the selected interconnection layer provides the verification excitation for the target interconnection layer and transmits the verification excitation to pass through a network layer of the first chipset, so that the first chipset obtains a corresponding verification output according to the verification excitation; the network layer of the first chipset obtains the verification output and sends the verification output to the selected interconnection layer through the target interconnection layer; the verification system receives the verification output from the selective interconnect layer.

For example, in a verification method provided in at least one embodiment of the present disclosure, receiving the verification stimulus from the target interconnect layer and providing the verification output to the target interconnect layer through a selected interconnect layer in the second chipset using a verification system includes: transmitting, by a network layer of the first chipset, the verification stimulus provided by the first chipset to the target interconnect layer; the target interconnect layer sending the verification stimulus to the select interconnect layer, and the verification system receiving the verification stimulus from the select interconnect layer to obtain a corresponding verification output; the selected interconnect layer obtaining the verification output from the verification system and sending the verification output to the target interconnect layer; the target interconnection layer receives the verification output and transmits the verification output to pass through the network layer of the first chipset

For example, in a verification method provided in at least one embodiment of the present disclosure, selecting a second chipset from the plurality of chipsets includes: selecting at least one peer chipset from the plurality of chipsets configured to be interconnected with the first chipset; selecting the second chipset from the at least one peer chipset.

For example, at least one embodiment of the present disclosure provides a verification method further including: selecting at least one third chipset from the at least one peer chipset; selecting a second interconnect module from at least one interconnect module in the first chipset; interconnecting a physical layer of a second interconnect module of the first chipset with a physical layer of a corresponding third chipset of the at least one third chipset.

For example, at least one embodiment of the present disclosure provides a verification method further including: in response to the at least one third chipset comprising a plurality of third chipset, serially interconnecting each third chipset of the at least one third chipset.

For example, in an authentication method provided in at least one embodiment of the present disclosure, the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are homogeneous chipsets.

At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein the memory has stored thereon a computer program which, when executed by the processor, implements the authentication method as defined in any one of the above.

At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium has a computer program stored therein, and the computer program, when executed by a processor, implements the authentication method as in any of the above examples.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of an interconnection between two chipset groups;

fig. 2 is a flow chart of a verification method provided by some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of two interchip verifications with a target interconnect layer being a link layer and a selected interconnect layer being the link layer according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of verification between two chipsets with a target interconnect layer as a physical layer and an interconnect layer selected as the physical layer according to some embodiments of the disclosure;

FIG. 5 is a schematic diagram of an inter-chip group verification method with a physical interconnect layer as a target interconnect layer and a link layer as a selected interconnect layer according to some embodiments of the disclosure;

fig. 6 is a flowchart provided by some embodiments of the present disclosure with respect to step S3 in fig. 2;

FIG. 7 is a flow chart of a verification method provided in further embodiments of the present disclosure;

FIG. 8 is a schematic diagram of three interchip verifications with a target interconnect layer being a link layer and a selected interconnect layer being a link layer according to some embodiments of the present disclosure;

FIG. 9 is a schematic diagram of three interchip verifications with a physical interconnect layer as a target interconnect layer and a link layer as a selected interconnect layer according to some embodiments of the present disclosure; and

fig. 10 is a block diagram of an electronic device provided in some embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The use of the terms "a" and "an" or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Flow charts are used in the disclosed embodiments to illustrate the steps of a method according to an embodiment of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or steps may be removed from the processes.

The inventor of the present disclosure finds that different chipsets can be combined according to different product requirements, and different verification platforms need to be set up for different product schemes. For example, a product of two chipsets, instantiates two real chipsets for interconnect verification; and in the product of four chipsets, four real chipsets are instantiated for interconnection verification, and the like.

For example, as shown in fig. 1, two chipsets that need to be interconnected are denoted as chipset 001 and chipset 002, and chipset 001 and chipset 002 may communicate with each other and are peer chipsets. The interconnection module of chipset 001 includes physical layer 101, link layer 102, and network layer 103 interconnected in sequence, and the interconnection module of chipset 002 also includes physical layer 201, link layer 202, and network layer 203 interconnected in sequence.

For the physical layer in the network protocol hierarchy, it provides a virtual bit pipe that carries a bit stream (bit sequence) between any pair of nodes connected by a physical communication channel. At the transmitting end, it converts the received bit stream into a signal suitable for transmission over the physical channel, and at the receiving end, restores the signal into the transmitted bit stream. The physical layer provides only the original digital bit stream transport service and does not perform error protection, e.g., the physical layer may be denoted as the first layer. For example, physical communication channels include, but are not limited to, twisted pair, coaxial cable, fiber optic cable, and radio channels.

In the network protocol layering, a transport layer, a session layer, a presentation layer, and an application layer are further included above the network layer, and are not described in detail here.

For the link layer of the network protocol hierarchy, it is responsible for the transmission of data blocks (frames) and performs the necessary synchronization control, error control and flow control. The upper layer of the data link layer may consider the transmission on the link to be error-free due to the services of the data link layer, e.g., the link layer may be denoted as the second layer and the link layer may be denoted as the upper layer of the physical layer.

For the network layer of the network protocol layering, which is between the transmission layer and the data link layer, the data communication in the network is further managed on the transmission function of the data frame between two adjacent nodes provided by the data link layer, the data is transmitted from the source end to the destination end through a plurality of intermediate nodes, and the most basic end-to-end data transmission service is provided for the transmission layer. For example, the network layer may be denoted as a third layer, and the network layer may be denoted as an upper layer of the link layer.

For example, as shown in fig. 1, a link layer of any one of the chipset 001 and the chipset 002 receives data provided by an upper network layer, and provides the data to a lower physical layer after performing corresponding processing, the physical layer transmits the data to a physical layer of an opposite chipset after performing corresponding processing, and in the opposite chipset, the data sequentially passes through corresponding processing of the physical layer, the link layer, and the network layer, so as to implement interconnection and communication between the chipset 001 and the chipset 002.

The inventors of the present disclosure found that the following problems exist in the method of verifying the above chipset: firstly, for the same chipset, a plurality of combinations needing verification are provided, and the verification platform is large in scale; secondly, if a real chipset is used, the verification platform has large scale, low simulation speed and long time consumption; thirdly, for the interconnection of heterogeneous chipsets, due to the fact that development cycles of different chipsets are different, proper chipsets are not necessarily interconnected, and therefore the interconnection verification of chipsets is not facilitated.

To this end, at least one embodiment of the present disclosure provides a verification method, including: providing a plurality of chipsets, wherein each of the plurality of chipsets respectively comprises at least one interconnection module, each of the at least one interconnection module comprising at least one of a physical layer, a link layer, and a network layer; selecting a first chipset from a plurality of chipsets, wherein the first chipset is a chipset to be tested; selecting a second chipset from the plurality of chipsets, wherein the interconnect module of the second chipset includes a select interconnect layer configured as one of a physical layer and a link layer of the interconnect module of the second chipset; selecting a first interconnect module from at least one interconnect module in a first chipset; selecting one of a physical layer and a link layer of the first interconnection module as a target interconnection layer; the first interconnect module of the first chipset and the selective interconnect layer of the second chipset are interconnected, whereby the selective interconnect layer in the second chipset provides a verification path such that the target interconnect layer of the first chipset transmits a verification stimulus or verification output to verify the first chipset.

The above embodiments of the present disclosure adopt layered modeling verification for different functions of a chipset, and model at least part of an interconnect module (for example, part of RTL (register transfer level) codes, for example, RTL codes only used for implementing a network layer, a link layer, or a physical layer) of an opposite-end chipset of a chipset to be tested according to different interconnect levels to interconnect with the chipset, so as to achieve the purpose of verifying different functions, and also use codes of part of interconnect levels of the opposite-end chipset without waiting for the completion of overall verification of the opposite-end chipset, thereby solving the problem caused by the development cycle of different chipsets in the verification process.

The verification method of the embodiment of the disclosure can also use the targeted RTL code for different verification scenes or verification targets, so that the scale of the verification platform is greatly reduced, and the simulation speed can also be greatly increased.

Fig. 2 is a flowchart of a verification method according to some embodiments of the present disclosure.

For example, as shown in fig. 2, a verification method provided by at least one embodiment of the present disclosure includes steps S1 to S6.

Step S1, providing a plurality of chipsets, wherein each of the chipsets comprises at least one interconnection module, and each interconnection module of the at least one interconnection module of each chipset comprises at least one of a physical layer, a link layer and a network layer.

Step S2, select a first chipset from the plurality of chipsets, where the first chipset is a chipset to be tested.

Step S3, selecting a second chipset from the plurality of chipsets, wherein the interconnect module of the second chipset includes a selective interconnect layer configured as one of a physical layer and a link layer of the interconnect module of the second chipset.

Step S4, selecting a first interconnect module from at least one interconnect module in the first chipset.

And step S5, selecting one of the physical layer and the link layer of the first interconnection module as a target interconnection layer.

Step S6, interconnecting the first interconnect module of the first chipset and the selective interconnect layer of the second chipset, whereby the selective interconnect layer in the second chipset provides a verification path, such that the target interconnect layer of the first chipset transmits a verification stimulus or verification output to verify the first chipset.

In the at least one embodiment of the present disclosure, hierarchical modeling verification is adopted for different functions of a chipset, and at least part of an interconnection module of an opposite terminal chipset of the tested chipset is modeled according to different interconnection levels to interconnect with the tested chipset, so that not only can the purpose of verifying different functions be achieved, but also the whole verification of the opposite terminal chipset is not required to be waited for to complete by using codes of part of interconnection levels of the opposite terminal chipset, thereby solving the problem caused by the development cycle of different chipsets in the verification process. The verification method of the embodiment of the disclosure can also use targeted codes for different functions, so that the scale of the verification platform is greatly reduced, and the simulation speed can also be greatly increased.

In some examples, the verification method of embodiments of the present disclosure further comprises the steps or processes of: a verification system is used to provide a verification stimulus to or receive a verification output from a target interconnect layer through a selected interconnect layer in the second chipset. Therefore, the verification system and the plurality of chipsets can realize the verification of different verification scenes.

In some examples, the Verification system includes a universal Verification module, for example, the universal Verification method Verification module is a uvm (universal Verification method) Verification module. For example, the UVM verification module is a verification platform development framework mainly based on a System Verilog class library, and a functional verification environment with a standardized hierarchical structure and interface, that is, a UVM environment, can be constructed by using reusable components of the UVM verification module. The UVM verification environment specifies the basic classes (i.e., reusable components) in the UVM, such as sequence editors (sequencers), monitors (monitors), etc., and communication interfaces. The verifier can extend the required classes based on the basic classes, and then connect the communication interfaces of the classes by using the communication statements of the UVM standard.

It should be noted that, in the present disclosure, since the specific composition of the verification system and the content of how to perform verification by using the verification system are not limited, details thereof are not described herein.

At least one embodiment of the disclosure realizes verification by using a UVM verification system, and has the advantages of high reusability, strong flexibility of the verification method, convenient use and high efficiency.

Fig. 3 is a schematic diagram of two interchip verifications with a target interconnect layer being a link layer and a selected interconnect layer being the link layer according to some embodiments of the disclosure. Fig. 4 is a schematic diagram of verification between two chipsets, where a target interconnect layer is a physical layer and an interconnect layer is selected as the physical layer according to some embodiments of the disclosure. Fig. 5 is a schematic diagram of two interchip verifications with a physical interconnect layer as a target interconnect layer and a link layer as a selected interconnect layer according to some embodiments of the disclosure. The illustrated embodiments will be described in detail below.

In some examples, for step S1, each chipset includes at least one interconnect module in a number equal to the number of peer chipsets to be interconnect verified by the chipset under test. For example, the number of interconnect modules included in a chipset may be one, such as one interconnect module 1110 of chipset 1100 shown in FIG. 3. As another example, the chipset may include a plurality of interconnect modules, for example, 2 or more, and the chipset 4100 shown in fig. 8 (see below) has two interconnect modules, i.e., an interconnect module 4110 and an interconnect module 4120. This is merely an example and is not a limitation on the embodiments of the present disclosure, which is not limited thereby.

It should be noted that, in the embodiments of the present disclosure, the peer chipset may not only represent a chipset directly interconnected with a chipset to be tested, such as peer chipset 1200 corresponding to chipset 1100 in fig. 3, peer chipset 2200 corresponding to chipset 2100 in fig. 4, peer chipset 3200 corresponding to chipset 3100 in fig. 5, peer chipset 4400 corresponding to chipset 4100 in fig. 8 (see below), and peer chipset 5400 corresponding to chipset 5100 in fig. 9 (see below), but also represent a chipset indirectly interconnected with a chipset to be tested, such as another chipset (not shown) connected with the chipset to be tested through at least one chipset in the middle.

For example, for step S1, the interconnect module of some of the plurality of chipsets may include three levels, physical, link and network, such as the interconnect module 2110 of the chipset 2100 (first chipset) shown in fig. 4 including a physical layer 2111, a link layer 2112 and a network layer 2113 and the interconnect module 3110 of the chipset 3100 (first chipset) shown in fig. 5 including a physical layer 3111, a link layer 3112 and a network layer 3113.

For another example, for step S1, the interconnect module of some of the plurality of chipsets may also include one of a physical layer, a link layer, and a network layer, the interconnect module 1210 of chipset 1200 (i.e., the second chipset) includes link layer 1212, as shown in fig. 3, or the interconnect module 2210 of chipset 2200 (i.e., the second chipset) includes physical layer 2211, as shown in fig. 4.

For another example, with respect to step S1, the interconnection module of some of the plurality of chipsets may further include two of a physical layer, a link layer, and a network layer, such as the chipset 3200 (second chipset) interconnection module 3210 shown in fig. 5 includes a physical layer 3211 and a link layer 3212.

Therefore, the embodiment of the present disclosure is not limited to this, and a targeted hierarchical code may be selected for use with respect to different verification targets, which is not described herein again.

In some examples, for step S2, the first chipset is an RTL module to be verified, which may also be referred to as a Device Under Test (DUT), such as the chipset 1100 shown in fig. 3, the chipset 2100 shown in fig. 4, the chipset 3100 shown in fig. 5, the chipset 4100 shown in fig. 8, and the chipset 5100 shown in fig. 9.

In some examples, for step S3, the second chipset is a peer chipset relative to the first chipset to be tested in the verification process, such as chipset 1200 shown in fig. 3, chipset 2200 shown in fig. 4, and chipset 3200 shown in fig. 5. The second chipset selects a transmission hierarchy according to different verification targets, hierarchically models the second chipset, and selects a hierarchy required for verification among a plurality of interconnection layers obtained by hierarchical modeling, so that the selected hierarchy (for example, using a corresponding RTL code) can be used to implement verification of the functions related to the first chipset, and at least part of components of the second chipset other than the selected hierarchy can be temporarily disregarded.

In some examples, the interconnect module of the second chipset may include at least some of a physical layer, a link layer, and a network layer, for example, the interconnect module of the second chipset includes a link layer (e.g., temporarily lacks at least some other layers of the physical layer, the network layer, etc.), or the interconnect module of the second chipset includes a physical layer and a link layer (e.g., temporarily lacks at least some other layers of the network layer, etc.), which may be adjusted accordingly according to different verification targets in practical applications, and embodiments of the present disclosure are not limited thereto.

In some examples, for step S3, the second chipset and the first chipset may be heterogeneous chipsets or homogeneous chipsets.

In some examples, for step S3, the select interconnect layer of the second chipset may be a link layer. In other examples, for step S3, the selected interconnect layer of the second chipset may also be a physical layer. This is merely exemplary and not a limitation of the present disclosure, and may be adjusted accordingly according to different verification objectives.

In some examples, for step S4, the first interconnect module selected from the first chipset is one of the interconnect modules in the first chipset used for interconnect verification with the second chipset. For example, what is used for performing interconnect verification with the chipset 1200 in the chipset 1100 in the example of fig. 3 is the interconnect module 1110, what is used for performing interconnect verification with the chipset 2200 in the chipset 2100 in the example of fig. 4 is the interconnect module 2110, what is used for performing interconnect verification with the chipset 3200 in the chipset 3100 in the example of fig. 5 is the interconnect module 3110, that is, the interconnect module 1110, the interconnect module 2110 and the interconnect module 3110 are the first interconnect modules of the corresponding examples respectively.

In some examples, for step S5, selecting one of a physical layer and a link layer of the first interconnect module as the target interconnect layer includes: the link layer of the first interconnect module is selected as the target interconnect layer. For example, when the target interconnect layer of the first chipset is the link layer of the first interconnect module, correspondingly, the selected interconnect layer of the second chipset is the link layer, as shown in fig. 3.

In other examples, for step S5, selecting one of a physical layer and a link layer of the first interconnect module as the target interconnect layer includes: the physical layer of the first interconnect module is selected as the target interconnect layer. For example, when the target interconnect layer of the first chipset is the physical layer of the first interconnect module, correspondingly, the selected interconnect layer of the second chipset may be the physical layer, as shown in fig. 4. For another example, when the target interconnect layer of the first chipset is the physical layer of the first interconnect module, the selected interconnect layer of the second chipset may also be the link layer, as shown in fig. 5.

Therefore, at least some embodiments of the disclosure select different layers of the opposite end chipset of the tested chipset to perform modeling to verify different functions aiming at different functions, thereby simplifying the complexity of the verification environment, greatly improving the simulation speed and saving the verification time. For example, based on the example of fig. 3, embodiments of the present disclosure may enable verification of functionality of the link layer and upper layers of the link layer. For another example, based on the examples of fig. 4 or 5, embodiments of the present disclosure may enable verification of the functionality of the physical layer and the upper layers of the physical layer.

It should be noted that, in the embodiments of the present disclosure, there is no limitation on the level modules included in the interconnection modules of the respective chipsets, which may be adjusted according to different protocol layers, for example, seven layers of the OSI reference model or a five-layer model of the internet or other models, and the embodiments of the present disclosure are not exhaustive and repeated here.

It should be further noted that the chipset and/or the interconnect module shown in the drawings of the embodiments of the present disclosure are also only a simple schematic diagram, and are not limited to the chipset and the interconnect module, for example, the first chipset may further include a master/slave device connected to the interconnect module and/or a module at a higher level in the interconnect module, which is not a key point in the description of the embodiments of the present disclosure, and is not repeated here.

In the present disclosure, the "target interconnect layer" refers to a layer in the first interconnect module of the first chipset for directly interconnecting with the interconnect module of the second chipset to implement verification of the function of the corresponding layer. In the present disclosure, "select interconnect layer" refers to a layer selected from the interconnect module of the second chipset for direct interconnection with the verification system according to the corresponding target interconnect layer.

For example, in the example of fig. 3, the first chipset is chipset 1100 and the first interconnect module of the first chipset is interconnect module 1110. The second chipset is chipset 1200, where chipset 1200 includes an interconnect module 1210. Interconnect module 1110 of chipset 1100 includes a physical layer 1111, a link layer 1112, and a network layer 1113. The interconnect module 1210 of the chipset 1200 includes a link layer 1212. The target interconnect layer of interconnect module 1110 of chipset 1100 is link layer 1112 and the select interconnect layer of interconnect module 1210 of chipset 1200 is link layer 1212.

For example, as shown in fig. 3, for step S6, interconnecting the first interconnect module of the first chipset and the selected interconnect layer of the second chipset, the following process or steps are included: the link layer 1212 of the chipset 1200 is directly interconnected with the link layer 1112 of the interconnect module 1110 and the link layer 1112 of the interconnect module 1110 is disconnected from the physical layer 1111 of the interconnect module 1110. The link layer 1212 in the chipset 1200 thus provides a verification path such that the link layer 1112 of the chipset 1100 transmits a verification stimulus or verification output to verify the chipset 1100. For example, in the example of fig. 3, link layer 1212 of chipset 1200 is directly interconnected with authentication system 1300.

Therefore, in the embodiment of the present disclosure, the link layer 1112 of the chipset 1100 is used as a target interconnection layer, so that verification of functions of the link layer and an upper layer of the link layer can be realized, and the link layer 1112 is disconnected from the physical layer 1111 and the link layer 1212 is directly interconnected with the link layer 1112, so that data transmission in the verification process is fast, and the verification speed is increased. In the case where the interconnection module 1210 of the chipset 1200 of the embodiment of the present disclosure includes a link layer, the amount of modeled code is small, which can simplify the complexity of the verification environment, increase the simulation speed, and save the verification time.

In some examples, a validation path is provided for link layer 1212 of chipset 1200 in the example of fig. 3, including: when chipset 1100 is the recipient, link layer 1212 of chipset 1200 provides verification stimuli to link layer 1112 of chipset 1100 and link layer 1212 of chipset 1200 receives verification outputs sent by link layer 1112 of chipset 1100.

For example, when the chipset 1100 is used as a receiving party, the authentication system 1300 sends an authentication stimulus to the link layer 1212 of the chipset 1200, the link layer 1212 provides the authentication stimulus to the link layer 1112 of the chipset 1100 and transmits the authentication stimulus to the network layer 1113 of the chipset 1100, the chipset 1100 performs corresponding processing according to the authentication stimulus and provides a corresponding authentication output (for example, also referred to as a response signal or a response signal), the authentication output is provided to the network layer 1113 of the chipset 1100 and transmitted to the link layer 1112 of the chipset 1100, and the link layer 1212 of the chipset 1200 receives the authentication output from the link layer 1112 of the chipset 1100 and transmits the authentication output to the authentication system 1300 to obtain an authentication result, thereby implementing authentication of the chipset 1100.

It should be noted that, for the link layer 1212 of the chipset 1200 in the example of fig. 3 to provide the authentication path, the embodiments of the disclosure are not limited to the case that the chipset 1100 may serve as the receiver, and may also include the case that the chipset 1100 serves as the sender.

For example, when chipset 1100 is acting as the sender, link layer 1212 of chipset 1200 receives the verification stimulus sent by link layer 1112 of chipset 1100 and link layer 1212 of chipset 1200 provides the verification output to link layer 1112 of chipset 1100.

For example, when the chipset 1100 is used as a sender, the network layer 1113 of the chipset 1100 transmits the verification stimulus provided by the chipset 1100 to the link layer 1112 of the chipset 1100, the link layer 1112 of the chipset 1100 sends the verification stimulus to the link layer 1212 of the chipset 1200, and the verification system 1300 receives the verification stimulus from the link layer 1212 of the chipset 1200 and obtains a corresponding verification output according to the verification stimulus. The link layer 1212 of the chipset 1200 obtains the authentication output from the authentication system 1300 and sends the authentication output to the link layer 1112 of the chipset 1100, and the link layer 1112 of the chipset 1100 receives the authentication output sent by the link layer 1212 of the chipset 1200 and transmits the authentication output through the network layer 1113 of the chipset 1100 to implement authentication of the chipset 1100.

It should be noted that, since the specific components of the verification system and the details of how to perform verification by using the verification system are not important to describe the embodiments of the present disclosure, the embodiments of the present disclosure do not describe any specific verification process again.

For example, in the example of fig. 4, the first chipset is chipset 2100 and the first interconnect module of the first chipset is interconnect module 2110. The second chipset is a chipset 2200, which chipset 2200 includes an interconnect module 2210. The interconnect module 2110 of chipset 2100 includes a physical layer 2111, a link layer 2112, and a network layer 2113. Interconnect module 2210 of chipset 2200 includes a physical layer 2211. The target interconnect layer of the interconnect module 2110 of the chipset 2100 is physical layer 2111 and the select interconnect layer of the interconnect module 2210 of the chipset 2200 is physical layer 2211.

For example, as shown in fig. 4, for step S6, interconnecting the first interconnection module of the first chipset and the selected interconnection layer of the second chipset, the following process or steps are included: physical layer 2211 of chipset 2200 is directly interconnected with physical layer 2111 of interconnect module 2110. Thus, the physical layer 211 in the chipset 2200 provides a verification path such that the physical layer 2111 of the chipset 2100 transmits a verification stimulus or verification output to verify the chipset 2100. For example, in the example of FIG. 4, physical layer 2211 of chipset 2200 is directly interconnected with verification system 2300.

Thus, embodiments of the present disclosure may implement verification of the functions of the physical layer and the upper layers of the physical layer, with the physical layer 2111 of the chipset 2100 as the target interconnect layer. In the case where the interconnect module 2210 of the chipset 2200 of the present disclosure includes a physical layer, the amount of code modeled is small, which can simplify the complexity of the verification environment, increase the simulation speed, and save the verification time.

In some examples, a validation path is provided for physical layer 2211 of chipset 2200 in the example of fig. 4, including: when chipset 2100 is the recipient, physical layer 2211 of chipset 2200 provides verification stimuli to physical layer 2111 of chipset 2100 or physical layer 2211 of chipset 2200 receives verification output sent by physical layer 2111 of chipset 2100.

It should be noted that, for the verification case in which the chipset 2100 serves as the receiver and the chipset 2100 serves as the sender in the example of fig. 4, reference may be made to the description above regarding the example of fig. 3, and details are not repeated here.

For example, in the example of fig. 5, the first chipset is chipset 3100 and the first interconnect module of the first chipset is interconnect module 3110. The second chipset, which is (one of) peer chipsets, is chipset 3200, chipset 3200 includes an interconnect module 3210. The interconnect module 3110 of the chipset 3100 includes a physical layer 3111, a link layer 3112, and a network layer 3113. Interconnect module 3210 of chipset 3200 includes a physical layer 3211 and a link layer 3212. The target interconnect layer of interconnect module 3110 of chipset 3100 is physical layer 3111 and the select interconnect layer of interconnect module 3210 of chipset 3200 is link layer 3212. For example, chipset 3100 and chipset 3200 may be part of the same system chip.

For example, as shown in fig. 5, for step S6, interconnecting the first interconnect module of the first chipset and the selected interconnect layer of the second chipset, the following process or steps are included: physical layer 3211 of chipset 3200 is interconnected with link layer 3212 of chipset 3200, and physical layer 3211 of chipset 3200 is directly interconnected with physical layer 3111 of interconnect module 3110 of chipset 3100. The link layer 3212 in the chipset 3200 thus provides a verification path such that the link layer 3112 of the chipset 3100 transmits a verification stimulus or verification output to verify the chipset 3100. For example, in the example of fig. 5, the link layer 3212 of the chipset 3200 is directly interconnected with the authentication system 3300.

Thus, embodiments of the present disclosure may implement verification of the functions of the physical layer and the upper layers of the physical layer, with the physical layer 3111 of the chipset 3100 as the target interconnect layer. In the case where the interconnection module 3210 of the chipset 3200 of the embodiment of the present disclosure includes a physical layer and a link layer, the amount of code to be modeled is reduced, which can simplify the complexity of the verification environment, increase the simulation speed, and save the verification time.

In some examples, an authentication path is provided for the link layer 3212 of the chipset 3200 in the example of fig. 5, including: with chipset 3100 acting as the recipient, link layer 3212 of chipset 3200 provides an authentication stimulus to physical layer 3111 of chipset 3100 through physical layer 3211 or link layer 3212 of chipset 3200 receives an authentication output transmitted by physical layer 3111 of chipset 3100 through physical layer 3211.

It should be noted that, for the verification case in which the chipset 3100 serves as a receiver and the chipset 3100 serves as a sender in the example of fig. 5, reference may be made to the description above regarding the example of fig. 3, and details are not repeated here.

Fig. 6 is a flowchart of step S3 in fig. 2 according to some embodiments of the present disclosure.

For example, as shown in fig. 6, one example of step S3 includes step S31 and step S32.

Step S31, selecting at least one peer chipset from the plurality of chipsets configured to be interconnected with the first chipset.

Step S32, selecting a second chipset from the at least one peer chipset.

Therefore, the embodiment of the disclosure is suitable for interconnection verification among any number of chip groups, can perform layered modeling according to different verification targets to verify functions of different layers, and has good portability and universality.

For example, in step S31, the number of peer chipsets may be one, for example, this peer chipset is the second chipset, and the verification method may implement the interconnection verification between the two chipsets. For another example, in step S31, if the number of peer chipsets may be multiple, for example, the second chipset is one of the multiple peer chipsets, the verification method may implement the verification of the interconnection between more than three chipsets, for example, as shown in fig. 8 and fig. 9 below.

It should be noted that, in the embodiment of the present disclosure, the number of opposite end chip sets corresponding to the first chip set is not limited, and may be freely adjusted according to an actual situation, which is not described herein again.

Fig. 7 is a flowchart of a verification method according to further embodiments of the present disclosure. Fig. 8 is a schematic diagram of three interchip verifications with a target interconnect layer being a link layer and a selected interconnect layer being the link layer according to some embodiments of the disclosure. Fig. 9 is a schematic diagram of three interchip verifications with a physical layer as a target interconnect layer and a link layer as a selected interconnect layer according to some embodiments of the present disclosure.

For example, as shown in fig. 7, the verification method provided in some embodiments of the present disclosure may further include steps S71 to S73.

Step S71, selecting at least one third chipset from at least one peer chipset.

Step S72, selecting a second interconnect module from at least one interconnect module in the first chipset.

Step S73, interconnecting the physical layer of the second interconnection module of the first chipset with the physical layer of a corresponding third chipset in the at least one third chipset.

Therefore, the embodiment of the disclosure is not only suitable for the interconnection verification between two chip groups, but also suitable for the interconnection verification between three or more chip groups, can cover more verification scenes, and is more comprehensive in verification.

In the above embodiments of the present disclosure, the third chipset is different from the second chipset. For example, in step S71, the number of the third chipset may be one, such as the chipset 4400 shown in fig. 8 and the chipset 5400 shown in fig. 9, and the verification method may achieve the verification of the interconnection between the three chipsets. For another example, the number of the third chipset may be multiple, and the verification method may implement the verification of the interconnection between four or more chipsets. It should be noted that, the number of the third chip sets is not limited in the embodiments of the present disclosure, and may be freely adjusted according to actual situations, which is not described herein again.

For example, in step S72, when the number of interconnect modules in the first chipset is equal to or greater than 2, the interconnect module of the first chipset includes, in addition to the first interconnect module, another interconnect module for performing interconnect verification with another chipset (e.g., a third chipset), that is, a second interconnect module, for example, in the embodiment shown in fig. 8, the second interconnect module is the interconnect module 4410 and the third chipset corresponding to the interconnect module 4410 is the chipset 4400, and in the embodiment shown in fig. 9, the second interconnect module is the interconnect module 5410 and the third chipset corresponding to the interconnect module 5410 is the chipset 5400.

In some examples, the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are homogeneous chipsets. For example, chipset 4200 and chipset 4100 shown in FIG. 8 may be heterogeneous chipsets and chipset 4400 and chipset 4100 may be homogeneous chipsets. For example, the chipset 5200 and the chipset 5100 shown in fig. 9 are heterogeneous chipsets, and the chipset 5400 and the chipset 5100 are homogeneous chipsets. In other examples, the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are heterogeneous chipsets. Therefore, the embodiment of the disclosure can realize the interconnection verification among more than three chip groups, can cover more verification scenes, and has high simulation speed.

In some examples, where the at least one third chipset described above includes a plurality of third chipsets, each of the at least one third chipsets may be interconnected serially. Therefore, the embodiment of the disclosure can realize interconnection verification among a plurality of chip groups, can cover more verification scenes, and has higher simulation speed. This is, of course, exemplary and not a limitation of the disclosure.

It should be noted that, for the verification of the interconnection between three chipsets or the verification of the interconnection between more chipsets, the disclosure is not limited to the above-described examples, for example, a verification scheme of physical layer or link layer modeling may be flexibly used for heterogeneous or homogeneous chipsets, and details are not described here.

For example, in the example of fig. 8, the first chipset is chipset 4100, the first interconnect module of the first chipset is interconnect module 4110, and the second interconnect module of the first chipset is interconnect module 4120. The second chipset, which is one of the peer chipsets, is chipset 4200, chipset 4200 includes an interconnection module 4210. The interconnect module 4110 of the chipset 4100 includes a physical layer 4111, a link layer 4112, and a network layer 4113. The interconnect module 4120 of the chipset 4100 includes a physical layer 4121, a link layer 4122, and a network layer 4113. Interconnect module 4210 of chipset 4200 includes a link layer 4212. The target interconnect layer of the interconnect module 4110 of the chipset 4100 is the link layer 4112, and the select interconnect layer of the interconnect module 4210 of the chipset 4200 is the link layer 4212. The third chipset is chipset 4400, and interconnect module 4410 of chipset 4400 includes a physical layer 4411, a link layer 4412 and a network layer 4413.

For example, in the example of FIG. 8, physical layer 4121 of interconnect module 4120 of chipset 4100 is interconnected with physical layer 4411 of interconnect module 4410 of chipset 4400. For example, in the example of fig. 8, the link layer 4212 of the chipset 4200 directly interconnects with the link layer 4112 of the interconnect module 4110 and disconnects the link layer 4112 of the interconnect module 4110 from the physical layer 4111 of the interconnect module 4110. For example, in the example of fig. 8, link layer 4212 of chipset 4200 is directly interconnected with authentication system 4300.

For example, as shown in fig. 8, chipset 4200 and chipset 4100 are heterogeneous chipsets, chipset 4400 and chipset 4100 are homogeneous chipsets, chipset 4400 and chipset 4100 which are homogeneous chipsets are interconnected using a complete RTL, chipset 4200 which is heterogeneous chipset with chipset 4100 is interconnected using link layer 4212 and chipset 4100, and verification system 4300 interacts with link layer 4212 of chipset 4200, thus implementing verification of chipset 4100.

Therefore, in the example of fig. 8 of the present disclosure, the link layer 4112 of the chipset 4100 is used as a target interconnection layer, verification of functions of the link layer and the upper layer of the link layer may also be implemented, and the link layer 4112 is disconnected from the physical layer 4111 and the link layer 4212 is directly interconnected with the link layer 4112, so that data transmission in the verification process is fast, and the verification speed is accelerated. In the case that the interconnection module 4210 of the chipset 4200 of the embodiment of the present disclosure includes a link layer, the amount of modeled code is small, which may simplify the complexity of the verification environment, increase the simulation speed, and save the verification time.

For example, in the example of fig. 9, the first chipset is a chipset 5100, the first interconnect module of the first chipset is an interconnect module 5110, and the second interconnect module of the first chipset is an interconnect module 5120. The second chipset is chipset 5200, and chipset 5200 includes an interconnect module 5210. The interconnect module 5110 of the chipset 5100 includes a physical layer 5111, a link layer 5112, and a network layer 5113. The interconnect module 5120 of the chipset 5100 includes a physical layer 5121, a link layer 5122, and a network layer 5113. The interconnect module 5210 of the chipset 5200 includes a link layer 5212 and a physical layer 5211. The target interconnect layer of interconnect block 5110 of chipset 5100 is physical layer 5111 and the select interconnect layer of interconnect block 5210 of chipset 5200 is link layer 5212. The third chipset is chipset 5400, and the interconnect module 5410 of chipset 5400 includes a physical layer 5411, a link layer 5412, and a network layer 5413.

For example, in the example of FIG. 9, the physical layer 5121 of the interconnect module 5120 of the chipset 5100 is interconnected with the physical layer 5411 of the interconnect module 5410 of the chipset 5400. For example, in the example of fig. 9, physical layer 5211 of chipset 5200 is interconnected with link layer 5212 of chipset 5200, and physical layer 5211 of chipset 5200 is directly interconnected with physical layer 5111 of interconnect module 5110 of chipset 5100. For example, in the example of fig. 9, the link layer 5212 of the chipset 5200 is directly interconnected with the verification system 5300.

For example, as shown in fig. 9, the chipset 5200 and the chipset 5100 are heterogeneous chipsets, and the chipset 5400 and the chipset 5100 are homogeneous chipsets, the chipset 5400 and the chipset 5100 which are homogeneous chipsets are interconnected by using a complete design, and the chipset 5200 which is heterogeneous chipset with the chipset 5100 adopts a link layer 5212 and a physical layer 5211 to realize interconnection with the chipset 5100, and the authentication system 5300 interacts with the link layer 5212 of the chipset 5200, so as to realize authentication of the chipset 5100.

Thus, the example of fig. 9 of the present disclosure may implement verification of the functionality of the physical layer and layers above the physical layer, using physical layer 5111 of chipset 5100 as the target interconnect layer. In the case where the interconnection module 5210 of the chipset 5200 of the present disclosure includes a physical layer and a link layer, the amount of code to be modeled is reduced, which can simplify the complexity of the verification environment, increase the simulation speed, and save the verification time.

It should be noted that, for the verification between three interchip groups, where the target interconnect layer is a physical layer and the interconnect layer is selected to be a link layer, not only the implementation can be realized by designing the interconnect module 5210 of the chipset 5200 to include the physical layer and the link layer in the example of fig. 9, but also the verification of the functions of the physical layer and the upper layer of the physical layer can be realized by designing the interconnect module 5210 of the chipset 5200 to include only the physical layer and directly connecting the physical layer of the interconnect module 5210 with the verification system, which may specifically refer to the description related to the example of fig. 5 and is not described herein again.

As described above, the verification method provided by some embodiments of the present disclosure may use a partial model (e.g., RTL model) of the peer chipset to model at different transmission levels to verify functions at different levels, which may simplify complexity of the verification environment, increase simulation speed, and save verification time. For example, for different architectures and verification platforms, one or a combination of several of the hierarchical modeling may be adopted, for example, the modeling may be performed at different levels such as a physical layer and a link layer, so as to achieve the purpose of verifying different functions, the scale of the verification platform may be greatly reduced, and the simulation speed may be greatly increased.

Fig. 10 is a schematic structural diagram of an electronic device according to at least one embodiment of the present disclosure, where the electronic device 600 includes a processor 610 and a memory 620, where the memory 620 stores a computer program, and when the computer program is executed by the processor 610, the verification method according to at least some embodiments of the present disclosure is implemented.

The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as notebook computers, tablet computers, and the like, and stationary terminals such as desktop computers and the like. The electronic device shown in fig. 10 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

For example, the processes described above with reference to the flowcharts may be implemented as computer software programs, according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the method illustrated by the flow chart. The computer program, when executed by a processor, performs the authentication method of an embodiment of the present disclosure.

It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In embodiments of the disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In embodiments of the present disclosure, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.

The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the verification method for specific functions and technical effects of the electronic device 600, and details are not described here.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A method of authentication, comprising:

providing a plurality of chipsets, wherein each of the plurality of chipsets respectively comprises at least one interconnect module, each of the at least one interconnect module comprising at least one of a physical layer, a link layer, and a network layer;

selecting a first chipset from the plurality of chipsets, wherein the first chipset is a chipset to be tested;

selecting a second chipset from the plurality of chipsets, wherein the interconnect module of the second chipset includes a select interconnect layer configured as one of a physical layer and a link layer of the interconnect module of the second chipset;

selecting a first interconnect module from at least one interconnect module in the first chipset;

selecting one of a physical layer and a link layer of the first interconnect module as a target interconnect layer;

interconnecting a first interconnect module of the first chipset and a select interconnect layer of the second chipset, whereby the select interconnect layer in the second chipset provides a verification path such that the target interconnect layer of the first chipset transmits a verification stimulus or verification output to verify the first chipset.

2. The authentication method of claim 1, further comprising:

providing the verification stimulus to the target interconnect layer and receiving the verification output from the target interconnect layer through a select interconnect layer in the second chipset using a verification system, or,

receiving, using a verification system, the verification stimulus from the target interconnect layer through a select interconnect layer in the second chipset and providing the verification output to the target interconnect layer.

3. The authentication method of claim 2, wherein the authentication system comprises a generic authentication module.

4. The verification method of claim 2, wherein selecting one of a physical layer and a link layer of the first interconnect module as a target interconnect layer comprises:

selecting a link layer of the first interconnect module as the target interconnect layer.

5. The authentication method of claim 4, wherein interconnecting the first interconnect module of the first chipset and the selected interconnect layer of the second chipset comprises:

in response to the second chipset selecting the interconnect layer to be a link layer, directly interconnecting the link layer of the second chipset with the link layer of the first interconnect module and disconnecting the link layer of the first interconnect module from the physical layer of the first interconnect module.

6. The verification method of claim 2, wherein selecting one of a physical layer and a link layer of the first interconnect module as a target interconnect layer comprises:

selecting a physical layer of the first interconnect module as the target interconnect layer.

7. The authentication method of claim 6, wherein interconnecting the first interconnect module of the first chipset and the selected interconnect layer of the second chipset comprises:

in response to the second chipset selecting the interconnect layer to be a physical layer, the second chipset including a physical layer and directly interconnecting the physical layer of the second chipset with the physical layer of the first interconnect module;

in response to the second chipset selecting the interconnect layer to be a link layer, the second chipset includes a physical layer and a link layer and directly interconnects the physical layer of the second chipset with the link layer of the second chipset and the physical layer of the second chipset with the physical layer of the first interconnect module.

8. The authentication method according to any one of claims 2 to 7,

a select interconnect layer of the second chipset directly interconnects with the authentication system.

9. The verification method of claim 2, wherein providing the verification stimulus to the target interconnect layer and receiving the verification output from the target interconnect layer through a select interconnect layer in the second chipset using a verification system comprises:

the verification system sending the verification stimulus to the select interconnect layer;

the selected interconnection layer provides the verification excitation for the target interconnection layer and transmits the verification excitation to pass through a network layer of the first chipset, so that the first chipset obtains a corresponding verification output according to the verification excitation;

the network layer of the first chipset obtains the verification output and sends the verification output to the selected interconnection layer through the target interconnection layer;

the verification system receives the verification output from the selective interconnect layer.

10. The verification method of claim 2, wherein receiving the verification stimulus from the target interconnect layer and providing the verification output to the target interconnect layer through a select interconnect layer in the second chipset using a verification system comprises:

transmitting, by a network layer of the first chipset, the verification stimulus provided by the first chipset to the target interconnect layer;

the target interconnect layer sending the verification stimulus to the select interconnect layer, and the verification system receiving the verification stimulus from the select interconnect layer to obtain a corresponding verification output;

the selected interconnect layer obtains the verification output from the verification system and sends the verification output to the target interconnect layer;

the target interconnect layer receives the verification output and transmits the verification output through a network layer of the first chipset.

11. The authentication method according to any one of claims 1-7, 9-10, wherein selecting a second chipset from the plurality of chipsets comprises:

selecting at least one peer chipset from the plurality of chipsets configured to be interconnected with the first chipset;

selecting the second chipset from the at least one peer chipset.

12. The authentication method of claim 11, further comprising:

selecting at least one third chipset from the at least one peer chipset;

selecting a second interconnect module from at least one interconnect module in the first chipset;

interconnecting a physical layer of a second interconnect module of the first chipset with a physical layer of a corresponding third chipset of the at least one third chipset.

13. The authentication method of claim 12, further comprising:

in response to the at least one third chipset comprising a plurality of third chipset, serially interconnecting each third chipset of the at least one third chipset.

14. The authentication method according to claim 12,

the second chipset and the first chipset are heterogeneous chipsets, and the third chipset and the first chipset are homogeneous chipsets.

15. An electronic device, comprising:

a processor and a memory, and a control unit,

wherein the memory has stored thereon a computer program which, when executed by the processor, implements the authentication method of any one of claims 1 to 14.

16. A computer-readable storage medium, wherein a computer program is stored in the storage medium, which computer program, when being executed by a processor, carries out the authentication method according to any one of claims 1 to 14.