CN114579312A - Instruction processing method, processor, chip and electronic equipment - Google Patents
Instruction processing method, processor, chip and electronic equipment Download PDFInfo
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- CN114579312A CN114579312A CN202210214964.0A CN202210214964A CN114579312A CN 114579312 A CN114579312 A CN 114579312A CN 202210214964 A CN202210214964 A CN 202210214964A CN 114579312 A CN114579312 A CN 114579312A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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Abstract
The invention provides an instruction processing method, a processor, a chip and electronic equipment, wherein the method comprises the following steps: the method comprises the steps of obtaining a target instruction, decoding the target instruction to obtain a plurality of micro instructions, adding operation information of the second micro instruction into the first micro instruction if the plurality of micro instructions comprise a first micro instruction and a second micro instruction, the second micro instruction is used for modifying the mapping relation of a target architecture register in a rename table, and the first micro instruction is a micro instruction which reads the value of the target architecture register at the last position before the second micro instruction, modifying the mapping relation of the target architecture register in the rename table according to the operation information carried by the first micro instruction, so that the second micro instruction does not need to be executed, the number of the micro instructions can be reduced, the execution time of the instructions is reduced, and physical register resources are released in advance.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to an instruction processing method, a processor, a chip and electronic equipment.
Background
During execution of a CISC (Complex Instruction Set Computer) Instruction, a processor typically decodes the Instruction into one or more microinstructions and sends the microinstructions to different execution units in parallel, so as to implement the same function as the Instruction with fewer clock cycles.
However, there is an inevitable issue of architectural register usage conflicts between microinstructions. The commonly used approach is to use temporary registers to hold the results of microinstructions that cause architectural register usage conflicts. However, this in turn results in an increase in the number of microinstructions, resulting in an increase in the time and power consumption of the instruction execution.
Disclosure of Invention
In view of this, embodiments of the present invention provide an instruction processing method, a processor, a chip and an electronic device, so as to solve the problem of an increase in the number of microinstructions due to the use of a temporary register.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions.
In a first aspect, the present invention provides an instruction processing method, including:
acquiring a target instruction;
decoding the target instruction to obtain a plurality of microinstructions;
if the plurality of microinstructions comprise a first microinstruction and a second microinstruction, the second microinstruction is used for modifying the mapping relation of the target architecture register in a renaming table, and the first microinstruction is a microinstruction which reads the value of the target architecture register at the last before the second microinstruction, the operation information of the second microinstruction is added into the first microinstruction;
and modifying the mapping relation of the target architecture register in the rename table according to the operation information carried by the first microinstruction.
In a second aspect, the present invention provides a processor comprising:
the instruction fetching unit is used for acquiring a target instruction;
a decode unit to decode the target instruction to obtain a plurality of microinstructions;
the control unit is used for adding the operation information of the second microinstruction into the first microinstruction when the microinstructions comprise a first microinstruction and a second microinstruction, the second microinstruction is used for modifying the mapping relation of the target architecture register in a rename table, and the first microinstruction is the microinstruction which reads the value of the target architecture register at the last before the second microinstruction;
and the renaming unit is used for modifying the mapping relation of the target architecture register in the renaming table according to the operation information carried by the first microinstruction.
In a third aspect, the present invention provides a chip including the processor according to the embodiment of the present invention.
In a fourth aspect, the present invention provides an electronic device, including the chip according to the embodiment of the present invention.
According to the instruction processing method, the processor, the chip and the electronic device, after the target instruction is obtained, the target instruction is decoded into the multiple micro instructions, if the multiple micro instructions comprise the first micro instruction and the second micro instruction, the second micro instruction is used for modifying the mapping relation of the target architecture register in the renaming table, and the first micro instruction is the micro instruction which reads the value of the target architecture register last before the second micro instruction, the operation information of the second micro instruction is added into the first micro instruction, and the mapping relation of the target architecture register in the renaming table is modified according to the operation information carried by the first micro instruction, so that the second micro instruction does not need to be executed, the second micro instruction can be discarded, the number of the micro instructions can be reduced, the execution time of the instruction can be reduced, and the physical register resource can be released in advance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a processor;
FIG. 2 is a diagram illustrating an ideal data exchange between architectural register A and architectural register B when a swap instruction is executed;
FIG. 3 is a diagram illustrating a data exchange between an architectural register A and an architectural register B during a swap instruction in a practical situation;
FIG. 4 is a block diagram of a processor according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method for instruction processing according to one embodiment of the invention;
FIG. 6 is a diagram illustrating the relationship between target architectural registers and microinstructions according to one embodiment of the present invention;
fig. 7 is a block diagram of a processor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The processor is the computational and control core of the computer architecture. Such as a Central Processing Unit (CPU), various Complex Instruction Set Computing (CISC) processors, various Reduced Instruction Set Computing (RISC) processors, various Very Long Instruction Word (VLIW) processors, and so forth. The processor is generally configured as a pipeline including an instruction fetch stage, a decode stage, a rename stage, an execute stage, and a commit stage.
As shown in fig. 1, fig. 1 is a schematic diagram of a processor, and the processor 10 may include: instruction fetch unit 101, decode unit 102, execution unit 103, rename table 104, physical register file 105, and rename unit 106.
In the fetch stage, instruction fetch unit 101 may fetch instructions from an instruction cache according to the instruction fetch, for example, according to the instruction fetch predicted by a branch prediction unit in the front end of the processor.
In the decode stage, decode unit 102 may decode and parse the instruction fetched by instruction fetch unit 101. The decoded instruction of the decoding unit 102 may be operation information that is obtained by parsing the instruction and is executable by a machine, for example, an OpCode (operation code), an operand, and a control field of the instruction are parsed to form a uop (micro-instruction) executable by the machine. In addition, the decoding unit 102 decodes the current instruction according to the instruction set architecture setting, obtains the specific operations executed by the subsequent execution units in the OpCode of the instruction, and obtains the architecture registers and other required information stored in the source operand and the destination operand of the instruction. The instruction may be expanded into a format required inside the processor after being decoded by the decode unit 102, and the decoded instruction may carry a plurality of attributes, such as opcode, operand, and the like.
In the renaming phase, the renaming unit 106 is used to modify the mapping relationship between the architectural register and the physical register in the renaming table 104. The rename table 104 may record a mapping relationship between actually allocated physical registers and architectural registers. The renaming unit 106 may be configured to re-establish or modify the mapping between the physical registers in the physical register file 105 and the architectural registers by modifying the mapping in the renaming table 104. The physical register after the mapping is reestablished or modified is identified as occupied and is not allocated to other architectural registers until the identified physical register is released, to prevent confusion caused by the reuse of physical registers by subsequent instructions during renaming.
It should be noted that the architectural register is a register specified on the instruction set architecture and can be used by a programmer when using assembly language, and the physical register is a hardware resource actually existing in the processor.
During the execute stage, the execution unit 103 may perform operations based on the decoded instructions, resulting in execution results. The execution unit 103 obtains the number of the physical register corresponding to the architectural register by combining the table entry in the rename table 104 according to the architectural register stored by the source operand and the destination operand decoded by the decoding unit 102; acquiring actually stored data from the physical register file 105 according to the serial number of the physical register to obtain a real-time storage result; and calculating according to the real-time storage result in the physical register to obtain an execution result.
And in a submitting stage, writing the execution result back to the physical register corresponding to the destination register.
It should be noted that the instruction fetch unit 101, the decode unit 102, the execution unit 103, the physical register file 105, and the rename unit 106 shown in fig. 1 may be logic circuit units in the processor 10. In addition, it is understood that fig. 1 only shows a part of the optional structure of the processor 10 by way of example, and the processor 10 may also include other possible devices, for example, the processor may also include other circuit devices that are not necessary for understanding the disclosure of the embodiment of the present invention, and since other circuit devices are not necessary for understanding the disclosure of the embodiment of the present invention, the embodiment of the present invention will not be described again.
It is further noted that there is an inevitable issue of architectural register usage conflicts between microinstructions. For example, after a microinstruction writes new data to an architectural register to overwrite old data of the architectural register, other microinstructions subsequent to the microinstruction cannot read the old data of the architectural register, resulting in a usage conflict for the architectural register.
As shown in fig. 2, fig. 2 is a schematic diagram illustrating the data exchange between the architectural register a and the architectural register B when the swap instruction is executed under an ideal condition, the swap instruction is decoded into at least a micro instruction 1 and a micro instruction 2, the micro instruction 1 assigns the value a of the architectural register a to the architectural register B, and the micro instruction 2 assigns the value B of the architectural register B to the architectural register a.
During the processor rename phase, rename unit 106 renames each microinstruction in order. The specific renaming operation is that each microinstruction searches a renaming table according to the architectural register number of the source operand, acquires the physical register number corresponding to the architectural register number, and then allocates a new physical register number to the destination register.
At the same time, since renaming is in order, micro instruction 1 is renamed first, and architectural register B is allocated a new physical register that stores the new value of a. When the microinstruction 2 is renamed, because the microinstruction 1 modifies the rename table, the microinstruction 2 can only obtain the newly allocated physical register of the microinstruction 1 when reading the physical register number corresponding to the architectural register number of the source operand, and the new value a is stored in the register. Therefore, the microinstruction 2 cannot obtain the old B value stored in the architectural register B, and cannot assign the B value of the architectural register B to the architectural register a, and thus cannot exchange data between the architectural register a and the architectural register B.
When a current processor encounters a problem with an architectural register usage conflict, a method is typically employed that uses a temporary register to hold the result of a microinstruction that causes the architectural register usage conflict. As shown in fig. 3, fig. 3 is a schematic diagram illustrating a data exchange manner between an architectural register a and an architectural register B when a swap instruction is actually executed, the swap instruction is decoded into at least a micro instruction 1, a micro instruction 2 and a micro instruction 3, the micro instruction 1 assigns the value a of the architectural register a to the temporary register T, the micro instruction 2 assigns the value B of the architectural register B to the architectural register a, and the micro instruction 3 assigns the value a of the temporary register T to the architectural register B.
Since micro instruction 2 needs to read the B value of architectural register B instead of the a value stored in architectural register B after micro instruction 3 executes, no micro instruction can write data into architectural register B until all micro instructions reading the B value of architectural register B end. When the microinstruction does not need to reserve the B value of the architectural register before execution, that is, when all the microinstructions that need to read the B value of the architectural register B have been executed, the architectural register B does not have the problem of conflict in use, and at this time, the a value temporarily stored in the temporary register T only needs to be moved to the architectural register B.
However, the use of the temporary register T to solve the problem of the architectural register use conflict among the microinstructions obviously increases the number of microinstructions, resulting in an increase in the execution time of the instructions. In addition, the use of the temporary register T also increases the consumption of the physical register by the microinstruction, which results in a shortage of physical register resources and affects the execution of other instructions requiring the physical register.
The inventor researches and discovers that since a processor can adopt a Move Elimination (Move Elimination) technology to optimize assignment among registers, a physical register corresponding to a temporary register in a rename table and a physical register corresponding to an architectural register can be kept consistent, so that the temporary register and the architectural register can share the value of one physical register, and the temporary register can assign a second value stored by the temporary register to the architectural register. That is, the assignment between registers can be achieved by only modifying the renaming table.
Based on this, the embodiment of the present invention provides an instruction processing scheme, which merges the microinstruction that modifies the rename table with other microinstructions to reduce the number of microinstructions, reduce the execution time of complex instructions, and release physical register resources in advance.
As an optional implementation of the disclosure of the embodiment of the present invention, an embodiment of the present invention provides an instruction processing method, which is used for processing an instruction to implement merging between microinstructions decoded from the instruction.
The execution main body of the instruction processing method provided by the embodiment of the invention can be a processor and also can be a functional module in the processor. The following takes an execution subject of the instruction processing method as an example of a processor, and an exemplary description is given of the instruction processing method provided in the embodiment of the present invention.
As shown in fig. 4, fig. 4 is a schematic diagram of an architecture of a processor according to an embodiment of the present invention, where the processor includes an instruction fetch unit 40, a decode unit 41, and a control unit 42. The control unit 42 includes a renaming unit, that is, the control unit 42 may implement functions of modifying the renaming unit or establishing a renaming table. Of course, the processor further includes an execution unit 43, a renaming table 44, a physical register file 45, a renaming unit 46, and the like, and the functions of the units in the processor can refer to the description of the corresponding parts, which will not be described herein again.
As shown in fig. 5, fig. 5 is a flowchart of an instruction processing method according to an embodiment of the present invention, where the instruction processing method includes:
s501: acquiring a target instruction;
during the fetch stage, fetch unit 40 may fetch target instructions from an instruction cache according to the instruction fetch instruction, e.g., according to the instruction fetch instruction predicted by a branch prediction unit at the front end of the processor. The target instruction includes a CISC instruction.
S502: decoding the target instruction to obtain a plurality of microinstructions;
in the decoding stage, the decoding unit 41 may decode and analyze the target instruction obtained by the instruction fetching unit 40 to obtain a plurality of microinstructions. It should be noted that the microinstructions in the embodiment of the present invention refer to machine-executable uops obtained by decoding target instructions.
S503: if the plurality of microinstructions comprise a first microinstruction and a second microinstruction, the second microinstruction is used for modifying the mapping relation of the target architecture register in the rename table, the first microinstruction is a microinstruction which reads the value of the target architecture register at the last before the second microinstruction, and the operation information of the second microinstruction is added into the first microinstruction;
in the decoding stage, the control unit 42 detects whether the plurality of micro instructions obtained by the decoding unit 41 include a first micro instruction and a second micro instruction, and if so, adds operation information of the second micro instruction to the first micro instruction, i.e., merges the first micro instruction and the second micro instruction.
In an alternative example, the target instruction is a swap instruction for causing a source architectural register, such as architectural register a, and a target architectural register, such as architectural register B, to swap saved values. However, since the target architectural register, such as architectural register B, has a use conflict, or the target architectural register, such as architectural register B, is an architectural register with a register use conflict, the value of the source architectural register, such as architectural register A, is assigned to the temporary register, and then the value of the temporary register is assigned to the target architectural register, such as architectural register B.
Because the assignment between the registers is optimized based on the mobile elimination technology, the value of the temporary register is assigned to the microinstruction of the target architecture register, and only the mapping relation of the target architecture register in the rename table is modified, namely the microinstruction does not need to be executed by the execution unit 43, and only needs to be executed by the rename unit 46, so that the modification of the rename table by the microinstruction can be handed to other microinstructions for execution.
Based on this, the control unit 42 only needs to detect whether there is a microinstruction that assigns the value of the temporary register to the target architecture register among the microinstructions, and if so, the microinstruction may be determined as the second microinstruction, the microinstruction that reads the value of the architecture register last before the second microinstruction is determined as the first microinstruction, and then the operation information of the second microinstruction is added to the first microinstruction.
Wherein, whether a microinstruction is a microinstruction that assigns a temporary register value to a target architectural register may be determined based on the register number. Also, since the first micro instruction is usually the previous micro instruction of the second micro instruction, the previous micro instruction of the second micro instruction can be determined as the first micro instruction after the second micro instruction is determined.
Of course, the present invention is not limited to this, and in other embodiments, even if there is no conflict problem in the target architectural register, or the target architectural register is not an architectural register with a conflict in register use, if there is a microinstruction that only modifies the mapping relationship of the target architectural register in the rename table, the microinstruction may be determined as the second microinstruction, and the microinstruction that reads the value of the target architectural register last before the second microinstruction may be determined as the first microinstruction. That is, as long as there is a microinstruction that only modifies the mapping of the target architectural register in the rename table, that microinstruction may be merged with the corresponding first microinstruction.
It should be noted that the operation information of the second micro instruction may be obtained according to the decoding result of the target instruction, and then the operation information of the second micro instruction may be added to the first micro instruction.
S504: and modifying the mapping relation of the target architecture register in the rename table according to the operation information carried by the first microinstruction.
In the renaming stage, when the renaming unit 46 renames the first microinstruction, the renaming unit renames the first microinstruction according to the operation information of the first microinstruction, for example, the renaming table is modified according to the register number carried by the first microinstruction, and then the renaming unit renames the first microinstruction according to the operation information additionally carried by the first microinstruction, that is, the mapping relationship of the target architecture register in the renaming table is modified according to the operation information additionally carried by the first microinstruction. Based on this, the rename unit 46 renames the first microinstruction twice, i.e., the rename unit 46 modifies the two rename entries according to the first microinstruction.
Because the operation information of the second microinstruction is added into the first microinstruction, and the second microinstruction does not need to be executed after the mapping relation of the target architecture register in the rename table is modified according to the operation information carried by the first microinstruction, which is equivalent to combining the first microinstruction and the second microinstruction, the number of the microinstructions can be reduced, the execution time of the instructions can be reduced, and the physical register resources can be released in advance.
In some alternative examples, after adding the operation information of the second microinstruction to the first microinstruction, the microinstruction may be dispatched to the execution queue for execution, where the second microinstruction may be ignored such that the second microinstruction may not be dispatched to the execution queue. That is, after the operation information of the second microinstruction is added to the first microinstruction, the second microinstruction may be discarded from the dispatch queue, so that the second microinstruction is no longer transmitted backwards, and the second microinstruction no longer occupies resources of various queues in the processor, thereby not only shortening the execution time of the instruction, but also releasing the physical register occupied by the second microinstruction more quickly, and improving the performance of the processor.
In some alternative examples, as shown in fig. 6, fig. 6 is a diagram illustrating a relationship between a target architectural register and a microinstruction according to an embodiment of the present invention, where the data currently stored in the target architectural register is a first value. The first micro instruction is used to read a first value from a target architectural register, and specifically, the first micro instruction may be a micro instruction that reads the first value from the target architectural register and writes the first value to another architectural register.
The second microinstruction is used for modifying the mapping relation of the target architecture register in the rename table. In some optional examples, the second microinstruction is configured to modify a mapping relationship between the target architecture register and other physical registers in the rename table into a mapping relationship between the target architecture register and a physical register corresponding to the temporary register, so as to assign a second value of the temporary register to the target architecture register, that is, write the second value of the temporary register into the target architecture register.
The first micro instruction is a last micro instruction that reads the first value of the target architecture register before the second micro instruction. Although all the microinstructions needing to read the first value from the target architecture register are executed after the execution of the first microinstruction is finished, and the second microinstruction modifies the mapping relation of the target architecture register in the rename table, the problem of conflict of use of the target architecture register does not exist, but the problem of increase of the number of the microinstructions still exists, or the problem of large number of the microinstructions exists.
For example, in resolving an architectural register usage conflict using a temporary register, a first microinstruction is used to assign the B value of architectural register B to architectural register A, and a second microinstruction is used to assign the a value of temporary register T to architectural register B, and there is no usage conflict in architectural register B after the first microinstruction execution ends. However, the use of temporary registers may result in an increased number of microinstructions.
In the embodiment of the invention, the operation information corresponding to the second micro instruction is added into the first micro instruction, and the mapping relation between the target architecture register and other physical registers in the rename table is modified into the mapping relation between the target architecture register and the physical register corresponding to the temporary register according to the operation information carried by the first micro instruction, so that the number of the micro instructions can be further reduced on the basis of avoiding the use conflict of the target architecture register, the occupation of the micro instruction on various queue resources in the processor is reduced, and compared with the prior scheme, the physical register occupied by the temporary register is released by one micro instruction in advance, and the performance of the processor is improved.
And the operation information of the second micro-instruction is added to the first micro-instruction which reads the value of the target architecture register at the last before the second micro-instruction, so that the situation that the micro-instruction still needs to read the first value from the target architecture register after the operation corresponding to the second micro-instruction is executed according to the operation information carried by the first micro-instruction can be avoided, and the instruction execution accuracy of the processor can be further ensured.
It should be noted that, in other optional examples, modifying the mapping relationship of the target architecture register in the rename table may also be modifying the mapping relationship of the target architecture register and other physical registers in the rename table into the mapping relationship of the target architecture register and physical registers corresponding to the other architecture registers, which is not described herein again. Wherein the temporary register may be an architectural register.
In some alternative examples, the operation information added to the first microinstruction may include a number of a target architecture register and a number of a temporary register.
On this basis, according to the operation information carried by the first microinstruction, modifying the mapping relationship between the target architecture register and other physical registers in the rename table into the mapping relationship between the target architecture register and the physical registers corresponding to the temporary registers comprises: according to the number of the temporary register, obtaining the number of a physical register which has a mapping relation with the temporary register from a renaming table item corresponding to the temporary register in the renaming table; and modifying the mapping relation of the target architecture register into the mapping relation between the target architecture register and the physical register in the renaming table corresponding to the target architecture register according to the number of the physical register and the number of the target architecture register.
Of course, the invention is not limited in this regard and in alternative examples, the operation information added to the first microinstruction may include a number of a target architectural register and a number of a physical register corresponding to the temporary register. On this basis, according to the operation information carried by the first microinstruction, modifying the mapping relationship between the target architecture register and other physical registers in the rename table into the mapping relationship between the target architecture register and the physical registers corresponding to the temporary registers comprises: and modifying the mapping relation between the target architecture register and other physical registers into the mapping relation between the target architecture register and the physical registers corresponding to the temporary registers in the micro-architecture rename table entry corresponding to the target architecture register according to the physical register number and the number of the target architecture register.
In order to more conveniently judge whether the microinstruction carries additional operation information and whether the microinstruction needs to be executed, an identifier, which may be some special signals, may be added to the microinstruction for distinguishing. In some optional examples, after adding the operation information of the second microinstruction to the first microinstruction, the method further comprises: adding a first identifier in the first microinstruction and adding a second identifier in the second microinstruction; the first identifier is used for identifying that the first microinstruction carries extra operation information, and the second identifier is used for identifying that the second microinstruction is discarded.
After adding the first identifier in the first microinstruction and adding the second identifier in the second microinstruction, the method further comprises the following steps: acquiring operation information from the first micro instruction according to the first identifier, and executing an operation corresponding to the second micro instruction according to the operation information; the second microinstruction is discarded from the issue queue based on the second identification.
That is, after the first identifier is added to the first microinstruction and the second identifier is added to the second microinstruction, when the microinstruction is dispatched to a different execution queue and waits to be executed, all the microinstructions carrying the second identifier are ignored, so that the second microinstruction is discarded from the dispatch queue, and the second microinstruction is not dispatched to the execution queue.
After the first identifier is added to the first microinstruction and the second identifier is added to the second microinstruction, if the first microinstruction carrying the first identifier is identified, the operation information additionally carried by the first microinstruction needs to be read in comparison with other microinstructions, so that the control unit 42 executes the operation corresponding to the second microinstruction according to the operation information carried by the first microinstruction.
It should be noted that the target instruction is decoded and split into micro instructions in sequence, the micro instructions are renamed in sequence, although the performance of the processor can be improved by executing the micro instructions out of order, in order to ensure that the semantics and the program of the target instruction execution are consistent, the target instruction needs to be submitted in sequence after the instruction execution is finished. Therefore, a micro-architectural rename table, which is a rename table modified during the rename phase, and an architectural rename table, which is a rename table modified during the in-order issue phase, i.e., modified during the last instruction issue phase, are typically maintained in the processor.
Because the wrong branch direction was predicted after the branch instruction, the rename table that was modified by the rename stage may be recorded in terms of the wrong instruction. Since branch mispredictions are discovered and corrected later, the architectural rename table is modified at the instruction commit stage after the instruction is determined to be correct, to ensure the correctness of the instruction execution.
Based on this, in some optional examples, modifying the mapping relationship of the architectural register in the renaming table according to the operation information carried by the first microinstruction includes: and modifying the mapping relation of the architecture register in the micro-architecture renaming table according to the operation information carried by the first micro instruction.
For example, according to the operation information carried by the first microinstruction, the mapping relationship between the architectural register and other physical registers in the microarchitecture renaming table is modified into the mapping relationship between the architectural register and the physical register corresponding to the temporary register, so as to assign the value of the temporary register to the architectural register.
Of course, on this basis, the instruction processing method provided by some embodiments of the present invention further includes: and modifying the mapping relation of the architecture register in the architecture renaming table to ensure that the mapping relation of the architecture register in the architecture renaming table is consistent with the mapping relation of the architecture register in the microarchitecture renaming table.
That is, in the renaming stage, after the mapping relationship of the architectural register in the microarchitecture renaming table is modified according to the operation information carried by the first microinstruction, in the instruction submitting stage, the mapping relationship of the architectural register in the architected renaming table is also modified according to the mapping relationship of the architectural register in the microarchitecture renaming table, so that the mapping relationship of the architectural register in the architected renaming table is consistent with the mapping relationship of the architectural register in the microarchitecture renaming table, and the correctness of the instruction executed by the processor is ensured.
As another alternative implementation of the disclosure of the embodiments of the present invention, the embodiments of the present invention provide a processor, which is configured to process instructions to implement merging between microinstructions decoded from the instructions. As shown in fig. 7, fig. 7 is a schematic diagram of an architecture of a processor according to an embodiment of the present invention, where the processor includes:
an instruction fetch unit 40 for fetching a target instruction;
a decoding unit 41, configured to decode a target instruction to obtain a plurality of microinstructions;
a control unit 42, configured to add operation information of a second microinstruction to the first microinstruction when the plurality of microinstructions includes a first microinstruction and a second microinstruction, and the second microinstruction is used to modify a mapping relationship of a target architecture register in the rename table, and the first microinstruction is a microinstruction that reads a value of the target architecture register last before the second microinstruction;
and a renaming unit 46, configured to modify a mapping relationship of the target architecture register in the renaming table according to the operation information carried by the first microinstruction.
Of course, referring to fig. 4, the processor may further include an execution unit 43, a renaming table 44, a physical register file 45, and the like, which are not described in detail herein.
In some alternative examples, the target architectural register is an architectural register for which register usage conflicts arise.
In some optional examples, modifying the mapping relationship of the target architecture register in the rename table by the rename unit 46 according to the operation information carried by the first microinstruction includes:
according to the operation information carried by the first microinstruction, the mapping relation of a target architecture register in the microarchitecture rename table is modified; the micro-architectural rename table is a rename table that is modified during a renaming phase.
In some optional examples, the second microinstruction is configured to modify a mapping relationship between the target architecture register and other physical registers in the rename table into a mapping relationship between the target architecture register and a physical register corresponding to the temporary register, so as to assign a value of the temporary register to the target architecture register;
the renaming unit modifies the mapping relation of the target architecture register in the renaming table according to the operation information carried by the first microinstruction, and comprises the following steps: and according to the operation information carried by the first microinstruction, modifying the mapping relation between the target architecture register and other physical registers in the rename table into the mapping relation between the target architecture register and the physical registers corresponding to the temporary registers, so as to assign the value of the temporary register to the target architecture register.
In some alternative examples, the operation information includes a number of architectural registers and a number of temporary registers. On this basis, in some optional examples, modifying, by the renaming unit 46, the mapping relationship between the target architectural register and the other physical registers in the renaming table into the mapping relationship between the target architectural register and the physical register corresponding to the temporary register according to the operation information carried by the first microinstruction includes:
according to the number of the temporary register, obtaining the number of a physical register which has a mapping relation with the temporary register from a renaming table item corresponding to the temporary register in the renaming table;
and modifying the mapping relation between the target architecture register and other physical registers in the renaming table corresponding to the target architecture register into the mapping relation between the target architecture register and the physical registers corresponding to the temporary registers according to the physical register number and the number of the target architecture register.
In some optional examples, the renaming unit 46 is further configured to modify the mapping relationship of the target architecture register in the architecture renaming table, so that the mapping relationship of the target architecture register in the architecture renaming table is consistent with the mapping relationship of the target architecture register in the microarchitecture renaming table; the architecture rename table is a rename table that is modified during the instruction commit phase.
In some optional examples, the control unit 42 is further to discard the second microinstruction from the issue queue after adding the operation information of the second microinstruction to the first microinstruction.
In some optional examples, the control unit 42 is further configured to add the first identifier to the first microinstruction and the second identifier to the second microinstruction after adding the operation information of the second microinstruction to the first microinstruction; the first identifier is used for identifying that the first microinstruction carries extra operation information, and the second identifier is used for identifying that the second microinstruction is discarded.
In some optional examples, the control unit 42 is further configured to, after adding the operation information of the second microinstruction to the first microinstruction, obtain the operation information from the first microinstruction according to the first identifier, so as to perform an operation corresponding to the second microinstruction according to the operation information; and discarding the second microinstruction from the dispatch queue according to the second identification.
As another optional implementation of the disclosure in the embodiment of the present invention, an embodiment of the present invention provides a chip, where the chip includes the processor provided in any embodiment of the present invention.
As another optional implementation of the disclosure of the embodiment of the present invention, an embodiment of the present invention provides an electronic device, which includes the chip provided in any embodiment of the present invention. The electronic device can be a terminal device and also can be a cloud server device.
While various embodiments of the present invention have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in connection with the embodiments of the present invention.
Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. An instruction processing method, comprising:
acquiring a target instruction;
decoding the target instruction to obtain a plurality of microinstructions;
if the microinstructions comprise a first microinstruction and a second microinstruction, the second microinstruction is used for modifying the mapping relation of a target architecture register in a renaming table, and the first microinstruction is a microinstruction which reads the value of the target architecture register at the last before the second microinstruction, adding the operation information of the second microinstruction into the first microinstruction;
and modifying the mapping relation of the target architecture register in the rename table according to the operation information carried by the first microinstruction.
2. The instruction processing method according to claim 1, wherein the target architectural register is an architectural register having a register usage conflict.
3. The method of claim 1, wherein modifying the mapping of the target architectural register in the rename table according to the operation information carried by the first microinstruction comprises:
modifying the mapping relation of the target architecture register in a micro architecture rename table according to the operation information carried by the first microinstruction; the microarchitectural rename table is a rename table that is modified during a renaming phase.
4. The instruction processing method according to any one of claims 1 to 3, wherein the second microinstruction is configured to modify a mapping relationship between the target architectural register and another physical register in the rename table into a mapping relationship between the target architectural register and a physical register corresponding to a temporary register, so as to assign a value of the temporary register to the target architectural register;
the modifying the mapping relationship of the target architecture register in the rename table according to the operation information carried by the first microinstruction comprises: and according to the operation information carried by the first microinstruction, modifying the mapping relation between the target architecture register and other physical registers in the rename table into the mapping relation between the target architecture register and the physical register corresponding to the temporary register, so as to assign the value of the temporary register to the target architecture register.
5. The instruction processing method according to claim 4, wherein the operation information includes a number of the target architecture register and a number of the temporary register.
6. The instruction processing method according to claim 5, wherein the modifying the mapping relationship between the target architecture register and other physical registers in the rename table to the mapping relationship between the target architecture register and the physical register corresponding to the temporary register according to the operation information carried by the first microinstruction comprises:
according to the number of the temporary register, obtaining the number of a physical register which has a mapping relation with the temporary register from a renaming table item corresponding to the temporary register in a renaming table;
and modifying the mapping relation between the target architecture register and other physical registers in the renaming table corresponding to the target architecture register into the mapping relation between the target architecture register and the physical registers corresponding to the temporary registers according to the physical register number and the number of the target architecture register.
7. The instruction processing method according to claim 3, further comprising:
modifying the mapping relation of the target architecture register in the architecture renaming table to make the mapping relation of the target architecture register in the architecture renaming table consistent with the mapping relation of the target architecture register in the micro architecture renaming table; the architecture rename table is a rename table that is modified during an instruction commit phase.
8. The method of claim 1, wherein after adding the operation information of the second microinstruction to the first microinstruction, the method further comprises:
discarding the second microinstruction from a dispatch queue.
9. The method of claim 1, wherein after adding the operation information of the second microinstruction to the first microinstruction, the method further comprises:
adding a first identifier in the first microinstruction and adding a second identifier in the second microinstruction; the first identifier is used for identifying that the first microinstruction carries extra operation information, and the second identifier is used for identifying that the second microinstruction is discarded.
10. The method of claim 9, wherein after adding a first tag to the first microinstruction and adding a second tag to the second microinstruction, the method further comprises:
acquiring the operation information from the first microinstruction according to the first identifier, and executing the operation corresponding to the second microinstruction according to the operation information;
and discarding the second microinstruction from a dispatch queue according to the second identifier.
11. A processor, comprising:
the instruction fetching unit is used for acquiring a target instruction;
a decode unit to decode the target instruction to obtain a plurality of microinstructions;
the control unit is used for adding the operation information of the second microinstruction into the first microinstruction when the microinstructions comprise a first microinstruction and a second microinstruction, the second microinstruction is used for modifying the mapping relation of the target architecture register in a rename table, and the first microinstruction is the microinstruction which reads the value of the target architecture register at the last before the second microinstruction;
and the renaming unit is used for modifying the mapping relation of the target architecture register in the renaming table according to the operation information carried by the first microinstruction.
12. The processor of claim 11, wherein the target architectural register is an architectural register having a register usage conflict.
13. The processor of claim 11, wherein the renaming unit modifies the mapping of the target architectural register in the renaming table according to the operation information carried by the first microinstruction comprises:
modifying the mapping relation of the target architecture register in a micro architecture rename table according to the operation information carried by the first microinstruction; the microarchitectural rename table is a rename table that is modified during a renaming phase.
14. The processor according to any one of claims 11 to 13, wherein the second microinstruction is configured to modify a mapping relationship between the target architectural register and other physical registers in the renaming table to a mapping relationship between the target architectural register and a physical register corresponding to a temporary register, so as to assign a value of the temporary register to the target architectural register;
the renaming unit modifies the mapping relation of the target architecture register in the renaming table according to the operation information carried by the first microinstruction, and comprises the following steps: and according to the operation information carried by the first microinstruction, modifying the mapping relation between the target architecture register and other physical registers in the rename table into the mapping relation between the target architecture register and the physical register corresponding to the temporary register, so as to assign the value of the temporary register to the target architecture register.
15. The processor of claim 13, wherein the renaming unit is further configured to modify the mapping of the target architectural register in an architectural renaming table such that the mapping of the target architectural register in the architectural renaming table is consistent with the mapping of the target architectural register in the microarchitectural renaming table; the architecture rename table is a rename table modified in an instruction sequential submission stage.
16. The processor of claim 11, wherein the control unit is further configured to discard the second microinstruction from a dispatch queue after adding operation information for the second microinstruction to the first microinstruction.
17. A chip comprising a processor according to any one of claims 11 to 16.
18. An electronic device comprising the chip of claim 17.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115525344A (en) * | 2022-10-31 | 2022-12-27 | 海光信息技术股份有限公司 | Decoding method, processor, chip and electronic equipment |
| CN116501385A (en) * | 2022-12-16 | 2023-07-28 | 海光信息技术股份有限公司 | Instruction processing method, processor, chip and computer equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115525344A (en) * | 2022-10-31 | 2022-12-27 | 海光信息技术股份有限公司 | Decoding method, processor, chip and electronic equipment |
| CN116501385A (en) * | 2022-12-16 | 2023-07-28 | 海光信息技术股份有限公司 | Instruction processing method, processor, chip and computer equipment |
| CN116501385B (en) * | 2022-12-16 | 2024-04-09 | 海光信息技术股份有限公司 | Instruction processing method, processor, chip and computer equipment |
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