CN114546288A - Method, system, equipment and storage medium for reducing time delay of key command - Google Patents
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Abstract
The invention provides a method, a system, equipment and a storage medium for reducing the time delay of a key command, wherein the method comprises the following steps: in response to receiving the read-write command, storing the read-write command with the first priority in a first data slot, and storing the read-write command with the second priority in a second data slot; analyzing the read-write commands in the first data slot and the second data slot to obtain a logic unit number corresponding to the read-write command, extracting corresponding first sub-data slots from the first data slot according to the logic unit number to be sequenced to form a first queue, and extracting corresponding second sub-data slots from the second data slot to be sequenced to form a second queue; setting the ratio of sending the first sub data slot and the second sub data slot, and respectively setting counters in the first queue and the second queue; and determining the execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and executing the commands according to the execution sequence. The invention reduces the time delay of the key command.
Description
Technical Field
The present invention relates to the field of data transmission, and more particularly, to a method, system, device and storage medium for reducing critical command latency.
Background
For Nand Flash (Flash), a LUN (Logical Unit Number) is the smallest Unit that can independently execute commands and report status, and a Nand granule may contain one or more LUNs that share a set of Nand granule interfaces. At present, the conventional way for executing commands of the same LUN is to execute the commands sequentially according to the order of issuing the commands by FW (Firmware), and such a way, if the key commands are configured after the normal commands, increases the latency of the key commands, and greatly reduces the satisfaction degree of users on products.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, a system, a computer device, and a computer readable storage medium for reducing a latency of a critical command, in which a command sequence issued to a LUN is adjusted by hardware according to a priority of a demand marking command and a set ratio and parameters of a high/low priority, so that a read/write speed of an existing NAND is maintained, and a latency of the critical command is reduced.
Based on the above object, an aspect of the embodiments of the present invention provides a method for reducing a critical command latency, including the following steps: in response to receiving the read-write command, storing the read-write command with the first priority in a first data slot, and storing the read-write command with the second priority in a second data slot; analyzing the read-write commands in the first data slot and the second data slot to obtain a logic unit number corresponding to the read-write command, extracting corresponding first sub data slots from the first data slot according to the logic unit number to be sequenced to form a first queue, and extracting corresponding second sub data slots from the second data slot to be sequenced to form a second queue; setting the ratio of sending a first sub data slot and a second sub data slot, and setting counters in the first queue and the second queue respectively; and determining the execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and executing the commands according to the execution sequence.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and responding to a second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot.
In another aspect of the embodiments of the present invention, a system for reducing a critical command latency is provided, including: the dividing module is configured to respond to the received read-write command, store the read-write command with the first priority in a first data slot, and store the read-write command with the second priority in a second data slot; the sorting module is configured to analyze the read-write commands in the first data slot and the second data slot, obtain a logic unit number corresponding to the read-write command, extract a corresponding first sub-data slot from the first data slot according to the logic unit number to sort to form a first queue, and extract a corresponding second sub-data slot from the second data slot to sort to form a second queue; the setting module is configured to set the proportion of sending the first sub data slot and the second sub data slot, and set counters in the first queue and the second queue respectively; and the execution module is configured to determine an execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and execute the commands according to the execution sequence.
In some embodiments, the execution module is configured to: responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue.
In some embodiments, the execution module is configured to: and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value.
In some embodiments, the execution module is configured to: in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and responding to a second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: according to the priority of the demand marking command, the command sequence issued to the LUN is adjusted by hardware through the setting proportion and parameters of the high/low priority, the read-write speed of the existing NAND is kept, and the time delay of the key command is reduced.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a diagram illustrating an embodiment of a method for reducing critical command latency according to the present invention;
FIG. 2 is a diagram of an embodiment of a system for reducing critical command latency according to the present invention;
FIG. 3 is a diagram illustrating a hardware structure of an embodiment of a computer device for reducing critical command latency according to the present invention;
FIG. 4 is a schematic diagram of an embodiment of a computer storage medium for reducing critical command latency according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of the embodiments of the present invention, an embodiment of a method for reducing a latency of a critical command is provided. Fig. 1 is a schematic diagram illustrating an embodiment of the method for reducing the latency of a critical command according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, in response to the received read-write command, storing the read-write command with the first priority in a first data slot, and storing the read-write command with the second priority in a second data slot;
s2, analyzing the read-write commands in the first data slot and the second data slot, obtaining a logic unit number corresponding to the read-write command, extracting a corresponding first sub-data slot from the first data slot according to the logic unit number to form a first queue, and extracting a corresponding second sub-data slot from the second data slot to form a second queue;
s3, setting and sending the proportion of the first sub data slot and the second sub data slot, and setting counters in the first queue and the second queue respectively; and
and S4, determining the execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and executing the commands according to the execution sequence.
In the embodiment of the invention, the read-write commands of the user and the system are subjected to priority division according to rules, then the commands are stored and analyzed by utilizing hardware resources, and the commands of each LUN are sequenced. And issuing and executing the sorted high-priority command and the low-priority command. In the command allocation method, the execution order of the commands is decided by using the set ratio parameters of the high-priority and low-priority commands and the command counters (H cnt and L cnt).
And responding to the received read-write command, storing the read-write command with the first priority in the first data slot, and storing the read-write command with the second priority in the second data slot. In the embodiment of the invention, the read-write command with the first priority is a high-priority read-write command, and the read-write command with the second priority is a low-priority read-write command. Generally, the firmware sets the read-write command of the user to be high priority, sets the read-write command of the system to be low priority, and also modifies the priority setting according to the requirements in the firmware execution process.
Analyzing the read-write commands in the first data slot and the second data slot, acquiring a logic unit number corresponding to the read-write command, extracting corresponding first sub-data slots from the first data slot according to the logic unit number to be sequenced to form a first queue, and extracting corresponding second sub-data slots from the second data slot to be sequenced to form a second queue. The high-priority read-write command is stored in the high-bit data slot with the depth of N, the low-bit data slot is used for storing the low-priority read-write command, and N can be flexibly set according to actual requirements. In the embodiment of the invention, the first data slot is a high-order data slot, and the second data slot is a low-order data slot. Analyzing the commands in the High-order data slot and the Low-order data slot, dividing the commands according to the LUNs used in the command information, and sorting the first sub data slot and the second sub data slot of the same LUN by using a High queue and a Low queue respectively. In the embodiment of the invention, the first queue is a high-order queue, and the second queue is a low-order queue.
And setting the ratio of sending the first sub data slot and the second sub data slot, and setting counters in the first queue and the second queue respectively. And setting the ratio parameters issued by the first sub data slot (High slot) and the second sub data slot (Low slot). For example, a High: low ═ 3: 1, the read-write command in 1 second sub-data slot needs to be issued every time the read-write command in 3 first sub-data slots is issued. And setting a first counter Hcnt in the first queue, counting the High slots issued in the High queue, setting a second counter Lcnt in the second queue, and counting the Low slots issued in the Low queue.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue. Continuing with the above example, the preset value may be 3, and when the value of the counter in the first queue reaches 3 and the second sub data slot does not exist in the second queue, the read-write command in the first queue continues to be issued.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value. Continuing with the above example, when the value of the counter in the first queue reaches 3 and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and incrementing the value of the counter in the second queue by one, where the second preset value is 3. Of course, in other embodiments, the second preset value may be other values, that is, the read/write command in the second sub data slot in the second queue is issued until the value of the issued read/write command reaches the second preset value.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and responding to a second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot. For example, when the value of the counter in the first queue does not reach 3 but the first sub data slot does not exist in the first queue at this time, it is determined whether a second sub data slot still exists in the second queue at this time, and if the second sub data slot exists in the second queue, the read-write command in the second sub data slot is issued.
If the count value of the Hcnt reaches a preset value, analyzing a Low slot, and issuing a read-write command in a Low queue; if the count value of the Hcnt reaches a preset value and no Low slot exists in the Low queue, analyzing the High slot and issuing a read-write command in the High queue; if the count value of the Hcnt does not reach the preset value and no High slot exists in the High queue at the moment, analyzing the Low slot and issuing a read-write command in the Low queue; if the count value of Hcnt does not reach the preset value, and there is no High slot in the High queue and no Low slot in the Low queue at this time, the command is issued at this time, and the firmware is waited to configure a new command. The counting principle of Lcnt is the same as Hcnt described above.
And determining the execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and executing the commands according to the execution sequence.
In the invention, the software and the hardware cooperate with each other, and the hardware carries out arbitration operation on the commands with high priority and low priority issued by the firmware. The proportion and the parameters of the high/low priority command are set according to the actual application requirements, so that certain commands are allowed to be executed preferentially, the time delay of certain emergency commands, particularly read commands, is reduced, and the performance of a Solid State Disk (SSD) is improved.
It should be particularly noted that, the steps in the embodiments of the method for reducing the critical command latency can be mutually intersected, replaced, added, and deleted, so that these methods for reducing the critical command latency, which are reasonably transformed by permutation and combination, should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the above, a second aspect of the embodiments of the present invention provides a system for reducing latency of critical commands. As shown in fig. 2, the system 200 includes the following modules: the dividing module is configured to respond to the received read-write command, store the read-write command with the first priority in a first data slot, and store the read-write command with the second priority in a second data slot; the sorting module is configured to analyze the read-write commands in the first data slot and the second data slot, obtain a logic unit number corresponding to the read-write command, extract a corresponding first sub-data slot from the first data slot according to the logic unit number to sort to form a first queue, and extract a corresponding second sub-data slot from the second data slot to sort to form a second queue; the setting module is configured to set the proportion of sending the first sub data slot and the second sub data slot, and set counters in the first queue and the second queue respectively; and the execution module is configured to determine an execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and execute the commands according to the execution sequence.
In some embodiments, the execution module is configured to: responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue.
In some embodiments, the execution module is configured to: and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value.
In some embodiments, the execution module is configured to: in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and responding to a second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, in response to the received read-write command, storing the read-write command with the first priority in a first data slot, and storing the read-write command with the second priority in a second data slot; s2, analyzing the read-write commands in the first data slot and the second data slot, obtaining a logic unit number corresponding to the read-write command, extracting a corresponding first sub-data slot from the first data slot according to the logic unit number to form a first queue, and extracting a corresponding second sub-data slot from the second data slot to form a second queue; s3, setting and sending the proportion of the first sub data slot and the second sub data slot, and setting counters in the first queue and the second queue respectively; and S4, determining the execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and executing the commands according to the execution sequence.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value.
In some embodiments, the determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue includes: in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and responding to a second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot.
Fig. 3 is a schematic hardware structural diagram of an embodiment of the computer device for reducing the critical command latency according to the present invention.
Taking the device shown in fig. 3 as an example, the device includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, such as the bus connection in fig. 3.
The memory 302 is a non-volatile computer-readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for reducing the latency of critical commands in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., implements a method of reducing critical command latency, by running non-volatile software programs, instructions, and modules stored in the memory 302.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of reducing the latency of critical commands, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Any embodiment of a computer device implementing the method for reducing critical command latency described above may achieve the same or similar effects as any of the preceding method embodiments corresponding thereto.
The present invention also provides a computer readable storage medium storing a computer program for executing the method of reducing latency of a critical command when executed by a processor.
FIG. 4 is a schematic diagram of an embodiment of a computer storage medium for reducing critical command latency according to the present invention. Taking the computer storage medium as shown in fig. 4 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for reducing the latency of the critical command can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), or a Random Access Memory (RAM). The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant only to be exemplary, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of an embodiment of the invention, also combinations between technical features in the above embodiments or in different embodiments are possible, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for reducing latency of critical commands, comprising the steps of:
in response to receiving the read-write command, storing the read-write command with the first priority in a first data slot, and storing the read-write command with the second priority in a second data slot;
analyzing the read-write commands in the first data slot and the second data slot to obtain a logic unit number corresponding to the read-write command, extracting corresponding first sub data slots from the first data slot according to the logic unit number to be sequenced to form a first queue, and extracting corresponding second sub data slots from the second data slot to be sequenced to form a second queue;
setting the ratio of sending a first sub data slot and a second sub data slot, and setting counters in the first queue and the second queue respectively; and
and determining the execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and executing the commands according to the execution sequence.
2. The method of claim 1, wherein determining an execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue comprises:
responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and
and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue.
3. The method of claim 2, wherein determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue comprises:
and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value.
4. The method of claim 2, wherein determining the execution order of the read and write commands according to the ratio and the values of the counters in the first queue and the second queue comprises:
in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and
and responding to the second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot.
5. A system for reducing critical command latency, comprising:
the dividing module is configured to respond to the received read-write command, store the read-write command with the first priority in a first data slot, and store the read-write command with the second priority in a second data slot;
the sorting module is configured to analyze the read-write commands in the first data slot and the second data slot, obtain a logic unit number corresponding to the read-write command, extract a corresponding first sub-data slot from the first data slot according to the logic unit number to sort to form a first queue, and extract a corresponding second sub-data slot from the second data slot to sort to form a second queue;
the setting module is configured to set the proportion of sending the first sub data slot and the second sub data slot, and set counters in the first queue and the second queue respectively; and
and the execution module is configured to determine an execution sequence of the read-write commands according to the proportion and the values of the counters in the first queue and the second queue, and execute the commands according to the execution sequence.
6. The system of claim 5, wherein the execution module is configured to:
responding to the value of the counter in the first queue to reach a preset value, and judging whether a second sub data slot still exists in the second queue; and
and responding to the second queue without the second sub data slot, and continuing to issue the read-write command in the first queue.
7. The system of claim 6, wherein the execution module is configured to:
and in response to the fact that the value of the counter in the first queue reaches a preset value and a second sub data slot exists in the second queue, issuing a read-write command in the second sub data slot in the second queue and adding one to the value of the counter in the second queue until the value of the counter in the second queue reaches a second preset value.
8. The system of claim 6, wherein the execution module is configured to:
in response to that the value of the counter in the first queue does not reach a preset value and a first sub data slot does not exist in the first queue, judging whether a second sub data slot still exists in the second queue; and
and responding to the second sub data slot existing in the second queue, and issuing a read-write command in the second sub data slot.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527967A (en) * | 2015-09-10 | 2017-03-22 | 蜂巢数据有限公司 | Reducing read command latency in storage devices |
| US20180336150A1 (en) * | 2017-05-19 | 2018-11-22 | Western Digital Technologies, Inc. | Context-aware dynamic command scheduling for a data storage system |
| US20200159680A1 (en) * | 2018-11-19 | 2020-05-21 | Xilinx, Inc. | Programming and controlling compute units in an integrated circuit |
| CN111258932A (en) * | 2020-01-09 | 2020-06-09 | 厦门鑫忆讯科技有限公司 | Method for accelerating UFS protocol processing and storage controller |
| US20200278808A1 (en) * | 2019-02-28 | 2020-09-03 | Micron Technology, Inc. | Double threshold controlled scheduling of memory access commands |
-
2022
- 2022-02-27 CN CN202210182776.4A patent/CN114546288A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527967A (en) * | 2015-09-10 | 2017-03-22 | 蜂巢数据有限公司 | Reducing read command latency in storage devices |
| US20180336150A1 (en) * | 2017-05-19 | 2018-11-22 | Western Digital Technologies, Inc. | Context-aware dynamic command scheduling for a data storage system |
| US20200159680A1 (en) * | 2018-11-19 | 2020-05-21 | Xilinx, Inc. | Programming and controlling compute units in an integrated circuit |
| US20200278808A1 (en) * | 2019-02-28 | 2020-09-03 | Micron Technology, Inc. | Double threshold controlled scheduling of memory access commands |
| CN111258932A (en) * | 2020-01-09 | 2020-06-09 | 厦门鑫忆讯科技有限公司 | Method for accelerating UFS protocol processing and storage controller |
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