CN114519975B

CN114519975B - Driving method of display panel and display device

Info

Publication number: CN114519975B
Application number: CN202011307431.4A
Authority: CN
Inventors: 王�琦; 于志超
Original assignee: EverDisplay Optronics Shanghai Co Ltd
Current assignee: EverDisplay Optronics Shanghai Co Ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2023-06-30
Anticipated expiration: 2040-11-19
Also published as: CN114519975A

Abstract

The embodiment of the invention discloses a driving method of a display panel and a display device. The driving method of the display panel comprises the following steps: a single line scanning mode and a double line simultaneous scanning mode; the double-line simultaneous scanning mode includes: inputting a first start signal to a start signal line; inputting a first clock signal to the first clock signal line and the third clock signal line; inputting a second clock signal to the second clock signal line and the fourth clock signal line; the first shift register and the second shift register of the same stage output driving signals at the same time; the single line scan mode includes: inputting a second start signal to the start signal line; inputting different clock signals to the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line; the first shift register group and the second shift register group alternately output driving signals. The technical scheme provided by the embodiment of the invention can realize the switching between the high-resolution mode and the high-refresh rate mode.

Description

Driving method of display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving method of a display panel and a display device.

Background

Displays are increasingly used in modern life, such as cell phone displays, notebook displays, MP3 (Moving Picture Experts Group Audio Layer-3) displays, television displays, augmented reality or virtual reality head mounted devices, and the like.

The higher the resolution of the display, the clearer the still image. The higher the refresh frequency of the display, the shorter the moving image switching delay, which is of significant benefit to some specific scenarios such as games. How to switch between high image quality and high refresh rate can satisfy the use requirement of users for different scenes.

Disclosure of Invention

The embodiment of the invention provides a driving method of a display panel and a display device, which are used for realizing switching between a high-resolution mode and a high-refresh rate mode.

In a first aspect, an embodiment of the present invention provides a driving method of a display panel, where the display panel includes a driving circuit and a plurality of driving signal lines;

the driving circuit includes: a first shift register group, a second shift register group, a start signal line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line,

the first shift register group comprises a plurality of cascaded first shift registers, and the first shift registers are electrically connected with a first clock signal line and a second clock signal line; the starting signal end of the first shift register positioned at the first stage is electrically connected with a starting signal wire; any one of the first shift registers is electrically connected with a driving signal line; the different first shift registers are electrically connected with different driving signal lines;

The second shift register group comprises a plurality of cascaded second shift registers, and the second shift registers are electrically connected with the third clock signal line and the fourth clock signal line; the starting signal end of the second shift register positioned at the first stage is electrically connected with a starting signal wire; any one of the second shift registers is electrically connected with a driving signal line; the different second shift registers are electrically connected with different driving signal lines; the first shift register and the second shift register are electrically connected to different driving signal lines;

the driving method comprises the following steps: a single line scanning mode and a double line simultaneous scanning mode;

the double-line simultaneous scanning mode includes:

inputting a first start signal to a start signal line;

inputting a first clock signal to the first clock signal line and the third clock signal line;

inputting a second clock signal to the second clock signal line and the fourth clock signal line, wherein the first clock signal and the second clock signal have the same period, the first level of the first clock signal and the first level of the second clock signal do not overlap in time, the first level is the same as the level of the first start signal, and the first clock signal and the first level of the second clock signal are generated in a cyclic manner according to the sequence of the first level of the first clock signal and the first level of the second clock signal;

The first shift register outputs a driving signal step by step;

the second shift register outputs driving signals step by step, wherein the q-th stage of the second shift register outputs driving signals at the same time when the q-th stage of the first shift register outputs driving signals, q is an integer, q is more than or equal to 1 and less than or equal to N-1, and N is the number of the first shift registers;

the single line scan mode includes:

inputting a second start signal to the start signal line;

inputting a third clock signal to the first clock signal line;

inputting a fourth clock signal to the second clock signal line;

inputting a fifth clock signal to the third clock signal line;

inputting a sixth clock signal to the fourth clock signal line, wherein the periods of the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, and the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal and the second level of the sixth clock signal do not overlap in time; generating in a sequential cycle of the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal; the second level is the same as the level of the second start signal;

The first shift register outputs a driving signal step by step;

the second shift register outputs the driving signal step by step, wherein after the q-th stage first shift register outputs the driving signal, the q-th stage second shift register outputs the driving signal before the q+1-th stage first shift register outputs the driving signal.

In a second aspect, an embodiment of the present invention further provides a display apparatus, including a display panel and a timing control circuit;

the display panel includes: a driving circuit and a plurality of driving signal lines;

The starting signal line, the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are electrically connected with the time sequence control circuit;

the time sequence control circuit is used for inputting a first starting signal to the starting signal line in a double-row simultaneous scanning mode; inputting a first clock signal to the first clock signal line and the third clock signal line; inputting a second clock signal to the second clock signal line and the fourth clock signal line, wherein the first clock signal and the second clock signal have the same period, the first level of the first clock signal and the first level of the second clock signal do not overlap in time, the first level is the same as the level of the first start signal, and the first clock signal and the first level of the second clock signal are generated in a cyclic manner according to the sequence of the first level of the first clock signal and the first level of the second clock signal; the first shift register outputs a driving signal step by step; the second shift register outputs driving signals step by step, wherein the q-th stage of the second shift register outputs driving signals at the same time when the q-th stage of the first shift register outputs driving signals, q is an integer, q is more than or equal to 1 and less than or equal to N-1, and N is the number of the first shift registers; in the single-line scanning mode, inputting a second start signal to the start signal line; inputting a third clock signal to the first clock signal line; inputting a fourth clock signal to the second clock signal line; inputting a fifth clock signal to the third clock signal line; inputting a sixth clock signal to the fourth clock signal line, wherein the periods of the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, and the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal and the second level of the sixth clock signal do not overlap in time; generating in a sequential cycle of the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal; the second level is the same as the level of the second start signal; the first shift register outputs a driving signal step by step; the second shift register outputs the driving signal step by step, wherein after the q-th stage first shift register outputs the driving signal, the q-th stage second shift register outputs the driving signal before the q+1-th stage first shift register outputs the driving signal.

In the technical scheme of the embodiment of the invention, in the double-row simultaneous scanning mode, a first clock signal is input to a first clock signal line and a third clock signal line, a second clock signal is input to a second clock signal line and a fourth clock signal line, so that two rows of pixel units corresponding to driving signal lines connected with a q-th stage first shift register and a q-th stage second shift register are scanned at the same time, two rows of simultaneous scanning is realized, scanning time is shortened, and refreshing frequency is improved. In the single-line scanning mode, a third clock signal is input to the first clock signal line, a fourth clock signal is input to the second clock signal line, a fifth clock signal is input to the third clock signal line, and a sixth clock signal is input to the fourth clock signal line, so that the first shift register group and the second shift register group alternately output driving signals to realize progressive scanning, and resolution is improved.

Drawings

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 2 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

FIG. 3 is a timing chart of a dual-line simultaneous scanning mode according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a single-line scanning mode according to an embodiment of the present invention;

FIG. 5 is a waveform diagram of signals at each end of a first shift register in outputting driving signals according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another display device according to an embodiment of the present invention;

fig. 7 is a flowchart of a driving method of a display panel according to another embodiment of the present invention;

FIG. 8 is a timing diagram of a dual-line simultaneous scanning mode according to an embodiment of the present invention;

FIG. 9 is a timing diagram of a single scan mode according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another display device according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of another display device according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a first shift register according to an embodiment of the present invention.

Description of the embodiments

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention. Wherein the display panel comprises a driving circuit and a plurality of driving signal lines 30.

The driving circuit includes: the first shift register group, the second shift register group, the start signal line STV, the first clock signal line CK1, the second clock signal line CK1, the third clock signal line CK1, and the fourth clock signal line CK1.

The plurality of driving signal lines 30 may extend in the first direction and be arranged in the second direction.

The first shift register group includes a plurality of cascaded first shift registers 10, the first shift registers 10 being electrically connected to the first clock signal line CK1 and the second clock signal line CK 2; the start signal terminal S1 of the first shift register 10 positioned at the first stage is electrically connected with the start signal line STV; any one of the first shift registers 10 is electrically connected to a driving signal line 30; the different first shift registers 10 are electrically connected to different drive signal lines 30. The i-th stage first shift register 10 may be electrically connected to the driving signal line 30 located at the 2i-1 th stage. i is an integer, i is not less than 1 and not more than N, and the number of the first shift registers 10 is N.

In which fig. 1 illustrates a case of cascading two first shift registers, which are the first shift registers 10-1 and 10-2, respectively. Any one of the first shift registers may output a driving signal delayed with respect to the start signal to the first driving signal line 30 electrically connected thereto in coordination with the clock signals having the same period and opposite phase inputted from the first clock signal input terminal CK and the second clock signal input terminal XCK when the start signal terminal S1 thereof receives the start signal, so that the light emitting state of a row of pixel units electrically connected to the first driving signal line 30 is updated, the updated light emitting state may be the same as or different from the previous light emitting state, and the light emitting state may include at least one of the color and the brightness of the light emitted from the pixel units, and output a start signal triggering the start of the next stage of the first shift register to the trigger signal terminal S2 thereof. Optionally, the first shift register further includes a driving signal output terminal electrically connected to the corresponding first driving signal line. Optionally, the trigger signal end S2 of the first shift register and the driving signal output end are the same end or different ends.

The second shift register group includes a plurality of cascaded second shift registers 20, the second shift registers 20 being electrically connected to the third clock signal line CK3 and the fourth clock signal line CK 4; the start signal terminal S1 of the second shift register 20 located at the first stage is electrically connected to the start signal line STV; any one of the second shift registers 20 is electrically connected to a driving signal line 30; the second different shift register 20 is electrically connected to the different drive signal line 30; the first shift register 10 and the second shift register 20 are electrically connected to different driving signal lines 30. The j-th stage second shift register 20 may be electrically connected to the driving signal line 30 located at the 2 j-th stage. j is an integer, 1.ltoreq.j.ltoreq.M, and the number of the second shift registers 20 is M.

In which fig. 1 illustrates a case of cascading two second shift registers, which are the second shift registers 20-1 and 20-2, respectively. The second shift register 20 has the same or similar structure and principle as the first shift register, and will not be described again here. The first shift register group and the second shift register group may be located at the same side of the driving signal line. Alternatively, the driving circuit is a scan driving circuit, and the driving signal line 30 is a scan line. Alternatively, the driving circuit is a light emission control circuit, and the driving signal line 30 is a light emission control line.

The embodiment of the invention provides a driving method of a display panel. Fig. 2 is a flowchart of a driving method of a display panel according to an embodiment of the present invention. Fig. 3 is a timing chart of a dual-line simultaneous scanning mode according to an embodiment of the present invention. Fig. 4 is a timing chart of a single-line scanning mode according to an embodiment of the present invention. The driving method of the display panel can be realized based on the display device provided by any embodiment of the invention. The driving method of the display panel comprises the following steps: a single line scan mode and a double line simultaneous scan mode.

As shown in connection with fig. 1 to 3, the two-line simultaneous scanning mode includes:

step 110, inputting a first start signal to the start signal line.

Here, as shown in fig. 1 to 3, a first start signal is input to the start signal line STV. The first enable signal may be low or high. Fig. 3 illustrates an exemplary case where the first enable signal is low.

Step 120, inputting the first clock signal to the first clock signal line and the third clock signal line.

As shown in fig. 1 and 3, the waveforms of the signals input to the first clock signal line CK1 and the third clock signal line CK3 are the same, and are the first clock signals.

Step 130, inputting the second clock signal to the second clock signal line and the fourth clock signal line.

As shown in fig. 1 and 3, the waveforms of the signals input to the second clock signal line CK2 and the fourth clock signal line CK4 are the same, and are both the second clock signals. Optionally, the periods of the first clock signal and the second clock signal are the same, and are both T1. The first level of the first clock signal and the first level of the second clock signal do not overlap in time, the first level being the same as the level of the first start signal, and illustratively the first level is a low level. Illustratively, the first clock signal is at a first level during a time period T11 and the second clock signal is at a first level during a time period T12. The first clock signal and the second clock signal are sequentially cyclically generated.

Step 140, the first shift register outputs the driving signal step by step.

Fig. 5 is a waveform diagram of signals at each end in a process of outputting a driving signal by the first shift register according to an embodiment of the present invention. In order to output the adjacent two stages of the first shift registers step by step, the clock signal input by the first clock signal input terminal CK of the first shift register of the previous stage is required to be identical to the clock signal input by the second clock signal input terminal XCK of the first shift register of the next stage, and the clock signal input by the second clock signal input terminal XCK of the first shift register of the previous stage is required to be identical to the clock signal input by the first clock signal input terminal CK of the first shift register of the next stage. In the adjacent two stages of first shift registers, the starting time of the output driving signals of the first shift register of the previous stage is earlier than the starting time of the output driving signals of the first shift register of the next stage. The first shift register 10 may output a driving signal when the clock signal input from the second clock signal input XCK is at the same level as the start signal. Fig. 3 illustrates a case where the driving signal is at a low level and the first start signal is at a low level, where S10-1 is a signal waveform of the driving signal output terminal or the trigger signal terminal of the first stage first shift register 10-1, and S10-2 is a signal waveform of the driving signal output terminal or the trigger signal terminal of the second stage first shift register 10-2. Illustratively, during the time period T12, the first stage first shift register 10-1 outputs the driving signal. In the period T11, the second stage first shift register 10-2 outputs a driving signal.

Step 150, the second shift register outputs driving signals step by step, wherein the q-th stage of the second shift register outputs driving signals at the same time when the q-th stage of the first shift register outputs driving signals, q is an integer, q is more than or equal to 1 and less than or equal to N-1, and N is the number of the first shift registers.

In order to output the adjacent two stages of second shift registers step by step, the clock signal input by the first clock signal input terminal CK of the previous stage of second shift register is required to be identical to the clock signal input by the second clock signal input terminal XCK of the next stage of second shift register, and the clock signal input by the second clock signal input terminal XCK of the previous stage of second shift register is required to be identical to the clock signal input by the first clock signal input terminal CK of the next stage of second shift register. In the adjacent two stages of second shift registers, the starting time of the output driving signals of the previous stage of second shift registers is earlier than the starting time of the output driving signals of the next stage of second shift registers. The start time of the output driving signal of the q-th stage first shift register may be the same as the start time of the output driving signal of the q-th stage second shift register. The second shift register 20 may output a driving signal when the clock signal input from the second clock signal input XCK is at the same level as the start signal. As shown in fig. 3, S20-1 is a signal waveform of a driving signal output terminal or a trigger signal terminal of the first stage second shift register 20-1, and S20-2 is a signal waveform of a driving signal output terminal or a trigger signal terminal of the second stage second shift register 20-2. Illustratively, the first stage second shift register 20-1 outputs a driving signal at the same time as the first stage first shift register 10-1 outputs a driving signal during the period T12. In the period T11, the second stage second shift register 20-2 outputs the driving signal while the second stage first shift register 10-2 outputs the driving signal.

As shown in connection with fig. 1, 2 and 4, the single-line scan mode includes:

step 160, inputting a second start signal to the start signal line.

Here, as shown in fig. 1, 2, and 4, a second start signal is input to the start signal line STV. The second enable signal may be low or high. Fig. 4 illustrates a case where the second enable signal is low.

Step 170, inputting a third clock signal to the first clock signal line.

Here, as shown in fig. 1, 2, and 4, the third clock signal is input to the first clock signal line CK 1.

Step 180, inputting a fourth clock signal to the second clock signal line.

As shown in fig. 1, 2, and 4, the fourth clock signal is input to the second clock signal line CK 2.

Step 190, inputting a fifth clock signal to the third clock signal line.

As shown in fig. 1, 2, and 4, the fifth clock signal is input to the third clock signal line CK 3.

Step 200, inputting a sixth clock signal to the fourth clock signal line.

As shown in fig. 1, 2, and 4, the sixth clock signal is input to the fourth clock signal line CK 4. Optionally, the periods of the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, and are all T2. The second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal do not overlap in time, the second level being the same as the level of the second enable signal. Illustratively, the second level is a low level. Illustratively, the fourth clock signal is at the second level during a time period T21, the sixth clock signal is at the second level during a time period T22, the third clock signal is at the second level during a time period T23, and the fifth clock signal is at the second level during a time period T24. The second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal are sequentially cyclically generated.

Step 210, the first shift register outputs the driving signal step by step.

In the case where the driving signal is shown as low in fig. 4 and the second enable signal is shown as low in the example, the first stage first shift register 10-1 outputs the driving signal in the period T21. In the period T23, the second stage first shift register 10-2 outputs a driving signal.

Step 220, the second shift register outputs the driving signal step by step, wherein after the first shift register of the q-th stage outputs the driving signal, the second shift register of the q-th stage outputs the driving signal before the first shift register of the q+1-th stage outputs the driving signal.

The start time of the output driving signal of the q-th stage first shift register can be earlier than the start time of the output driving signal of the q-th stage second shift register. The start time of the output driving signal of the q+1th stage first shift register may be later than the start time of the output driving signal of the q-th stage second shift register. As shown in fig. 4, the first stage second shift register 20-1 outputs a driving signal during a period T22. In the period T24, the second stage second shift register 20-2 outputs a driving signal. After the first stage first shift register 10-1 outputs the driving signal, the first stage second shift register 20-1 outputs the driving signal before the second stage first shift register 10-2 outputs the driving signal.

In the technical scheme of the embodiment, in the dual-row simultaneous scanning mode, a first clock signal is input to a first clock signal line and a third clock signal line, a second clock signal is input to a second clock signal line and a fourth clock signal line, so that two rows of pixel units corresponding to driving signal lines connected with a q-th stage first shift register and a q-th stage second shift register are scanned at the same time, two rows of simultaneous scanning is realized, scanning time is reduced, and refreshing frequency is improved. In the single-line scanning mode, a third clock signal is input to the first clock signal line, a fourth clock signal is input to the second clock signal line, a fifth clock signal is input to the third clock signal line, and a sixth clock signal is input to the fourth clock signal line, so that the first shift register group and the second shift register group alternately output driving signals to realize progressive scanning, and resolution is improved.

Optionally, based on the foregoing embodiment, fig. 6 is a schematic structural diagram of another display device provided in the embodiment of the present invention, where the display panel 1 further includes: the first switching unit 51. The first switching unit 51 includes a first terminal, a second terminal, and a control terminal, and the first clock signal line CK1 is electrically connected to the first terminal of the first switching unit 51; a second terminal of the first switching unit 51 is for receiving a first clock signal.

Wherein, in the double-row simultaneous scanning mode or the high refresh frequency mode (for example, the refresh frequency may be 120 Hz), the first switching unit 51 is controlled to be turned on to input the first clock signal to the first clock signal line CK 1. In the single-line scanning mode or the high resolution mode, the first switching unit 51 is controlled to be turned off, and the first clock signal is not input to the first clock signal line CK 1. The first switching unit 51 may include a thin film transistor.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: and a second switching unit 52. The second switching unit 52 includes a first terminal, a second terminal, and a control terminal, and the first clock signal line CK1 is electrically connected to the first terminal of the second switching unit 52; a second terminal of the second switching unit 52 is arranged to receive a third clock signal.

The second switching unit 52 may include a thin film transistor. In the single-line scanning mode or the high resolution mode, the second switching unit 52 is controlled to be turned on to input the third clock signal to the first clock signal line CK 1. In the double-row simultaneous scanning mode or the high refresh frequency mode, the second switching unit 52 is controlled to be turned off, and the first clock signal is not input to the first clock signal line CK 1. The first switching unit 51 and the second switching unit 52 are not turned on at the same time. The clock signal transmitted on the first clock signal line CK1 is controlled by controlling the switching states of the first switching unit 51 and the second switching unit 52.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: the third switching unit 53. The third switching unit 53 includes a first terminal, a second terminal, and a control terminal, and the second clock signal line CK2 is electrically connected to the first terminal of the third switching unit 53; a second terminal of the third switching unit 53 is for receiving a second clock signal.

The third switching unit 53 may include a thin film transistor, among others. In the double-row simultaneous scanning mode or the high refresh frequency mode, the third switching unit 53 is controlled to be turned on to input the second clock signal to the second clock signal line CK 2. In the single-line scanning mode or the high resolution mode, the third switching unit 53 is controlled to be turned off, and the second clock signal is not input to the second clock signal line CK 2.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: fourth switching unit 54. The fourth switch unit 54 includes a first terminal, a second terminal, and a control terminal, and the second clock signal line CK2 is electrically connected to the first terminal of the fourth switch unit 54; a second terminal of the fourth switching unit 54 is arranged to receive a fourth clock signal.

The fourth switching unit 54 may include a thin film transistor. In the single-line scanning mode or the high resolution mode, the fourth switching unit 54 is controlled to be turned on to input the fourth clock signal to the second clock signal line CK 2. In the two-line simultaneous scanning mode or the high refresh frequency mode, the fourth switching unit 54 is controlled to be turned off, and the fourth clock signal is not input to the second clock signal line CK 2. The third switching unit 53 and the fourth switching unit 54 are not turned on at the same time. The clock signal transmitted on the second clock signal line CK2 is controlled by controlling the switching states of the third switching unit 53 and the fourth switching unit 54.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: and a fifth switching unit 55. The fifth switching unit 55 includes a first terminal, a second terminal, and a control terminal, and the third clock signal line CK3 is electrically connected to the first terminal of the fifth switching unit 55; a second terminal of the fifth switching unit 55 is for receiving the first clock signal.

The fifth switching unit 55 may include a thin film transistor. In the double-row simultaneous scanning mode or the high refresh frequency mode, the fifth switching unit 55 is controlled to be turned on to input the first clock signal to the third clock signal line CK 3. In the single-line scanning mode or the high resolution mode, the fifth switching unit 55 is controlled to be turned off, and the first clock signal is not input to the third clock signal line CK 3.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: a sixth switching unit 56. The sixth switching unit 56 includes a first terminal, a second terminal, and a control terminal, and the third clock signal line CK3 is electrically connected to the first terminal of the sixth switching unit 56; a second terminal of the sixth switching unit 56 is for receiving the fifth clock signal.

The sixth switching unit 56 may include a thin film transistor. In the single-line scanning mode or the high resolution mode, the sixth switching unit 56 is controlled to be turned on to input the fifth clock signal to the third clock signal line CK 3. In the two-line simultaneous scanning mode or the high refresh frequency mode, the sixth switching unit 56 is controlled to be turned off, and the fifth clock signal is not input to the third clock signal line CK 3. The fifth switching unit 55 and the sixth switching unit 56 are not turned on at the same time. The clock signal transmitted on the third clock signal line CK3 is controlled by controlling the switching states of the fifth switching unit 55 and the sixth switching unit 56.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: a seventh switching unit 57. The seventh switching unit 57 includes a first terminal, a second terminal, and a control terminal, and the fourth clock signal line CK4 is electrically connected to the first terminal of the seventh switching unit 57; a second terminal of the seventh switching unit 57 is for receiving the second clock signal.

Among them, the seventh switching unit 57 may include a thin film transistor. In the double-row simultaneous scanning mode or the high refresh frequency mode, the seventh switching unit 57 is controlled to be turned on to input the second clock signal to the fourth clock signal line CK 4. In the single-line scanning mode or the high resolution mode, the seventh switching unit 57 is controlled to be turned off, and the second clock signal is not input to the fourth clock signal line CK 4.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: eighth switching unit 58. The eighth switching unit 58 includes a first terminal, a second terminal, and a control terminal, and the fourth clock signal line CK4 is electrically connected to the first terminal of the eighth switching unit 58; a second terminal of the eighth switching unit 58 is arranged to receive the sixth clock signal.

The eighth switching unit 58 may include a thin film transistor. In the single-line scanning mode or the high resolution mode, the eighth switching unit 58 is controlled to be turned on to input the sixth clock signal to the fourth clock signal line CK 4. In the two-line simultaneous scanning mode or the high refresh frequency mode, the eighth switching unit 58 is controlled to be turned off, and the sixth clock signal is not input to the fourth clock signal line CK 4. The seventh switching unit 57 and the eighth switching unit 58 are not turned on at the same time. The clock signal transmitted on the fourth clock signal line CK4 is controlled by controlling the switching states of the seventh switching unit 57 and the eighth switching unit 58.

Optionally, with continued reference to fig. 6, based on the foregoing embodiment, the display panel further includes: at least one control signal line. The control terminal of the first switching unit 51, the control terminal of the second switching unit 52, the control terminal of the third switching unit 53, the control terminal of the fourth switching unit 54, the control terminal of the fifth switching unit 55, the control terminal of the sixth switching unit 56, the control terminal of the seventh switching unit 57, and the control terminal of the eighth switching unit 58 are electrically connected to the same control signal line or different control signal lines. The control terminal of the first switching unit 51, the control terminal of the second switching unit 52, the control terminal of the third switching unit 53, the control terminal of the fourth switching unit 54, the control terminal of the fifth switching unit 55, the control terminal of the sixth switching unit 56, the control terminal of the seventh switching unit 57, and the control terminal of the eighth switching unit 58 are electrically connected to the same control signal line, and the complexity of wiring can be reduced.

Fig. 7 is a flowchart of a driving method of a display panel according to another embodiment of the present invention. On the basis of the above-described embodiments, as shown in fig. 3 to 7, the driving method of the display panel includes: the double-line simultaneous scanning mode includes:

Step 310, controlling the first switch unit, the third switch unit, the fifth switch unit and the seventh switch unit to be turned on.

Here, referring to fig. 6, the first, third, fifth and seventh switching units 51, 53, 55 and 57 are controlled to be turned on to input the first clock signal to the first and third clock signal lines CK1 and CK3 and to input the second clock signal to the second and fourth clock signal lines CK2 and CK 4.

Step 320, controlling the second switching unit, the fourth switching unit, the sixth switching unit and the eighth switching unit to be turned off.

Step 330, inputting a first start signal to the start signal line.

Step 340, inputting the first clock signal to the first clock signal line and the third clock signal line.

Step 350, inputting the second clock signal to the second clock signal line and the fourth clock signal line.

Step 360, the first shift register outputs the driving signal step by step.

Step 370, the second shift register outputs driving signals step by step, wherein the q-th stage of the second shift register outputs driving signals at the same time as the q-th stage of the first shift register outputs driving signals, wherein q is an integer, q is more than or equal to 1 and less than or equal to N-1, and N is the number of the first shift registers.

The single line scan mode includes:

step 380, controlling the first, third, fifth and seventh switching units to be turned off.

Step 390, controlling the second switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit to be turned on.

Here, referring to fig. 6, the second, fourth, sixth and eighth switching units 52, 54, 56 and 58 are controlled to be turned on to input the third clock signal to the first clock signal line CK1, the fourth clock signal to the second clock signal line CK2, the fifth clock signal to the third clock signal line CK3 and the sixth clock signal to the fourth clock signal line CK 4.

Step 400, inputting a second start signal to the start signal line.

Step 410, inputting a third clock signal to the first clock signal line, inputting a fourth clock signal to the second clock signal line, inputting a fifth clock signal to the third clock signal line, and inputting a sixth clock signal to the fourth clock signal line.

Step 420, the first shift register outputs the driving signal step by step.

Step 430, the second shift register outputs the driving signal step by step, wherein after the first shift register of the q-th stage outputs the driving signal, the second shift register of the q-th stage outputs the driving signal before the first shift register of the q+1-th stage outputs the driving signal.

Optionally, based on the above embodiment, fig. 8 is a timing chart of still another dual-line simultaneous scanning mode according to the embodiment of the present invention, where a duration T13 of the first level of the first clock signal overlapping with the first start signal in time is equal to a duration T11 of the first level of the first clock signal in its period, that is, t13=t11. The first level of the second clock signal does not overlap in time with the first enable signal.

Optionally, based on the above embodiment, fig. 9 is a timing chart of still another single-line scanning mode according to an embodiment of the present invention, where a duration T25 of the second level of the third clock signal overlapping the second start signal in time is equal to a duration T23 of the first level of the third clock signal in its period, that is, t25=t23. The duration T26 of the second level of the fifth clock signal overlapping in time with the second start signal is equal to the duration T24 of the fifth clock signal at the first level during its period, i.e. t26=t24. The second level of the fourth clock signal does not overlap in time with the second enable signal. The second level of the sixth clock signal does not overlap in time with the second enable signal.

Alternatively, with continued reference to fig. 8, the waveforms of the first clock signal and the second clock signal are identical and in opposite phases.

Alternatively, with continued reference to fig. 9, the waveforms of the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are the same on the basis of the above-described embodiments. Optionally, the third clock signal is in opposite phase to the fourth clock signal. Optionally, the phase of the fifth clock signal leads the phase of the fourth clock signal by 90 degrees. Optionally, the fifth clock signal is in opposite phase to the sixth clock signal.

Optionally, on the basis of the above embodiment, the period T1 of the first clock signal is smaller than the period T2 of the third clock signal, so that the scanning time of the dual-line simultaneous scanning mode is shortened, and the refresh frequency of the display screen is improved.

Alternatively, on the basis of the above embodiment, the first start signal and the second start signal are at high level, or the first start signal and the second start signal are at low level.

Optionally, the duration of the first clock signal and the second clock signal at the first level in the period thereof is equal, i.e. t12=t11. Optionally, the duration T21 of the first clock signal at the first level in its period is less than or equal to one half of its period T1.

Optionally, the duration of the first level of the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal in the period thereof is equal, i.e. t21=t22=t23=t24. Optionally, the duration T23 of the third clock signal at the second level in its period is less than or equal to one quarter of its period T2.

The embodiment of the invention provides a display device. The display device can be used for executing the driving method of the display panel provided by any embodiment of the invention. In the above embodiment, with continued reference to fig. 1, the display device includes a display panel and a timing control circuit 40.

The display panel includes: a drive circuit and a plurality of drive signal lines 30.

The driving circuit includes: the first shift register 10 group, the second shift register 20 group, the start signal line, the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4.

The first shift register 10 group includes a plurality of cascaded first shift registers 10, the first shift registers 10 being electrically connected to the first clock signal line CK1 and the second clock signal line CK 2; the starting signal end S1 of the first shift register 10 positioned at the first stage is electrically connected with a starting signal line; any one of the first shift registers 10 is electrically connected to a driving signal line 30; the different first shift registers 10 are electrically connected to different drive signal lines 30.

The second shift register 20 group includes a plurality of cascaded second shift registers 20, the second shift registers 20 being electrically connected to the third clock signal line CK3 and the fourth clock signal line CK 4; the start signal end S1 of the second shift register 20 positioned at the first stage is electrically connected with a start signal line; any one of the second shift registers 20 is electrically connected to a driving signal line 30; the second different shift register 20 is electrically connected to the different drive signal line 30; the first shift register 10 and the second shift register 20 are electrically connected to different driving signal lines 30.

The start signal line, the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4 are electrically connected to the timing control circuit 40.

The timing control circuit 40 is used for inputting a first start signal to the start signal line in the single-line scanning mode; inputting a first clock signal to the first clock signal line CK1 and the third clock signal line CK 3; the second clock signal is input to the second clock signal line CK2 and the fourth clock signal line CK 4.

The periods of the first clock signal and the second clock signal are the same, for example, T1. The first level of the first clock signal and the first level of the second clock signal do not overlap in time. The first level is the same as the level of the first enable signal, and may be a low level, for example. The duration T13 of the first level of the first clock signal overlapping in time with the first start signal is equal to the duration T11 of the first clock signal at the first level during its period, i.e. t13=t11. The first level of the second clock signal does not overlap in time with the first enable signal.

The timing control circuit 40 is further configured to input a second start signal to the start signal line in the dual-line simultaneous scanning mode; inputting a third clock signal to the first clock signal line CK 1; inputting a fourth clock signal to the second clock signal line CK 2; inputting a fifth clock signal to the third clock signal line CK 3; the sixth clock signal is input to the fourth clock signal line CK 4.

The periods of the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, for example, T2. The second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal do not overlap in time. The second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal are sequentially cyclically generated. The second level is the same as the level of the second enable signal.

The duration T25 of the second level of the third clock signal overlapping in time with the second start signal is equal to the duration T23 of the third clock signal at the first level during its period, i.e. t25=t23. The duration T26 of the second level of the fifth clock signal overlapping in time with the second start signal is equal to the duration T24 of the fifth clock signal at the first level during its period, i.e. t26=t24. The second level of the fourth clock signal does not overlap in time with the second enable signal. The second level of the sixth clock signal does not overlap in time with the second enable signal.

The display panel may be an organic light emitting display panel. The display device can be a smart phone, a notebook computer, a tablet computer, an intelligent wearable device and the like. The display device provided by the embodiment of the invention can be used for executing the driving method of the display panel provided by any embodiment of the invention, so that the display device provided by the embodiment of the invention also has the beneficial effects described in the above embodiment, and the description is omitted here.

Alternatively, with continued reference to fig. 6, the timing control circuit 40 includes a first clock signal generating circuit 41, a second clock signal generating circuit 42, a third clock signal generating circuit 43, a fourth clock signal generating circuit 44, a fifth clock signal generating circuit 45, a sixth clock signal generating circuit 46, and a control circuit 47, on the basis of the above-described embodiments.

Wherein the first clock signal generating circuit 41 is operable to generate the first clock signal. The second clock signal generation circuit 42 is operable to generate a second clock signal. The third clock signal generation circuit 43 may be configured to generate a third clock signal. The fourth clock signal generation circuit 44 is operable to generate a fourth clock signal. The fifth clock signal generation circuit 45 is operable to generate a fifth clock signal. The sixth clock signal generation circuit 46 is operable to generate a sixth clock signal. The control circuit 47 may also initiate a signal line STV connection.

Optionally, the display device further comprises a switching circuit 50.

Optionally, the switching circuit 50 includes: the first switching unit 51. The first switching unit 51 includes a first terminal, a second terminal, and a control terminal, and the first clock signal line CK1 is electrically connected to the first terminal of the first switching unit 51; a second terminal of the first switching unit 51 is electrically connected to the first clock signal generating circuit 41 or the third clock signal line CK 3.

Optionally, the switching circuit 50 includes: and a second switching unit 52. The second switching unit 52 includes a first terminal, a second terminal, and a control terminal, and the first clock signal line CK1 is electrically connected to the first terminal of the second switching unit 52; a second terminal of the second switching unit 52 is electrically connected to the third clock signal generating circuit 43.

Optionally, the switching circuit 50 includes: the third switching unit 53. The third switching unit 53 includes a first terminal, a second terminal, and a control terminal, and the second clock signal line CK2 is electrically connected to the first terminal of the third switching unit 53; a second terminal of the third switching unit 53 is electrically connected to the second clock signal generating circuit 42 or the fourth clock signal line CK 4.

Optionally, the switching circuit 50 includes: fourth switching unit 54. The fourth switch unit 54 includes a first terminal, a second terminal, and a control terminal, and the second clock signal line CK2 is electrically connected to the first terminal of the fourth switch unit 54; a second terminal of the fourth switching unit 54 is electrically connected to the fourth clock signal generation circuit 44.

Optionally, the switching circuit 50 includes: and a fifth switching unit 55. The fifth switching unit 55 includes a first terminal, a second terminal, and a control terminal, and the third clock signal line CK3 is electrically connected to the first terminal of the fifth switching unit 55; a second terminal of the fifth switching unit 55 is electrically connected to the first clock signal generation circuit 41 or the first clock signal line CK 1; at least one of the second terminal of the first switching unit 51 and the second terminal of the fifth switching unit 55 is electrically connected to the first clock signal generating circuit 41.

Optionally, the switching circuit 50 includes: a sixth switching unit 56. The sixth switching unit 56 includes a first terminal, a second terminal, and a control terminal, and the third clock signal line CK3 is electrically connected to the first terminal of the sixth switching unit 56; a second terminal of the sixth switching unit 56 is electrically connected to the fifth clock signal generation circuit 45.

Optionally, the switching circuit 50 includes: a seventh switching unit 57. The seventh switching unit 57 includes a first terminal, a second terminal, and a control terminal, and the fourth clock signal line CK4 is electrically connected to the first terminal of the seventh switching unit 57; a second terminal of the seventh switching unit 57 is electrically connected to the second clock signal generation circuit 42 or the second clock signal line CK 2; at least one of the second terminal of the third switching unit 53 and the second terminal of the seventh switching unit 57 is electrically connected to the second clock signal generating circuit 42.

Optionally, the switching circuit 50 includes: eighth switching unit 58. The eighth switching unit 58 includes a first terminal, a second terminal, and a control terminal, and the fourth clock signal line CK4 is electrically connected to the first terminal of the eighth switching unit 58; a second terminal of the eighth switching unit 58 is electrically connected to the sixth clock signal generating circuit 46.

Optionally, the switching circuit 50 includes: at least one control signal line, the control terminal of the first switching unit 51, the control terminal of the second switching unit 52, the control terminal of the third switching unit 53, the control terminal of the fourth switching unit 54, the control terminal of the fifth switching unit 55, the control terminal of the sixth switching unit 56, the control terminal of the seventh switching unit 57 and the control terminal of the eighth switching unit 58 are electrically connected to the same control signal line or different control signal lines, and the control signal lines are electrically connected to the control circuit 47.

The control circuit 47 is configured to control the first switching unit 51, the third switching unit 53, the fifth switching unit 55, and the seventh switching unit 57 to be turned on in the double-line simultaneous scanning mode; controlling the second, fourth, sixth and eighth switching units 52, 54, 56, 58 to be turned off; in the single-line scanning mode, the first, third, fifth, and seventh switching units 51, 53, 55, and 57 are controlled to be turned off; the second switching unit 52, the fourth switching unit 54, the sixth switching unit 56, and the eighth switching unit 58 are controlled to be turned on.

Alternatively, with continued reference to fig. 6, the switching circuit 50, the driving circuit, and the plurality of driving signal lines 30 are disposed in the array substrate of the display panel on the basis of the above-described embodiments. The switching circuit 50 and the driving circuit may be located in the non-display area 3 of the display panel 1. The plurality of driving signal lines 30 may be located in the display area 2 of the display panel 1.

Alternatively, the switching circuit 50 is integrated in the same chip as the timing control circuit 40 on the basis of the above-described embodiment.

Alternatively, the driving circuit is a scan driving circuit, and the driving signal line 30 is a scan line.

Alternatively, the driving circuit is a light emission control circuit, and the driving signal line 30 is a light emission control line.

Optionally, any first shift register 10 includes a first clock signal input CK, a second clock signal input XCK, a start signal terminal S1 and a trigger signal terminal S2, the start signal terminal S1 of the i-th first shift register 10 is electrically connected to the trigger signal terminal S2 of the i+1th first shift register 10, where i is an integer,

n is the number of the first shift registers 10, and N is more than or equal to 2.

The first clock signal input CK of the 2k+1 th first shift register 10 is electrically connected to the first clock signal line CK 1; wherein k is an integer,

the method comprises the steps of carrying out a first treatment on the surface of the The second clock signal input XCK of the 2k+1 th first shift register 10 is electrically connected to the second clock signal line CK 2; the first clock signal input CK of the 2k+2 th first shift register 10 is electrically connected to the second clock signal line CK 2; the second clock signal input XCK of the 2k+2 first shift register 10 is electrically connected to the first clock signal line CK 1.

Optionally, any second shift register 20 includes a first clock signal input CK, a second clock signal input XCK, a start signal terminal S1 and a trigger signal terminal S2, the start signal terminal S1 of the jth second shift register 20 is electrically connected to the trigger signal terminal S2 of the jth (1) th first shift register 10, where j is an integer,

M is the number of the second shift registers 20, M is equal to or greater than 2, M=N, or N-M=1.

The first clock signal input CK of the 2p+1 th first shift register 10Is electrically connected with the third clock signal line CK 3; wherein, p is an integer,

the method comprises the steps of carrying out a first treatment on the surface of the The second clock signal input XCK of the 2p+1 th second shift register 20 is electrically connected to the fourth clock signal line CK 4; the first clock signal input CK of the 2p+2 th second shift register 20 is electrically connected to the fourth clock signal line CK 4; the second clock signal input XCK of the 2p+2 second shift register 20 is electrically connected to the third clock signal line CK 3.

Alternatively, with continued reference to fig. 6 based on the above embodiment, the first switching unit 51 includes an N-type thin film transistor, the second switching unit 52 includes a P-type thin film transistor, the third switching unit 53 includes an N-type thin film transistor, the fourth switching unit 54 includes a P-type thin film transistor, the fifth switching unit 55 includes an N-type thin film transistor, the sixth switching unit 56 includes a P-type thin film transistor, the seventh switching unit 57 includes an N-type thin film transistor, and the eighth switching unit 58 includes a P-type thin film transistor.

Alternatively, on the basis of the above embodiment, fig. 10 is a schematic structural diagram of still another display device according to an embodiment of the present invention, where the first switch unit 51 includes a P-type thin film transistor, the second switch unit 52 includes an N-type thin film transistor, the third switch unit 53 includes a P-type thin film transistor, the fourth switch unit 54 includes an N-type thin film transistor, the fifth switch unit 55 includes a P-type thin film transistor, the sixth switch unit 56 includes an N-type thin film transistor, the seventh switch unit 57 includes a P-type thin film transistor, and the eighth switch unit 58 includes an N-type thin film transistor.

Optionally, based on the foregoing embodiment, fig. 11 is a schematic structural diagram of another display device according to an embodiment of the present invention, where the first shift register set and the second shift register set are located on opposite sides of the driving signal line.

Optionally, based on the foregoing embodiment, fig. 12 is a schematic structural diagram of a first shift register according to an embodiment of the present invention. The first shift register includes: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the first capacitor C1, and the second capacitor C2. The start signal terminal S1 is electrically connected to the first pole of the first transistor M1; the first pole of the third transistor M3, the control pole of the fourth transistor M4, and the first pole of the eighth transistor M8 are all electrically connected to the second pole of the first transistor M1; the control electrode of the first transistor M1 and the second electrode of the fourth transistor M4 are electrically connected with the first clock signal input end CK; the control electrode of the third transistor M3 and the first electrode of the sixth transistor M6 are electrically connected to the second clock signal input XCK; the first pole of the second transistor M2, the first pole of the first capacitor C1, and the first pole of the seventh transistor M7 are electrically connected to the first potential signal input terminal VD; a control electrode of the eighth transistor M8, and a first electrode of the fifth transistor M5 are electrically connected to the second potential signal input terminal VE; the second pole of the third transistor M3 is electrically connected to the second pole of the second transistor M2; the control electrode of the second transistor M2, the second electrode of the fourth transistor M4, the second electrode of the first capacitor C1, and the second electrode of the fifth transistor are electrically connected to the control electrode of the seventh transistor M7; the second pole of the eighth transistor M8, and the first pole of the second capacitor C2 are electrically connected to the control pole of the sixth transistor; the second pole of the sixth transistor M6, the second pole of the second capacitor C2, and the second pole of the seventh transistor M7 are electrically connected to the driving signal output terminal (also referred to as the trigger signal terminal S2). The first transistor M1 may be a double gate transistor.

It should be noted that fig. 12 illustrates a case where the first transistor M1 to the eighth transistor M8 are P-type transistors, and the timing chart corresponding to the solution of fig. 12 may be fig. 5. The first potential signal input terminal VD may have a higher potential than the second potential signal input terminal VE. The potential of the first potential signal input terminal VD is logically opposite to the potential of the second potential signal input terminal VE.

Alternatively, the first to eighth transistors M1 to M8 may be N-type transistors. The corresponding timing diagram can be obtained by inverting the level of each time of the waveform of each end signal in fig. 5. The potential of the first potential signal input terminal VD may be lower than the potential of the second potential signal input terminal VE. At this time, the level of each time of the waveform of each end signal in fig. 3, 4, 8, and 9 needs to be inverted.

Alternatively, the display panel may further include a first potential signal line and a second potential signal line. The first potential signal input ends of the first shift register and the second shift register are electrically connected with the first potential signal line. The second potential signal input ends of the first shift register and the second shift register are electrically connected with the second potential signal line.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A driving method of a display panel, wherein the display panel includes a driving circuit and a plurality of driving signal lines;

the first shift register group comprises a plurality of cascaded first shift registers, and the first shift registers are electrically connected with the first clock signal line and the second clock signal line; the starting signal end of the first shift register positioned at the first stage is electrically connected with the starting signal line; any one of the first shift registers is electrically connected with one of the driving signal lines; the different first shift registers are electrically connected with different driving signal lines;

the second shift register group comprises a plurality of cascaded second shift registers, and the second shift registers are electrically connected with the third clock signal line and the fourth clock signal line; the starting signal end of the second shift register positioned at the first stage is electrically connected with the starting signal line; any one of the second shift registers is electrically connected with one of the driving signal lines; the different second shift registers are electrically connected with different driving signal lines; the first shift register and the second shift register are electrically connected to different driving signal lines;

The driving method includes: a single line scanning mode and a double line simultaneous scanning mode;

the dual-line simultaneous scanning mode includes:

inputting a first start signal to the start signal line;

inputting a second clock signal to the second clock signal line and the fourth clock signal line, wherein the first clock signal has the same period as the second clock signal, the first level of the first clock signal and the first level of the second clock signal do not overlap in time, and the first level is the same as the first start signal, and is generated in a cycle of the first level of the first clock signal and the first level of the second clock signal in order;

the first shift register outputs driving signals step by step;

the second shift register outputs driving signals step by step, wherein the q-th stage second shift register outputs driving signals at the same time when the q-th stage first shift register outputs driving signals, q is an integer, q is more than or equal to 1 and less than or equal to N-1, and N is the number of the first shift registers;

the single line scan mode includes:

Inputting a second start signal to the start signal line;

inputting a third clock signal to the first clock signal line;

inputting a fourth clock signal to the second clock signal line;

inputting a fifth clock signal to the third clock signal line;

inputting a sixth clock signal to the fourth clock signal line, wherein the periods of the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are the same, and the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal do not overlap in time; cyclically generating in the order of the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal; the second level is the same as the level of the second start signal;

the first shift register outputs driving signals step by step;

the second shift register outputs the driving signal step by step, wherein after the first shift register of the q-th stage outputs the driving signal, the second shift register of the q-th stage outputs the driving signal before the first shift register of the q+1-th stage outputs the driving signal.

2. The driving method of a display panel according to claim 1, wherein the first clock signal and the second clock signal have the same waveform and opposite phases;

the waveforms of the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are the same, and the phases of the third clock signal and the fourth clock signal are opposite; the phase of the fifth clock signal leads the phase of the fourth clock signal by 90 degrees; the fifth clock signal is in opposite phase to the sixth clock signal.

3. The driving method of a display panel according to claim 1, wherein a period of the first clock signal is smaller than a period of the third clock signal.

4. The driving method of the display panel according to claim 1, wherein the first start signal and the second start signal are at a high level or the first start signal and the second start signal are at a low level;

the time duration of the first level of the first clock signal and the first starting signal overlapped in time is equal to the time duration of the first level of the first clock signal in the period of the first clock signal, and the first level of the second clock signal and the first starting signal are not overlapped in time; the duration of the first clock signal and the second clock signal in the period of the first clock signal is equal to the duration of the first level; the duration of the first clock signal at the first level in the period is less than or equal to one half of the period;

The time duration of the second level of the third clock signal overlapped with the second starting signal in time is equal to the time duration of the first level of the third clock signal in the period; the time duration of the second level of the fifth clock signal overlapping the second start signal in time is equal to the time duration of the fifth clock signal at the first level in the period; the second level of the fourth clock signal does not overlap in time with the second enable signal; the second level of the sixth clock signal does not overlap in time with the second enable signal; the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal have the same duration of the first level in the period; the duration of the third clock signal at the second level in its period is less than or equal to one quarter of its period.

5. The driving method of a display panel according to claim 1, wherein the display panel further comprises:

the first switch unit comprises a first end, a second end and a control end, and the first clock signal line is electrically connected with the first end of the first switch unit; the second end of the first switch unit is used for receiving the first clock signal;

The second switch unit comprises a first end, a second end and a control end, and the first clock signal line is electrically connected with the first end of the second switch unit; the second end of the second switch unit is used for receiving the third clock signal;

the second clock signal line is electrically connected with the first end of the third switch unit; the second end of the third switch unit is used for receiving the second clock signal;

the fourth switch unit comprises a first end, a second end and a control end, and the second clock signal line is electrically connected with the first end of the fourth switch unit; the second end of the fourth switch unit is used for receiving the fourth clock signal;

the fifth switch unit comprises a first end, a second end and a control end, and the third clock signal line is electrically connected with the first end of the fifth switch unit; a second end of the fifth switch unit is used for receiving the first clock signal;

the sixth switch unit comprises a first end, a second end and a control end, and the third clock signal line is electrically connected with the first end of the sixth switch unit; the second end of the sixth switching unit is used for receiving the fifth clock signal;

The seventh switch unit comprises a first end, a second end and a control end, and the fourth clock signal line is electrically connected with the first end of the seventh switch unit; a second end of the seventh switch unit is used for receiving the second clock signal;

an eighth switching unit including a first terminal, a second terminal, and a control terminal, the fourth clock signal line being electrically connected to the first terminal of the eighth switching unit; a second end of the eighth switching unit is used for receiving the sixth clock signal;

at least one control signal line, the control end of the first switch unit, the control end of the second switch unit, the control end of the third switch unit, the control end of the fourth switch unit, the control end of the fifth switch unit, the control end of the sixth switch unit, the control end of the seventh switch unit and the control end of the eighth switch unit are electrically connected to the same control signal line or different control signal lines;

the single line scan mode further includes:

controlling the first, third, fifth and seventh switching units to be turned on;

controlling the second, fourth, sixth and eighth switching units to be turned off;

The dual-line simultaneous scanning mode further includes:

controlling the first, third, fifth and seventh switching units to be turned off;

and controlling the second switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit to be conducted.

6. A display device is characterized by comprising a display panel and a time sequence control circuit;

the start signal line, the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are electrically connected to the timing control circuit;

the time sequence control circuit is used for inputting a first starting signal to the starting signal line in a double-row simultaneous scanning mode; inputting a first clock signal to the first clock signal line and the third clock signal line; inputting a second clock signal to the second clock signal line and the fourth clock signal line, wherein the first clock signal has the same period as the second clock signal, the first level of the first clock signal and the first level of the second clock signal do not overlap in time, and the first level is the same as the first start signal, and is generated in a cycle of the first level of the first clock signal and the first level of the second clock signal in order; the first shift register outputs driving signals step by step; the second shift register outputs driving signals step by step, wherein the q-th stage second shift register outputs driving signals at the same time when the q-th stage first shift register outputs driving signals, q is an integer, q is more than or equal to 1 and less than or equal to N-1, and N is the number of the first shift registers; in a single-line scanning mode, inputting a second start signal to the start signal line; inputting a third clock signal to the first clock signal line; inputting a fourth clock signal to the second clock signal line; inputting a fifth clock signal to the third clock signal line; inputting a sixth clock signal to the fourth clock signal line, wherein the periods of the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are the same, and the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal do not overlap in time; cyclically generating in the order of the second level of the third clock signal, the second level of the fifth clock signal, the second level of the fourth clock signal, and the second level of the sixth clock signal; the first shift register outputs driving signals step by step; the second shift register outputs the driving signal step by step, wherein after the first shift register of the q-th stage outputs the driving signal, the second shift register of the q-th stage outputs the driving signal before the first shift register of the q+1-th stage outputs the driving signal.

7. The display device according to claim 6, wherein the timing control circuit includes a first clock signal generation circuit, a second clock signal generation circuit, a third clock signal generation circuit, a fourth clock signal generation circuit, a fifth clock signal generation circuit, a sixth clock signal generation circuit, and a control circuit;

the display device further includes a switching circuit including:

the first switch unit comprises a first end, a second end and a control end, and the first clock signal line is electrically connected with the first end of the first switch unit; a second end of the first switch unit is electrically connected with the first clock signal generating circuit or the third clock signal line;

the second switch unit comprises a first end, a second end and a control end, and the first clock signal line is electrically connected with the first end of the second switch unit; the second end of the second switch unit is electrically connected with the third clock signal generation circuit;

the second clock signal line is electrically connected with the first end of the third switch unit; a second end of the third switching unit is electrically connected with the second clock signal generating circuit or the fourth clock signal line;

The fourth switch unit comprises a first end, a second end and a control end, and the second clock signal line is electrically connected with the first end of the fourth switch unit; the second end of the fourth switch unit is electrically connected with the fourth clock signal generation circuit;

the fifth switch unit comprises a first end, a second end and a control end, and the third clock signal line is electrically connected with the first end of the fifth switch unit; a second end of the fifth switching unit is electrically connected with the first clock signal generating circuit or the first clock signal line; at least one of the second terminal of the first switching unit and the second terminal of the fifth switching unit is electrically connected to the first clock signal generating circuit;

the sixth switch unit comprises a first end, a second end and a control end, and the third clock signal line is electrically connected with the first end of the sixth switch unit; the second end of the sixth switching unit is electrically connected with the fifth clock signal generating circuit;

the seventh switch unit comprises a first end, a second end and a control end, and the fourth clock signal line is electrically connected with the first end of the seventh switch unit; a second terminal of the seventh switching unit is electrically connected to the second clock signal generating circuit or the second clock signal line; at least one of the second terminal of the third switching unit and the second terminal of the seventh switching unit is electrically connected to the second clock signal generating circuit;

An eighth switching unit including a first terminal, a second terminal, and a control terminal, the fourth clock signal line being electrically connected to the first terminal of the eighth switching unit; the second end of the eighth switch unit is electrically connected with the sixth clock signal generation circuit;

at least one control signal line, the control end of the first switch unit, the control end of the second switch unit, the control end of the third switch unit, the control end of the fourth switch unit, the control end of the fifth switch unit, the control end of the sixth switch unit, the control end of the seventh switch unit and the control end of the eighth switch unit are electrically connected to the same control signal line or different control signal lines, and the control signal lines are electrically connected with the control circuit;

the control circuit is used for controlling the first switch unit, the third switch unit, the fifth switch unit and the seventh switch unit to be conducted in the double-row simultaneous scanning mode; controlling the second, fourth, sixth and eighth switching units to be turned off; controlling the first, third, fifth and seventh switching units to be turned off in the single-line scanning mode; and controlling the second switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit to be conducted.

8. The display device according to claim 7, wherein the switching circuit, the driving circuit, and the plurality of driving signal lines are provided in an array substrate of a display panel, or wherein the switching circuit and the timing control circuit are integrated in the same chip.

9. The display device according to claim 6, wherein the driving circuit is a scanning driving circuit, and wherein the driving signal line is a scanning line;

or the driving circuit is a light-emitting control circuit, and the driving signal line is a light-emitting control line.

10. The display device according to claim 6, wherein any one of the first shift registers includes a first clock signal input terminal, a second clock signal input terminal, a start signal terminal, and a trigger signal terminal, the start signal terminal of the i-th first shift register is electrically connected to the trigger signal terminal of the i+1th first shift register, wherein i is an integer, 1 is less than or equal to i < N, N is the number of the first shift registers, and N is more than or equal to 2;

the first clock signal input end of the 2k+1 first shift register is electrically connected with the first clock signal line; wherein k is an integer, and k is more than or equal to 0 and less than or equal to N/2-1; the second clock signal input end of the 2k+1 first shift register is electrically connected with the second clock signal line; the first clock signal input end of the 2k+2 first shift register is electrically connected with the second clock signal line; the second clock signal input end of the 2k+2 first shift register is electrically connected with the first clock signal line;

Any one of the second shift registers comprises a first clock signal input end, a second clock signal input end, a starting signal end and a triggering signal end, wherein the starting signal end of the j-th second shift register is electrically connected with the triggering signal end of the j+1th first shift register, j is an integer, i < M is 1-2, M=N or N-M=1;

the first clock signal input end of the 2p+1 first shift register is electrically connected with the third clock signal line; wherein, p is an integer, p is more than or equal to 0 and less than or equal to M/2-1; the second clock signal input end of the 2p+1 second shift register is electrically connected with the fourth clock signal line; the first clock signal input end of the 2p+2 second shift register is electrically connected with the fourth clock signal line; the second clock signal input end of the 2p+2 second shift register is electrically connected with the third clock signal line.