CN114500767A - Input video source adjusting method and device, video input card and video processing equipment - Google Patents
Input video source adjusting method and device, video input card and video processing equipment Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
Abstract
The embodiment of the invention relates to an input video source adjusting method, which comprises the following steps: acquiring a clock cycle of an input video source and determining a plurality of continuous clock phases according to the clock cycle; sequentially adjusting the clock phase of the input video source to be the plurality of clock phases and sampling the input video source based on the current clock phase in the plurality of clock phases to obtain a plurality of sampling data groups; acquiring test reference data of a test reference source; respectively detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of corresponding detection results; determining a target clock phase according to the plurality of detection results; adjusting the clock phase of the input video source to the target clock phase; in the embodiment, the dynamic adjustment of the clock phase of the input video source is realized by determining and detecting a plurality of clock phases and obtaining the target clock phase according to the detection result.
Description
Technical Field
The invention relates to the technical field of display, in particular to an input video source adjusting method, an input video source adjusting device, a video input card and video processing equipment.
Background
In the LED industry, a video source is connected to a video input card, then is output to an output card through the video input card, and then is output to an LED display screen through the output card for display.
When different video sources need to be replaced, a user needs to manually modify the clock phase of the video input card to achieve the purpose that the video sources can be stably output to the LED display screen.
However, since the clock phase of the video input card is fixed, when different video sources are switched to, the different video sources may have compatibility problems after being output through the video input card, the quality output to the LED display screen does not meet the standard or is not stable enough, and the video input card cannot be adjusted in real time, resulting in poor compatibility of the video input card.
Disclosure of Invention
Therefore, to overcome at least some of the defects and shortcomings in the prior art, embodiments of the present invention provide an input video source adjusting method, an input video source adjusting device, a video input card and a video processing apparatus.
On one hand, an input video source adjusting method provided by the embodiment of the invention includes: acquiring a clock cycle of the input video source and determining a plurality of continuous clock phases according to the clock cycle; sequentially adjusting the clock phase of the input video source to be the plurality of clock phases and sampling the input video source based on the current clock phase in the plurality of clock phases to obtain a plurality of sampling data groups; acquiring test reference data of a test reference source; respectively detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of detection results which correspond to one another one by one; determining a target clock phase according to the plurality of detection results; and adjusting the clock phase of the input video source to the target clock phase.
Because the clock phase needs to be manually determined and fixed in the prior art, when an input source is changed and the compatibility problem occurs, dynamic adjustment cannot be performed, and the compatibility is poor. The invention firstly obtains the clock period of the input video source, determines a plurality of clock phases, then sequentially and respectively samples the plurality of clock phases for detection, and finally obtains the target clock phase through whether the detection result is correct, wherein the target clock phase is the optimal clock phase of the input video source, thereby realizing the dynamic adjustment of the clock phase of the input video source and improving the compatibility of the video input card.
In one embodiment of the present invention, the plurality of clock phases includes a first clock phase, the plurality of sample data groups includes a first sample data group, the first sample data group includes first video data and a first synchronization signal; sequentially adjusting the clock phase of the input video source to the plurality of clock phases and sampling the input video source based on a current clock phase of the plurality of clock phases to obtain a plurality of sampled data sets comprises: adjusting the current clock phase of the input video source to the first clock phase; and sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
In one embodiment of the invention, the plurality of detection results comprises a first detection result; the detecting the plurality of sampling data groups respectively according to the test reference data to obtain a plurality of detection results in one-to-one correspondence, including: comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result; judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signal in the first sampling data group are the same and/or the frame rates are the same to obtain a first synchronous signal detection result; and determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
In an embodiment of the present invention, the determining the target clock phase according to the plurality of detection results includes: judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value; and when the counting value reaches a correct detection result quantity threshold value, taking a clock phase corresponding to a target detection result in the continuous correct detection results as the target clock phase.
In one embodiment of the present invention, the clock period is generated by the resolution of the input video source and the output mode of the interface chip.
On the other hand, an embodiment of the present invention provides an input video source adjusting apparatus, adapted to perform the input video source adjusting method according to any one of the preceding claims, and including: the clock period acquisition module is used for acquiring the clock period of an input video source and determining a plurality of continuous clock phases according to the clock period; a sampling data obtaining module, configured to sequentially adjust a clock phase of the input video source to be the multiple clock phases and sample the input video source based on a current clock phase of the multiple clock phases to obtain multiple sampling data sets; the reference data acquisition module is used for acquiring test reference source test reference data; a detection result obtaining module, configured to respectively detect the multiple sampling data sets according to the test reference data to obtain multiple detection results that correspond to each other; a clock phase determining module, configured to determine a target clock phase according to the multiple detection results; and the clock phase adjusting module is used for adjusting the clock phase of the input video source to the target clock phase.
In another aspect, an embodiment of the present invention provides a first video input interface, configured to access an input video source and a test reference source; the communication interface is used for receiving an input video source adjusting instruction; the programmable logic device is connected with the first video input interface and the communication interface; wherein the programmable logic device is configured to perform the input video source adjustment method of any of the preceding claims.
In one embodiment of the invention, the programmable logic device comprises: the device comprises a hybrid clock management module, a data sampling module, a data detection module and a hybrid clock management configuration module; the hybrid clock management configuration module is configured to obtain the input video source adjustment instruction through the communication interface, obtain the clock cycle of the input video source, and determine the multiple continuous clock phases according to the clock cycle; the hybrid clock management module is used for sequentially adjusting the clock phases of the input video source into the plurality of clock phases; the data sampling module is configured to sample the input video source based on the current clock phase of the multiple clock phases to obtain multiple sampling data sets, and obtain the test reference data of the test reference source through the first video input interface; the data detection module is used for respectively detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of detection results in one-to-one correspondence; the hybrid clock management configuration module is further configured to determine the target clock phase according to the plurality of detection results; the hybrid clock management module is further configured to adjust a clock phase of the input video source to the target clock phase.
In one embodiment of the present invention, the data detection module includes a video data detection unit and a synchronization signal detection unit; the video data detection unit is used for comparing whether the video data in the plurality of sampling data groups are the same one by one according to the test reference data to obtain a plurality of video data detection results; the synchronous signal detection unit is used for judging whether the resolutions of the multi-frame continuous pictures of the synchronous signals in the plurality of sampling data groups are the same and/or the frame rates are the same one by one to obtain a plurality of synchronous signal detection results.
In a further aspect, an embodiment of the present invention provides a video processing apparatus, including: the video input card of any of the preceding claims; and the master control card is connected with the communication interface of the video input card.
In another aspect, an embodiment of the present invention provides an input video source processing system, including: a processor and a memory coupled to the processor; wherein the memory stores instructions for execution by the processor, and the instructions cause the processor to perform operations to perform any of the aforementioned input video source adjustment methods.
In still another aspect, an embodiment of the present invention provides a computer-readable storage medium, which is a non-volatile memory and stores program code, and when the program code is executed by a computer, the method for adjusting an input video source is implemented by any one of the foregoing input video source adjusting methods.
As can be seen from the above, the above technical features of the present invention may have one or more of the following advantages:
1. according to the embodiment of the invention, firstly, the clock period of an input video source is obtained, a plurality of clock phases are determined, then the plurality of clock phases are sequentially and respectively sampled and detected, and finally, a target clock phase is obtained through a detection result, wherein the target clock phase is the optimal clock phase of the input video source, so that the dynamic adjustment of the clock phase of the input video source is realized, and the compatibility of a video input card is improved;
2. in the embodiment of the invention, the video input card can use different clock phases by accessing different input video sources, thereby effectively improving the compatibility of the video input card.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart illustrating steps of an input video source adjusting method according to a first embodiment of the present invention.
Fig. 2 is a flowchart illustrating a specific step of step S102 in the input video source adjusting method shown in fig. 1.
Fig. 3 is a flowchart illustrating a specific step of step S104 in the input video source adjusting method shown in fig. 1.
Fig. 4 is a flowchart illustrating a specific step of step S105 in the input video source adjusting method shown in fig. 1.
Fig. 5 is a diagram illustrating an exemplary method for adjusting an input video source according to an embodiment of the present invention.
Fig. 6 is a block diagram of an input video source adjusting apparatus according to a second embodiment of the present invention.
Fig. 7A is a schematic structural diagram of a video input card according to a third embodiment of the present invention.
Fig. 7B is a schematic structural diagram of a programmable logic device according to a third embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a video processing apparatus according to a fourth embodiment of the present invention.
Fig. 9 is a schematic structural diagram of an input video source adjusting system according to a fifth embodiment of the present invention.
FIG. 10 is a diagram illustrating a computer-readable storage medium according to a sixth embodiment of the present invention
[ brief description of the drawings ]
S101-S106, S201-S202, S301-S303, S401-S402: inputting a video source adjusting method;
600: inputting a video source adjusting device; 601: a clock period acquisition module; 602: a sampled data obtaining module; 603: a reference data acquisition module; 604: a detection result obtaining module; 605: a clock phase determination module; 606: a clock phase adjustment module; 6021: a clock phase adjustment unit; 6022: a video source sampling unit; 6041: a video data obtaining unit; 6042: a synchronization signal obtaining unit; 6043: a detection result determination unit; 6051: a count value obtaining unit; 6052: a clock phase determination unit;
700: a video input card; 701: a first video input interface; 703: a communication interface; 704: a programmable logic device; 7041: a hybrid clock management module; 7042: a data sampling module; 7043: a data detection module; 7044: a hybrid clock pipeline configuration module; 70431: a video data detection unit; 70432: a synchronization signal detection unit;
800: a video processing device; 801: a video input card; 802: a master control card; 8011: a communication interface;
900: inputting a video source regulating system; 901: a processor; 903: a memory;
1000: a computer readable storage medium.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In this embodiment, the input video source adjusting method is performed in the video input card. The video input card comprises a plurality of interfaces, an interface chip and a programmable logic device.
The video input interface is used for accessing a plurality of input video sources, and the communication interface is used for receiving an input video source adjusting instruction; in this embodiment, the adjustment instruction is a clock phase adjustment instruction, in other embodiments, the adjustment instruction may be a frequency adjustment instruction or other adjustment function instruction, and different adjustment instructions may be set according to an actual situation, which is not limited herein.
The interface chip is used for converting a video source accessed by the video input interface into video data and then inputting the video data to the programmable logic device, and the programmable logic device is used for executing the input video source adjusting method in the embodiment.
[ first embodiment ] A method for manufacturing a semiconductor device
As shown in fig. 1, a first embodiment of the present invention provides an input video source adjusting method, for example, including:
s101, acquiring a clock cycle of an input video source and determining a plurality of continuous clock phases according to the clock cycle;
s102, sequentially adjusting the clock phase of the input video source to be the plurality of clock phases and sampling the input video source based on the current clock phase in the plurality of clock phases to obtain a plurality of sampling data groups;
s103, acquiring test reference data of a test reference source;
s104, respectively detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of detection results in one-to-one correspondence;
s105, determining a target clock phase according to the detection results;
and S106, adjusting the clock phase of the input video source to the target clock phase.
Because the clock phase needs to be manually determined and fixed in the prior art, when an input source is changed and the compatibility problem occurs, dynamic adjustment cannot be performed, and the compatibility is poor. According to the invention, firstly, the clock period of the input video source is obtained, a plurality of clock phases are determined, then the plurality of clock phases are respectively sampled and detected in sequence, and finally, the target clock phase is obtained through the detection result, wherein the target clock phase is the optimal clock phase of the input video source, so that the dynamic adjustment of the clock phase of the input video source is realized, and the compatibility is improved.
It should be noted here that, for the access sequence of the input video source and the test reference source, it may be, for example, before adjusting the clock phase and sampling the data of the input video source, first access the test reference source through the video input interface and obtain the test reference data at the initial clock phase and store it on the video input card, for example, on the non-volatile memory thereon or directly store it in the programmable logic device in the video input card, for example, on the internal RAM thereof, then access the input video source through the video input interface, and start to sample the data of the input video source, and perform dynamic adjustment of the clock phase according to the test reference data of the test reference source obtained by sampling and the sampled data of the input video source; of course, it may also be that an input video source is accessed through the video input interface, the input video source is subjected to clock phase division to obtain a plurality of clock phases, and then adjusted to a current clock phase of the plurality of clock phases, the input video source is subjected to data sampling based on the current clock phase and sample data is recorded, then a test reference source is accessed through the video input interface, test reference data is obtained at an initial clock phase and stored on the video input card, and finally detection and clock phase dynamic adjustment are performed according to the test reference data of the test reference source obtained by sampling and the sample data of the input video source; even, the input video source may be accessed through one video input interface, the input video source is subjected to clock phase division to obtain a plurality of clock phases, the clock phases are adjusted to the current clock phase of the plurality of clock phases, data sampling is performed on the input video source based on the current clock phase, sampling data is recorded, a test reference source is accessed through another interface, test reference data is obtained at the initial clock phase and stored on the video input card, and dynamic adjustment of the clock phases is performed according to the test reference data of the test reference source obtained through sampling and the sampling data of the input video source, which is not limited by the present invention.
The input video source adjusting method in this embodiment has a plurality of application scenarios, for example, when a video input card is corrected for the first time before shipping and when a video source is accessed, it is found that the video input card has a compatibility problem.
In step S101, a clock cycle of the input video source is obtained and a plurality of consecutive clock phases are determined according to the clock cycle, in this embodiment, one clock cycle is equally divided into a plurality of equal clock phases according to the clock cycle of the input video source; in other embodiments, a clock period is equally divided into a plurality of unequal clock phases according to a clock period of the input video source, which is not limited herein. And the clock period is generated by the programmable logic device according to the resolution of the input video source and the output mode of the interface chip.
In step S102, the plurality of sample data groups include, for example, a plurality of video data and a plurality of synchronization signals, and the synchronization signals include: a field sync signal VS, a line sync signal HS and an active display data signal DE. The video data is, for example, image data of an input video source, such as data represented in RGB format.
In step S104, the plurality of detection results include, for example: video data detection results and synchronization signal detection results.
In step S106, the clock phase of the input video source is adjusted to the target clock phase, and after the target clock phase is determined, since the plurality of equally divided clock phases need to be detected, when adjusting, the current clock phase is the last clock phase of the plurality of clock phases, that is, the current clock phase is adjusted to the target clock phase from the last clock phase by one step. For example, the clock period is equally divided into 32 clock phases, and then the target clock phase obtained through a plurality of detection results is the 18 th clock phase, so that the clock period is directly adjusted from the 32 th clock phase which is the last clock phase in the plurality of clock phases to the 18 th clock phase, which is equivalent to moving the clock period from the position of the 32 th clock phase to the position of the 18 th clock phase, and the phase adjustment work is completed.
In another specific embodiment, as shown in fig. 2, the plurality of clock phases includes a first clock phase, the plurality of sample data sets includes a first sample data set, the first sample data set includes first video data and a first synchronization signal, and the step S102 includes:
s201, adjusting the current clock phase of the input video source to be the first clock phase;
s202, sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
In another specific embodiment, as shown in fig. 3, the plurality of detection results includes a first detection result, and the step 104 includes, for example:
s301, comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result;
s302, judging whether the resolutions of multiple continuous frames of the first synchronous signal in the first sampling data group are the same and/or the frame rates are the same to obtain a first synchronous signal detection result;
s303, determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
Judging whether the first synchronous signal in the first sampling data group comprises three signals of a field synchronous signal VS, a line synchronous signal HS and an effective display data signal DE in the first synchronous signal, and judging whether the resolutions of the field synchronous signal VS, the line synchronous signal HS and the effective display data signal DE under continuous pictures of multiple frames are the same and/or the frame rates are the same; wherein the resolution of the plurality of frames of consecutive pictures comprises: judging whether the resolutions of a plurality of continuous pictures are the same, namely judging whether the data and the quantity of the pixel points in the rows of the frame picture data and/or the columns of the frame picture data are the same, and obtaining a first synchronous signal detection result; judging whether the frame rates are the same comprises the following steps: the time intervals between a preset number of adjacent frame pictures in the input video source are compared within a continuous time, such as 250 milliseconds, for example, the time interval between a first frame picture and a second frame picture is compared with the time interval between the second frame picture and a third frame picture, and whether the two time intervals are the same or not is judged.
In another specific embodiment, as shown in fig. 4, the step S105 includes, for example:
s401, judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value;
s402, when the counting value reaches a threshold value of the number of correct detection results, taking a clock phase corresponding to a target detection result in the continuous correct detection results as the target clock phase.
In step S401, the first detection result is determined by the first video data detection result and the first synchronization signal detection result, and when the video data detection result is the same and the synchronization signal detection result is the same, the first detection result is correct, otherwise, the first detection result is incorrect.
In step S402, the correct detection result number threshold may be set manually, or may be set through a command sent by an upper computer or other main control card, for example, to determine that 15% of the number of the plurality of clock phases is used as the correct detection result number threshold, for example, to determine that the number of the clock phases is 32, the correct detection result number threshold is 5.
In step S402, the target detection result is a detection result at an intermediate position in the consecutive correct detection results, for example, if the count of the consecutive correct detection results is 5 count values, the target detection result is a third intermediate detection result, that is, if the count of the consecutive correct detection results is an odd number, the target detection result takes an intermediate value in the count values; if the count of the consecutive correct detection results is 6 count values, the target detection result is selected from one of the middle third and fourth detection results as the target detection result, that is, when the count value of the consecutive correct detection results is an even number, the target detection result may be any one of the middle two values in the count values.
For better understanding of the present embodiment, the following describes the input video source adjusting method of the present embodiment in detail with reference to the specific embodiment of fig. 5.
In this embodiment, the execution main body is a programmable logic device (also called FPGA) in the video input card. In the following, the implementation of the input video source adjusting method provided by the embodiment of the present invention will be described in detail.
As shown in fig. 5, an embodiment of the present invention provides a specific method for adjusting an input video source, including:
the method includes the steps that an FPGA acquires an input video source adjusting instruction, wherein the input video source adjusting instruction can be sent by an upper computer or an adjusting instruction issued by a main control card and can be determined according to actual conditions, and the specific situation is not limited here.
Then, the clock period of the input video source is obtained according to the input video source adjustment instruction, and the clock period is equally divided into a plurality of consecutive clock phases.
The FPGA sequentially adjusts the clock phase of an input video source into 32 continuous clock phases, performs video data sampling and synchronous signal sampling on the input video source based on the current clock phase in the 32 clock phases, for example, adjusts the clock phase to be a first clock phase, then samples the input video source based on the first clock phase to obtain first video data and a first synchronous signal, then adjusts the clock phase to be a second clock phase, then obtains second video data and a second synchronous signal based on the second clock phase, and sequentially samples the 32 clock phases to obtain 32 sampling data groups and records the 32 sampling data groups, wherein each sampling data group comprises video data and a synchronous signal. The sampling synchronization signal is three signals of a field synchronization signal VS, a line synchronization signal HS and an effective display data signal DE, and in other embodiments, the sampling synchronization signal may be other synchronization signals, which is not limited herein. The video data is image data of an input video source, for example, image data expressed in RGB format.
After the FPGA samples video data and a synchronization signal of the input video source based on a current clock phase of the 32 clock phases, the FPGA determines the current clock phase to determine whether the current clock phase completes detection of the 32 clock phases, for example, the current clock phase is a 32 th clock phase, and after the FPGA samples video data and a synchronization signal of the input video source based on the 32 th clock phase, the FPGA determines that the current 32 th clock phase completes detection of the 32 clock phases, and then the FPGA determines a target clock phase according to the 32 detection results, otherwise, the FPGA continues to adjust and detect the clock phase of the input video source.
And the FPGA acquires the test reference data of the test reference source. The test reference source at this time may be, for example, image data of a test image sent through an external such as a host computer, and stored on a video input card such as a nonvolatile memory thereon. The test image may be, for example, a still image, which is used to detect video data in the sampled data sets. The test reference data is video data acquired by a test reference source through a first clock phase in 32 clock phases, and then whether a plurality of video data acquired by an input video source through 32 clock phases are respectively the same as the test reference data is compared to obtain a video data detection result, wherein the video data detection result comprises: the current video data is the same as the test reference data or the current video data is the same as the test reference data, the current video data is obtained by sampling an input video source through a current clock phase of 32 clock phases, for example, the current video data is 01010101, the test reference data is 01010111, the current video data detection result obtained by comparing the current video data with the test reference data is different, if the current video data is 01010101, the test reference data is 01010101, and the current video data detection result obtained by comparing the current video data with the test reference data is the same.
Then, judging frame rates and/or resolutions of three synchronous signals obtained by sampling, and the like, and then obtaining synchronous signal detection results, wherein the frame rates are judged, for example, within continuous 250 milliseconds, time intervals between a preset number of adjacent frame pictures in an input video source are compared, for example, the time interval between a first frame picture and a second frame picture is compared with the time interval between a second frame picture and a third frame picture, whether the time intervals of the first frame picture and the second frame picture are the same or not is judged, and if the time intervals of the first frame picture and the second frame picture are the same, the synchronous signal detection results are the same, namely, the synchronous signals are stable; if the two time intervals are not the same, judging that the detection results of the synchronous signals are not the same, namely the synchronous signals are unstable, wherein the error of the time intervals of the two time intervals is within 0.01 percent, considering that the time intervals of the two time intervals are the same, and otherwise, judging that the time intervals are not the same; the time of 250 milliseconds can be set by a user or set time issued by an upper computer or a main control card; the resolution includes a horizontal resolution and a vertical resolution, whether the resolutions of the continuous pictures of the multiple frames are the same or not can be judged, the horizontal resolution and/or the vertical resolution of the continuous pictures of the multiple frames can be judged, a judgment condition can be set according to an actual situation, and the specific situation is not limited here. The judgment condition of the resolution is whether the data and the quantity of the pixel points in the rows and/or the columns of the frame image data are the same under continuous multi-frame images, if so, the synchronous signal detection results are judged to be the same, namely, the synchronous signals are stable; if not, the synchronous signal detection result is judged to be not the same, namely the synchronous signal is unstable. When the judgment results of the synchronous signals are the same, namely the time intervals are the same and the pixel points of the rows of the frame picture data and/or the columns of the frame picture data are the same; when the judgment results of the synchronous signals are different, namely the time intervals are different or the rows of the frame picture data and/or the pixels of the columns of the frame picture data are different, the synchronous signals can be obtained; then, determining the detection result according to the video data detection result and the synchronous signal detection result, wherein when the detection result is correct, the video data detection result is the same, and the synchronous signal detection result is also the same; when the detection result is incorrect, that is, any one of the video data detection result or the synchronization signal detection result is not the same.
After the FPGA obtains the detection result, determining whether the detection result is correct, for example, when the video data detection results are the same and the synchronization signal detection results are also the same, determining that the detection result is correct; and when any one of the video data detection result or the synchronous signal detection result is different, judging that the detection result is incorrect.
When the detection result is judged to be correct, counting the correct detection result to obtain a count value, and when the count value reaches a correct detection result quantity threshold value, taking a clock phase corresponding to a target detection result in the continuous correct detection result as the target clock phase, wherein the target detection result is a detection result at a middle position in the continuous correct detection result; the correct detection result quantity threshold value can be set manually or by commands sent by an upper computer or other main control cards, for example, to determine that 15% of the number of multiple clock phases is used as the correct detection result number threshold, say 32 clock phases, the threshold value of the number of correct detection results is 5, when the detection results are judged to be correct and 5 consecutive detection results are all correct, taking the clock phase corresponding to the middle result in the continuous 5 detection results as the target clock phase, when the continuous correct detection results are 5, if the target detection result is the third middle detection result, the target clock phase is the clock phase corresponding to the third detection result, and the count value of the continuous correct detection result is an odd number, the target detection result takes the middle value of the count values; if the count of the consecutive correct detection results is 6 count values, the target detection result is selected from one of the middle third and fourth detection results as the target detection result, that is, when the count value of the consecutive correct detection results is an even number, the target detection result may be any one of the middle two values in the count values.
After the FPGA obtains the target clock phase, the FPGA adjusts the clock period to the target clock phase, and since the plurality of clock phases which are equally divided need to be detected, the current clock phase is the last clock phase in the plurality of clock phases during adjustment, namely the current clock phase is adjusted to the target clock phase from the last clock phase in one step. For example, a clock cycle is equally divided into 32 clock phases, then 32 detection results are obtained through the 32 clock phases, and it is determined from the 32 detection results that a target clock phase is an 18 th clock phase, then the last clock phase, namely the 32 th clock phase, in the 32 clock phases of the clock cycle is directly adjusted to the 18 th clock phase, which is equivalent to moving the clock cycle from the position of the 32 th clock phase to the position of the 18 th clock phase, thereby completing the process of dynamically adjusting the clock phases. In summary, the present invention first obtains the clock period of the input video source, determines a plurality of continuous clock phases according to the clock period, then sequentially and respectively samples and detects the plurality of continuous clock phases, and finally obtains the target clock phase through the detection result, wherein the target clock phase is the optimal clock phase output by the FPGA, thereby implementing a dynamic adjustment process of the clock phase, improving the compatibility of the video input card, and simultaneously achieving the effect of reducing the labor cost through the automatic adjustment process.
[ second embodiment ]
As shown in fig. 6, a second embodiment of the present invention provides an input video source adjusting apparatus 600, for example, comprising: a clock cycle obtaining module 601, a sampling data obtaining module 602, a reference data obtaining module 603, a detection result obtaining module 604, a clock phase determining module 605, and a clock phase adjusting module 606.
The clock period acquiring module 601 is configured to acquire a clock period of an input video source and determine a plurality of continuous clock phases according to the clock period; a sampling data obtaining module 602, configured to sequentially adjust a clock phase of the input video source to be the multiple clock phases and sample the input video source based on a current clock phase in the multiple clock phases to obtain multiple sampling data sets; a reference data obtaining module 603, configured to obtain test reference source test reference data; a detection result obtaining module 604, configured to respectively detect the multiple sampling data sets according to the test reference data to obtain multiple detection results that correspond to each other; a clock phase determining module 605, configured to determine a target clock phase according to the multiple detection results; and a clock phase adjusting module 606, configured to adjust the clock phase of the input video source to the target clock phase.
Further, this embodiment provides a sampled data obtaining module 602, where the multiple clock phases include a first clock phase, the multiple sampled data sets include a first sampled data set, the first sampled data set includes first video data and a first synchronization signal, and the sampled data obtaining module 602 is specifically configured to: adjusting the current clock phase of the input video source to the first clock phase; and sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
Further, this embodiment provides a detection result obtaining module 604, where the multiple detection results include a first detection result, and the detection result obtaining module 604 is specifically configured to: comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result; judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signal in the first sampling data group are the same and/or the frame rates are the same to obtain a first synchronous signal detection result; and determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
Further, the present embodiment provides a clock phase determining module 605, specifically configured to: judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value; and when the counting value reaches a correct detection result quantity threshold value, taking a clock phase corresponding to a target detection result in the continuous correct detection results as the target clock phase. And the target detection result is a detection result at an intermediate position in the continuous correct detection results.
Further, the clock period is generated by the resolution of the input video source and the output mode of the interface chip.
The input video source adjusting method implemented by the input video source adjusting apparatus 600 disclosed in this embodiment is as described in the first embodiment, and therefore, will not be described in detail herein. Optionally, each module and the other operations or functions in the second embodiment are respectively for implementing the method in the first embodiment of the present invention, and the beneficial effects of this embodiment may refer to the description of the beneficial effects of the first embodiment, and are not described herein again.
[ third embodiment ]
As shown in fig. 7A, a third embodiment of the present invention provides a video input card 700, including: a first video input interface 701, a communication interface 703 and a programmable logic device 704.
The first video input interface 701 is used for accessing an input video source and accessing a test reference source; for the access of the input video source and the test reference source from the first video input interface 701, for example, before performing clock phase adjustment and data sampling of the input video source, the test reference source is accessed first, and test reference data is acquired at an initial clock phase and stored on a video input card, for example, on a nonvolatile memory of the video input card, which is connected with the programmable logic device 704, or directly stored in the programmable logic device 704, for example, on an internal RAM thereof, and then the input video source is accessed through the first video input interface 701, and data sampling is started for the input video source, and dynamic adjustment of the clock phase is performed according to the test reference data of the test reference source obtained by sampling and the sampling data of the input video source; of course, it may also be that the input video source is accessed through the first video input interface 701, the clock phase division of the input video source is started and adjusted to the current clock phase of the multiple clock phases, the data sampling is performed on the input video source based on the current clock phase and the sampling data is recorded, then the test reference source is accessed through the first video input interface 701, the test reference data is obtained at the initial clock phase and stored on the video input card, for example, the nonvolatile memory connected to the programmable logic device 704, or directly stored in the programmable logic device 704, for example, the internal RAM thereof, and finally the dynamic adjustment of the clock phase is performed according to the test reference data of the test reference source obtained by sampling and the sampling data of the input video source; even the input video source may be accessed through the first video input interface 701, and the input video source starts to be clock-phase-divided and adjusted to a current clock phase of the multiple clock phases, and data sampling and recording the sampling data are performed on the input video source based on the current clock phase, and the test reference source is accessed through another interface, such as a video input interface or a communication interface, and the test reference data is acquired at the initial clock phase and stored on a video input card, such as a nonvolatile memory connected to the programmable logic device 704 or directly stored in the programmable logic device 704, such as an internal RAM thereof, and the clock phase is dynamically adjusted according to the test reference data of the test reference source obtained by sampling and the sampling data of the input video source, which is not limited by the present invention.
The communication interface 703 is configured to receive an input video source adjustment instruction; the programmable logic device 704 is connected to the first video input interface 701 and the communication interface 703.
Wherein the programmable logic device is configured to perform the input video source adjustment method as described above in the first embodiment.
The video input card 700 may further include a second video input interface and a third video input interface, etc., and a plurality of video input interfaces may be arranged on the video input card 700 according to actual needs, which is not limited herein.
Further, as shown in fig. 7B, the programmable logic device 704 includes: a hybrid clock management module 7041, a data sampling module 7042, a data detection module 7043, and a hybrid clock management configuration module 7044.
The hybrid clock management configuration module 7044 is configured to obtain the input video source adjustment instruction through the communication interface 703, obtain the clock cycle of the input video source, and determine the multiple continuous clock phases according to the clock cycle; the hybrid clock management module 7041 is configured to sequentially adjust the clock phases of the input video source to the plurality of clock phases; the data sampling module 7042 is configured to sample the input video source based on the current clock phase of the multiple clock phases to obtain multiple sampling data sets, and obtain the test reference data of the test reference source through the first video input interface; the data detection module 7043 is configured to detect the multiple sampling data sets according to the test reference data, respectively, to obtain the multiple detection results in a one-to-one correspondence; the hybrid clock management configuration module 7044 is further configured to determine the target clock phase according to the plurality of detection results; the hybrid clock management module 7041 is further configured to adjust the clock phase of the input video source to the target clock phase.
Further, as shown in fig. 7B, the data detecting module 7043 includes a video data detecting unit 70431 and a synchronization signal detecting unit 70432; the video data detecting unit 70431 is configured to compare, according to the test reference data, whether video data in the multiple sampling data groups are the same one by one to obtain multiple video data detection results; the synchronizing signal detecting unit 70432 is configured to determine one by one whether resolutions of multiple frames of consecutive pictures of the synchronizing signal in the plurality of sample data sets are the same and/or frame rates are the same, so as to obtain a plurality of synchronizing signal detection results.
[ fourth example ] A
As shown in fig. 8, a video processing apparatus 800 according to a fourth embodiment of the present invention includes: a video input card 801; a main control card 802 connected to the communication interface 8011 of the video input card 801;
the video input card 801 is, for example, the video input card in the third embodiment.
[ fifth embodiment ]
As shown in fig. 9, a fifth embodiment of the present invention provides an input video source adjusting system 900, which includes: a processor 901 and a memory 903; the memory 903 stores instructions executed by the processor 901, and the processor 901 executes the instructions to perform the input video source adjusting method described in the foregoing first embodiment.
[ sixth embodiment ]
As shown in fig. 10, a sixth embodiment of the present invention provides a computer-readable storage medium 1000, which is a non-volatile memory and stores computer-readable instructions, when the computer-readable instructions are executed by one or more processors, for performing the input video source adjusting method according to the first embodiment.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and technical solutions of the embodiments can be arbitrarily combined and used without conflict between technical features and structures, and without departing from the purpose of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and/or method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units/modules is only one logical division, and there may be other divisions in actual implementation, for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units/modules described as separate parts may or may not be physically separate, and parts displayed as units/modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
The integrated units/modules, which are implemented in the form of software functional units/modules, may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An input video source adjustment method, comprising:
acquiring a clock cycle of an input video source and determining a plurality of continuous clock phases according to the clock cycle;
sequentially adjusting the clock phase of the input video source to be the plurality of clock phases and sampling the input video source based on the current clock phase in the plurality of clock phases to obtain a plurality of sampling data groups;
acquiring test reference data of a test reference source;
respectively detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of detection results which correspond to one another one by one;
determining a target clock phase according to the plurality of detection results; and
and adjusting the clock phase of the input video source to the target clock phase.
2. The input video source adjustment method of claim 1, wherein the plurality of clock phases comprises a first clock phase, the plurality of sample data sets comprises a first sample data set, the first sample data set comprises first video data and a first synchronization signal; sequentially adjusting the clock phase of the input video source to the plurality of clock phases and sampling the input video source based on a current clock phase of the plurality of clock phases to obtain a plurality of sampled data sets comprises:
adjusting the current clock phase of the input video source to the first clock phase;
and sampling the input video source according to the first clock phase to obtain the first video data and the first synchronous signal.
3. The input video source adjustment method of claim 2, wherein the plurality of detection results comprises a first detection result; the detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of one-to-one corresponding detection results respectively includes:
comparing whether the test reference data is the same as the first video data or not to obtain a first video data detection result;
judging whether the resolutions of the multi-frame continuous pictures of the first synchronous signal in the first sampling data group are the same and/or the frame rates are the same to obtain a first synchronous signal detection result; and
and determining the first detection result according to the first video data detection result and the first synchronous signal detection result.
4. The input video source adjustment method of claim 1, wherein said determining a target clock phase from said plurality of detection results comprises:
judging whether the detection results are correct or not and counting the continuous correct detection results to obtain a count value;
and when the count value reaches the number threshold of the correct detection results, taking the clock phase corresponding to the target detection result in the continuous correct detection results as the target clock phase.
5. The input video source adjustment method of claim 1, wherein the clock period is determined by a resolution of the input video source and a clock period generated by an output pattern of an interface chip.
6. An input video source adjusting apparatus, for implementing the input video source adjusting method according to any one of claims 1 to 5 and comprising:
the clock period acquisition module is used for acquiring the clock period of an input video source and determining a plurality of continuous clock phases according to the clock period;
a sampling data obtaining module, configured to sequentially adjust a clock phase of the input video source to be the multiple clock phases and sample the input video source based on a current clock phase of the multiple clock phases to obtain multiple sampling data sets;
the reference data acquisition module is used for acquiring test reference data of the test reference source;
a detection result obtaining module, configured to respectively detect the multiple sampling data sets according to the test reference data to obtain multiple detection results that correspond to each other;
a clock phase determining module, configured to determine a target clock phase according to the multiple detection results; and
and the clock phase adjusting module is used for adjusting the clock phase of the input video source to the target clock phase.
7. A video input card, comprising:
the first video input interface is used for accessing an input video source and a test reference source;
the communication interface is used for receiving an input video source adjusting instruction;
the programmable logic device is connected with the first video input interface and the communication interface;
wherein the programmable logic device is configured to perform the input video source adjustment method of any of claims 1 to 6 above.
8. The video input card of claim 7, wherein the programmable logic device comprises: the device comprises a hybrid clock management module, a data sampling module, a data detection module and a hybrid clock management configuration module;
the hybrid clock management configuration module is configured to obtain the input video source adjustment instruction through the communication interface, obtain the clock cycle of the input video source, and determine the multiple continuous clock phases according to the clock cycle;
the hybrid clock management module is used for sequentially adjusting the clock phases of the input video source into the plurality of clock phases;
the data sampling module is configured to sample the input video source based on the current clock phase of the multiple clock phases to obtain multiple sampling data sets, and obtain the test reference data of the test reference source through the first video input interface;
the data detection module is used for respectively detecting the plurality of sampling data groups according to the test reference data to obtain a plurality of detection results in one-to-one correspondence;
the hybrid clock management configuration module is further configured to determine the target clock phase according to the plurality of detection results;
the hybrid clock management module is further configured to adjust a clock phase of the input video source to the target clock phase.
9. The video input card of claim 8, wherein the data detection module comprises a video data detection unit and a synchronization signal detection unit;
the video data detection unit is used for comparing whether the video data in the plurality of sampling data groups are the same one by one according to the test reference data to obtain a plurality of video data detection results;
the synchronous signal detection unit is used for judging whether the resolutions of the multi-frame continuous pictures of the synchronous signals in the plurality of sampling data groups are the same and/or the frame rates are the same one by one to obtain a plurality of synchronous signal detection results.
10. A video processing apparatus, comprising:
the video input card of any one of claims 7-9;
and the master control card is connected with the communication interface of the video input card.
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