CN114499757A

CN114499757A - Method and device for generating checksum and electronic equipment

Info

Publication number: CN114499757A
Application number: CN202210015683.2A
Authority: CN
Inventors: 陈坚
Original assignee: Ruijie Networks Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2022-01-07
Filing date: 2022-01-07
Publication date: 2022-05-13

Abstract

A method and a device for generating a checksum and an electronic device are provided. In the application, the message to be processed is split into a plurality of subdata, each subdata is subjected to accumulation calculation by a single checksum accumulation unit to obtain an accumulation result, and all the obtained accumulation results are accumulated and combined to obtain the checksum corresponding to the message to be processed. The method realizes that the hardware equipment splits and accumulates the messages to be processed to obtain the checksum, not only can save CPU resources, but also can meet the requirement of large bandwidth.

Description

Method and device for generating checksum and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for generating a checksum, and an electronic device.

Background

Currently, the communication between devices is performed based on data transmission, and in order to ensure the integrity and accuracy of data during data transmission, a checksum is required, which is used in the data communication field to check the sum of a group of data items at a destination, and is usually expressed in hexadecimal system.

Specifically, a checksum in a network packet based on Transmission Control Protocol (TCP) is an end-to-end checksum, which is calculated by a transmitting end and then verified by a receiving end. The purpose is to discover any changes that occur to the TCP header data between the sender and receiver.

At present, the calculation of checksum is mainly performed directly by a CPU, that is, when a packet is assembled, a checksum field in the packet is set to 0, data to be checked is used as a digital composition with 16 bits as a unit, binary cyclic summation accumulation is performed in sequence, and carry accumulation is also performed. And inverting the obtained 16-bit result and putting the result into a checksum field.

For example, if the checksum of the next piece of data is calculated, the data is in a 16-system number;

45 00 00 3c 00 00 00 00 40 11 6d 36 c0 a8 2b c3 08 08 08 08 11

the field 6d36 is a checksum field, the checksum is set to be 0, data is grouped and supplemented by 0, the sorted data is as follows, the middle checksum is set to be 0, and finally 1byte 0 is supplemented;

4500 003c 0000 0000 4011 0000 c0a8 2bc3 0808 0808 1100

and (3) calculating: 4500+003C +0000+0000+4011+0000+ C0a8+2bc3+0808+0808+1100 ═ 192C 8;

high and low 16bit addition: 1+92C8 ═ 92C 9;

taking the inverse: -92C 9 ═ 6D 36;

the final data obtained were: 4500003 c 0000000040116 d36 c0a 82 b c 30808080811;

through the scheme, the CPU can directly complete the checksum calculation, the CPU can be used for directly performing the checksum calculation of the message under the condition of low bandwidth, but under the condition of high bandwidth requirement, the CPU directly used for performing the checksum calculation of the message occupies a large amount of CPU resources, the CPU load is increased, and the checksum calculation speed is reduced.

Disclosure of Invention

The application provides a method and a device for generating a checksum and electronic equipment, which are used for splitting and accumulating messages to be processed on a hardware circuit to obtain the checksum.

In a first aspect, the present application provides a method for calculating a checksum, including:

when a first message to be processed is obtained, carrying out data splitting on the first message to be processed according to a preset byte number to obtain a plurality of first subdata;

distributing the plurality of first subdata to each check sum accumulation unit, and obtaining an accumulation result obtained by accumulating and calculating the first subdata by each check sum accumulation unit;

and accumulating and combining all the obtained accumulation results to obtain a checksum corresponding to the first message to be processed.

In the application, by the method, the message to be processed can be split into a plurality of subdata in a hardware circuit, and each subdata is subjected to accumulation calculation by a separate checksum accumulation unit to obtain an accumulation result. The messages to be processed are split and accumulated through the hardware equipment, so that not only can CPU resources be saved, but also the requirement of large bandwidth can be met.

In one possible embodiment, distributing the plurality of first sub-data to the respective checksum accumulation units includes:

judging whether second subdata with the byte number smaller than the preset byte number exists in each first subdata;

if the message exists, determining an invalid byte bit and an effective byte in the second subdata according to the total byte number of the message to be processed and the byte number of each first subdata;

adding a designated numerical value to the invalid byte bit in the second subdata to obtain third subdata;

and sending the effective bytes in the first subdata and the third subdata to a checksum accumulation unit.

In one possible implementation, the determining whether there is second sub-data in each first sub-data, where the number of bytes is less than a preset number of bytes, includes:

and acquiring the effective byte number in each first subdata, and judging whether the effective byte number in each first subdata is smaller than a preset byte number.

In a possible implementation manner, the obtaining an accumulation result obtained by performing accumulation calculation on the first sub-data by each checksum accumulation unit includes:

detecting whether an end mark indicating the end of the data of the first message to be processed exists or not;

if yes, outputting the accumulation result and clearing the cached accumulation result;

and if the first subdata does not exist, accumulating and calculating the first subdata of the first message to be processed continuously.

detecting whether a message identifier of a second message to be processed exists at present;

if yes, outputting the accumulation result, and clearing the cached accumulation result;

if not, accumulation calculation is continuously carried out on the first subdata.

In a second aspect, the present application provides an apparatus for calculating a checksum, the apparatus comprising: a data splitting unit, a checksum accumulation unit and a merging unit, the checksum accumulation unit comprising a plurality of checksum accumulation modules, wherein,

the data splitting unit is used for splitting the first message to be processed according to a preset byte number when the first message to be processed is obtained, obtaining a plurality of first subdata, and distributing the plurality of first subdata to each check sum accumulation module;

the checksum accumulation unit is used for obtaining an accumulation result obtained by accumulating and calculating the first subdata by each checksum accumulation module;

and the merging unit is used for accumulating and merging all the obtained accumulation results to obtain the checksum corresponding to the first message to be processed.

In a possible implementation manner, the data splitting unit is specifically configured to determine whether there is second sub-data in which the number of bytes is less than a preset number of bytes in each first sub-data; if the message exists, determining an invalid byte bit and an effective byte in the second subdata according to the total byte number of the message to be processed and the byte number of each first subdata; adding a designated numerical value to the invalid byte bit in the second subdata to obtain third subdata; and sending the effective bytes in the first subdata and the third subdata to a checksum accumulation unit.

In a possible implementation manner, the data splitting unit is specifically configured to obtain an effective number of bytes in each first sub-data, and determine whether the effective number of bytes in each first sub-data is smaller than a preset number of bytes.

In a possible implementation manner, the checksum accumulation unit is further configured to detect whether an end identifier indicating an end of data of the first to-be-processed packet exists; if yes, outputting the accumulation result and clearing the cached accumulation result; and if the first subdata does not exist, accumulating and calculating the first subdata of the first message to be processed continuously.

In a third aspect, the present application provides an electronic device, comprising:

a memory for storing a computer program;

and the processor is used for realizing the checking and generating method steps when executing the computer program stored in the memory.

In a fourth aspect, the present application provides a computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the method steps of checksum generation as described above.

For each of the second to fourth aspects and possible technical effects of each aspect, please refer to the above description of the first aspect or the possible technical effects of each of the possible solutions in the first aspect, and no repeated description is given here.

Drawings

FIG. 1 is a schematic flow chart diagram illustrating a method for generating a checksum provided herein;

FIG. 2 is a schematic diagram of a hardware circuit configuration provided in the present application;

fig. 3 is a schematic diagram of a to-be-processed message splitting result provided in the present application;

FIG. 4 is a schematic diagram of the subdata accumulation calculation provided by the present application;

fig. 5 is a schematic structural diagram of an accumulation result merging unit in a hardware circuit provided in the present application;

FIG. 6 is a schematic diagram illustrating a timing process for calculating a checksum provided herein;

fig. 7 is a second schematic diagram of a hardware circuit structure provided in the present application;

fig. 8 is a third schematic diagram of a hardware circuit structure provided in the present application;

fig. 9 is a schematic structural diagram of an electronic device provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings. The particular methods of operation in the method embodiments may also be applied to apparatus embodiments or system embodiments. It should be noted that "a plurality" is understood as "at least two" in the description of the present application. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. A is connected with B and can represent: a and B are directly connected and A and B are connected through C. In addition, in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not intended to indicate or imply relative importance nor order to be construed.

45 00 00 3c 00 00 00 00 40 11 6d 36 c0 a8 2b c3 08 08 08 08 11

4500 003c 0000 0000 4011 0000 c0a8 2bc3 0808 0808 1100

high and low 16bit addition: 1+92C8 ═ 92C 9;

taking the inverse: -92C 9 ═ 6D 36;

In order to solve the above problem, the present Application provides a method for generating a checksum, which may be applied to a Field Programmable Gate Array (FPGA) Circuit or an Application Specific Integrated Circuit (ASIC), and may also be applied to other hardware devices or hardware circuits, which is not illustrated here.

The hardware equipment is provided with a plurality of check sum accumulation modules, so that the message to be processed can be divided into a plurality of subdata, and each check sum accumulation module can respectively carry out accumulation calculation on the subdata of the message to be processed to obtain an accumulation result. The messages to be processed are split and accumulated through the hardware equipment, so that not only can CPU resources be saved, but also the requirement of large bandwidth can be met.

The technical solution of the present application is described in detail below with the attached figures and examples.

Fig. 1 is a flowchart of a method for generating a checksum in an embodiment of the present application, where the method includes:

s1, when the first message to be processed is obtained, data splitting is carried out on the first message to be processed according to the preset byte number, and a plurality of first subdata are obtained;

first, the method is applied to a hardware circuit, such as an FPGA circuit or an ASIC circuit, as shown in fig. 2, the hardware circuit includes a data splitting unit, a checksum accumulation unit and an accumulation result merging unit, and the checksum accumulation unit includes a plurality of checksum accumulation modules.

The data splitting unit is used for splitting data of the first message to be processed according to a preset byte number when the first message to be processed is obtained. For example, the first message to be processed is 512 bytes of data, and when the message to be processed is split according to the preset byte number of 64 bytes, the 512 bytes of the first message to be processed is split into 8 sub-data of 64 bytes, that is, each sub-data of 64 bytes is the first sub-data.

Certainly, the byte number of each message to be processed may not be split into sub-data with a preset byte number, for example, the total length of the message is 265 bytes, the first 4 clocks are 64 bytes, each 64 bytes may be split into 8 sub-data with 64 bits for calculation, all the data is valid, and mod of the sub-data is 8. At the 5 th clock, 9 bytes (265-; the 2 nd highest significant byte number mod is 1, and the remaining 7 bits are the number of invalid byte bits, so the data is complemented by 0 of 7 bytes; the remaining child data mod is all 0.

Therefore, in the embodiment of the present application, in addition to splitting the first to-be-processed packet into a plurality of first sub-data, validity verification needs to be performed on the split first sub-data, that is, it is determined whether second sub-data with a byte number smaller than a preset byte number exists in each first sub-data, and if the second sub-data does not exist, the first sub-data is directly distributed to each check and accumulation unit; if the message exists, determining invalid byte bits and valid bytes in the second subdata according to the total byte number of the message to be processed and the byte number of each first subdata; and adding an appointed value to the invalid byte bit, obtaining third subdata according to the effective byte number and the appointed value, and sending the effective byte of the first subdata and the third subdata to a check and accumulation unit.

For example, as shown in fig. 3, when 265 bytes of data are divided into 64 bytes, the first 4 sub-data are 64 bytes, but the fifth sub-data has 9 bytes. The previous 4 clocks are 8 according to the original valid byte number mod, and the decoded mod [7] to mod [0] are all 8, that is, the corresponding 8 64 bits of each unit are valid. And the last clock is original mod 9, valid data are stored from high bits to low bits in the design according to a big-end mode, so that the valid byte number mod _ decode [7] is 8, which represents that the 7 th unit data are all valid, mod _ decode [6] is 1, which represents that the 6 th unit data only has the highest 8 bits of data, and other mod _ decodes are all 0, which indicates that the input data are invalid.

Through the mode, the invalid byte in the first subdata can be added with 0, so that the first subdata can be accurately accumulated and calculated in the follow-up process.

After the splitting of the first to-be-processed message and the validity determination of the first sub-data are completed, the accumulation calculation is completed through step S2.

S2, distributing the plurality of first subdata to each checksum accumulation unit, and obtaining the accumulation result obtained by each checksum accumulation unit performing accumulation calculation on the first subdata;

after the first sub-data and the third sub-data obtained by adding the designated numerical value are obtained, the first sub-data and the third sub-data are distributed to each checksum accumulation unit, as shown in fig. 4, if the first sub-data obtained by the first to-be-processed message which is split in fig. 4 is 64 bytes, the first sub-data is directly transmitted to a latch of the checksum accumulation unit for accumulation calculation, so that an accumulation result of the first sub-data is obtained. But the data involved in the calculation is not always 64bit aligned, so in the last data period, mod _ decode indicates the number of valid bytes for the last clock of the checksum accumulation unit, and the other invalid byte bits are padded with 0.

For example, in fig. 4, if mod _ decode is 8, and all of the 8 bytes are valid, the highest byte data [63:56] is valid, and all of the lowest byte data [55:0] is valid, so that the accumulation calculation can be performed directly.

If mod _ decode is 1, then the most significant byte is valid, i.e.: data [63:56] is valid and the subsequent low byte data [55:0] is padded with 0's to participate in the accumulation calculation.

If mod _ decode is 2, when all 2 bytes are valid, then data [63:48] is valid and data [47:0] is padded with 0 to participate in the accumulation calculation.

Other values of mod _ decode can be used to replace invalid bytes according to the above method, which is not illustrated here.

After the validity verification of the first sub-data is completed, the first sub-data or the third sub-data is subjected to an accumulation calculation, and the specific accumulation calculation mode is to add according to 2 bytes, which has been described in detail in the foregoing, and is not described here again.

Further, in the embodiment of the present application, a latch is disposed in the checksum accumulation unit, and the latch may specifically store an accumulation result accumulated for each time of accumulating the first sub-data, for example, after one first sub-data is accumulated, the accumulation result is stored, and then when a second first sub-data is accumulated, the accumulation result stored in the latch is accumulated, that is, each accumulation result is used as an input of a next accumulation calculation.

In the presence of the latch, in order to ensure the accuracy of each accumulation calculation, before the accumulation calculation of the first sub-data is required each time, it is required to detect whether an end flag indicating the end of the data of the first to-be-processed packet exists. If the ending mark exists, the data of the first message to be processed is ended, at the moment, an accumulation result is output, and the cached accumulation result is cleared; if the ending mark does not exist, the first subdata of the first message to be processed is continuously accumulated and calculated. By the method, the output time of each accumulated result can be accurately determined, and the accuracy of the output of the accumulated result is ensured.

In addition, in the embodiment of the present application, since the accumulated result obtained by each accumulation calculation is stored in the latch, when there are new other messages to be processed that need to be processed, the accumulated result in the latch needs to be cleared by 0.

Specifically, after obtaining the accumulation result, it is required to detect whether a packet identifier of the second to-be-processed packet exists currently, where the packet identifier may be an identifier carried in the first sub-data, and of course, the packet identifier may also be obtained in another manner. If the message identification of the second message to be processed is detected, obtaining and outputting an accumulation result, and clearing the accumulated result cached; and if the message identifier of the second message to be processed is not detected, continuously performing accumulation calculation on the first subdata. By the method, the accumulated result can be cleared in time after the accumulated calculation of the messages to be processed is finished every time, and interference caused by the accumulated calculation of other messages to be processed is avoided.

It should be noted that, in the embodiment of the present application, the output bit width of the checksum accumulation unit is 32 bits, so that no overflow occurs until the maximum data addition of 16 bits of 64K bytes, that is, no overflow occurs in the checksum accumulation unit when the packet length is less than 128K bytes, and in general, the TCP packet length is longest at 64K bytes, so that after splitting, ethernet transmission is generally at 1500 bytes, and therefore, no overflow occurs in the checksum accumulation unit.

And S3, accumulating and combining all the accumulated results to obtain the checksum corresponding to the first message to be processed.

In the embodiment of the present application, since there are a plurality of checksum accumulation units, the accumulation result obtained by each checksum accumulation unit cannot be used as the final checksum, and therefore, the accumulation results obtained by all checksum accumulation units need to be accumulated.

As shown in fig. 5, the accumulated result merging unit in fig. 5 includes a first-stage adder, a second-stage adder, and a third-stage adder.

In the embodiment of the present application, the checksum accumulation unit includes a plurality of checksum accumulation units, so that after each checksum accumulation unit performs accumulation calculation to obtain an accumulation result, the accumulation result is transmitted to the first-stage adder. For a 265-byte message, 8 32-bit addition of the accumulated results needs to be completed in the first-stage adder, and in order to ensure the timing requirement, the first-stage adder can be split into 2 parallel adders to complete the addition of the accumulated results. Equivalent to 4 data additions of 32 bits per adder.

The second-stage adder splits the accumulated result of all data into high-order 16 bits and low-order 16 bits, wherein the high-order 16 bits are data [31:16] and the low-order 16 bits are data [15:0], and carry is generated by accumulation calculation in the second-stage adder.

The third-stage adder adds the low-order 16 bits of the second-stage adder, and as the maximum result of the addition of the two 16 bits of the second-stage adder does not exceed 0x1FFFE, namely under the condition that the two 16 bits are the maximum input values: 0xFFFF +0xFFFF ═ 0x1FFFE, the lower 16 bits are 0 xffffe, and the carry C is 1. Therefore, the sum of the low 16bit and the carry C in the third stage adder will not exceed 0xFFFF, that is, the final checksum can be obtained, and no overflow occurs.

In addition, in the embodiment of the present application, as shown in fig. 6, a timing process diagram for calculating a checksum is shown, in fig. 6, the calculation of the checksum is completed within 9 clocks, that is, clk1 to clk9, and corresponding processes are performed at each clock, for example, the splitting of the message to be processed is completed at clk1 to clk5, the first accumulation is completed at clk6, the first merging calculation of the accumulated result is completed at clk7, the second merging calculation is completed at clk8, and finally the checksum is obtained at clk 9.

By the pipeline calculation mode shown in fig. 6, the time sequence problem in the checksum calculation process can be effectively solved, the hardware circuit dominant frequency can have higher calculation efficiency, and the checksum calculation speed is improved.

Further, in the time sequence process shown in fig. 6, since the checksum accumulation calculation of the message to be processed is already completed at clk6, the checksum calculation of the next message to be processed may be performed at the location of clk6, and it is not necessary to wait until the location of clk9 to perform the checksum calculation of the next message to be processed, so that the efficiency of the checksum accumulation calculation may be improved.

Based on the method, the message to be processed is split into a plurality of subdata, and each subdata is subjected to accumulation calculation by a separate checksum accumulation unit to obtain an accumulation result. The messages to be processed are split and accumulated through the hardware equipment, so that not only can CPU resources be saved, but also the requirement of large bandwidth can be met.

The method provided by the embodiment of the application also provides a device for calculating the checksum, and the device can be used for carrying out splitting calculation on the message to be processed, and then combining the accumulated results of the splitting calculation to obtain the final checksum. As shown in fig. 7, the apparatus includes: the system comprises a data splitting unit 701, a checksum accumulation unit 702 and a merging unit 703, wherein the checksum accumulation unit 702 comprises a plurality of checksum accumulation modules, and the merging unit 703 comprises a plurality of adders.

The data splitting unit 701 is configured to split data of a first message to be processed according to a preset number of bytes when the first message to be processed is obtained, obtain a plurality of first subdata, and distribute the plurality of first subdata to each checksum accumulation module;

a checksum accumulation unit 702, configured to obtain an accumulation result obtained by performing accumulation calculation on the first sub data by each checksum accumulation module;

the merging unit 703 is configured to perform accumulation and merging on all obtained accumulation results to obtain a checksum corresponding to the first to-be-processed message.

Specifically, the data splitting unit 701 performs data splitting on the first message to be processed according to the preset number of bytes. For example, the first message to be processed is 512 bytes of data, and when the message to be processed is split according to the preset byte number of 64 bytes, the 512 bytes of the first message to be processed is split into 8 sub-data of 64 bytes, that is, each sub-data of 64 bits is the first sub-data.

Further, in this embodiment of the present application, the data splitting unit 701 includes a data splitting module and a decoding module, where the data splitting module performs data splitting on the first to-be-processed packet, and the decoding module is configured to verify validity of the split first sub-data, that is, determine whether a second sub-data with a byte number smaller than a preset byte number exists in each first sub-data, and if not, directly distribute the first sub-data to each checking and accumulating module; if the message exists, determining invalid byte bits and valid bytes in the second subdata according to the total byte number of the message to be processed and the byte number of each first subdata; and adding an appointed value to the invalid byte bit, obtaining third subdata according to the effective byte number and the appointed value, and sending the effective byte of the first subdata and the third subdata to a check and accumulation module.

For example, as shown in fig. 3, when a 265-byte data is split into 64 bytes, the first 4 sub-data are 64 bytes, but the fifth sub-data has 9 bytes. The first 4 clocks are all 8 from original mod [7] to mod [0], i.e. 8 bits per unit are valid. And the last clock, original mod is 9, since valid data is stored from high order to low order in the design according to the big-end mode, mod _ decode [7] is 8, which represents that the 7 th unit data is all valid, mod _ decode [6] is 1, which represents that the 6 th unit data only with the highest 8 bits is valid, and other mod _ decodes are all 0, which indicates that the input data is invalid.

Further, in this embodiment of the application, after the data splitting unit 701 splits the first sub-data and the third sub-data obtained by adding the specified numerical value, the data splitting unit 701 distributes the first sub-data and the third sub-data to each checksum accumulation module. As shown in fig. 4, if the first subdata obtained from the first to-be-processed packet split in fig. 4 is 64 bytes, the first subdata is directly transmitted to the latch of the checksum accumulation unit for accumulation calculation, so as to obtain the accumulation result of the first subdata. However, the data involved in the calculation is not always 64-bit aligned, so in the last data period, mod _ decode indicates the valid number of bytes for the last clock of the checksum accumulation unit, and the other invalid byte bits are padded with 0.

For example, in fig. 4, if mod _ decode is 8, the highest byte data [63:56] is valid, and all the lowest bytes data [55:0] are valid, so that the accumulation calculation can be directly performed.

If mod _ decode is 2, then data [63:48] is valid and data [47:0] is padded with 0 to participate in the accumulation calculation.

Further, in this embodiment of the application, the checksum accumulation unit 702 further includes a latch, and the latch may specifically store an accumulation result accumulated for each time of accumulating the first sub-data, for example, after one first sub-data is accumulated, the accumulation result is stored, and then when a second first sub-data is accumulated, the accumulation result stored in the latch is accumulated, that is, each accumulation result is used as an input of a next accumulation calculation.

Specifically, after the latch obtains the accumulation result, it is detected whether a packet identifier of the second to-be-processed packet exists currently, where the packet identifier may be an identifier carried in the first sub-data, and of course, the packet identifier may also be obtained in another manner. If the message identification of the second message to be processed is detected, obtaining and outputting an accumulation result, and clearing the accumulated result cached; and if the message identifier of the second message to be processed is not detected, continuously performing accumulation calculation on the first subdata. By the method, the accumulated result can be cleared in time after the accumulated calculation of the messages to be processed is finished every time, and interference caused by the accumulated calculation of other messages to be processed is avoided.

Further, as shown in fig. 8, in the embodiment of the present application, the merging unit 703 includes a first-stage adder 81, a second-stage adder 82, and a third-stage adder 83, and for a 265-byte message, 8 32-bit addition of the accumulated results needs to be completed in the first-stage adder 81, and in order to ensure the timing requirement, the adding unit may be split into 2 parallel adders to complete addition of the accumulated results. Equivalent to 4 data additions of 32 bits per adder.

The second stage adder 82 splits the accumulated result of all data into high 16 bits and low 16 bits, where the high 16 bits are data [31:16] and the low 16 bits are data [15:0], and carries are generated by performing accumulation calculation in the second stage adder 82.

The third-stage adder 83 adds the low-order 16 bits of the second-stage adder 82, and since the maximum addition result of the two 16 bits of the second-stage adder 82 does not exceed 0x1FFFE, that is, under the condition that the two 16 bits are the maximum input values: 0xFFFF +0xFFFF ═ 0x1FFFE, the lower 16 bits are 0 xffffe, and the carry C is 1. Therefore, the sum of the 16 bits and the carry C in the third-stage adder 83 will not exceed 0xFFFF, i.e. the final checksum can be obtained, and no overflow occurs.

In addition, in this embodiment, as shown in fig. 6, which is a schematic diagram of a timing process for calculating a checksum, the apparatus for calculating a checksum performs the checksum calculation according to the timing process shown in fig. 6, the checksum calculation is completed within 9 clocks, that is, clk1 to clk9, a corresponding process is performed at each clock, for example, the data splitting units 701 between clk1 and clk5 complete the splitting of the to-be-processed packet, the first-stage adder 81 completes the first accumulation at clk6, the second-stage adder 82 completes the first combination calculation of the accumulation result at clk7, the third-stage adder 83 completes the second combination calculation at clk8, and finally the checksum is obtained at clk 9.

Based on the same inventive concept, an embodiment of the present application further provides an electronic device, where the electronic device can implement the function of the output device in the foot falling area, and with reference to fig. 9, the electronic device includes:

at least one processor 901 and a memory 902 connected to the at least one processor 901, in this embodiment, a specific connection medium between the processor 901 and the memory 902 is not limited in this application, and fig. 9 illustrates an example in which the processor 901 and the memory 902 are connected through a bus 900. The bus 900 is shown in fig. 9 by a thick line, and the connection manner between other components is merely illustrative and not limited thereto. The bus 900 may be divided into an address bus, a data bus, a control bus, etc., and is shown with only one thick line in fig. 9 for ease of illustration, but does not represent only one bus or type of bus. Alternatively, the processor 901 may also be referred to as a controller, without limitation to name a few.

In the embodiment of the present application, the memory 902 stores instructions executable by the at least one processor 901, and the at least one processor 901 can execute the method for calculating the checksum discussed above by executing the instructions stored in the memory 902. The processor 901 may implement the functions of the respective modules in the apparatus shown in fig. 7.

The processor 901 is a control center of the apparatus, and may connect various parts of the entire apparatus by using various interfaces and lines, and perform various functions of the apparatus and process data by executing or executing instructions stored in the memory 902 and calling up data stored in the memory 902, thereby performing overall monitoring of the apparatus.

In one possible design, the processor 901 may include one or more processing units, and the processor 901 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, and the like, and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 901. In some embodiments, the processor 901 and the memory 902 may be implemented on the same chip, or in some embodiments, they may be implemented separately on separate chips.

The processor 901 may be a general-purpose processor, such as a Central Processing Unit (CPU), a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, that may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method for calculating the checksum disclosed in the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

Memory 902, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The Memory 902 may include at least one type of storage medium, and may include, for example, a flash Memory, a hard disk, a multimedia card, a card-type Memory, a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Programmable Read Only Memory (PROM), a Read Only Memory (ROM), a charge Erasable Programmable Read Only Memory (EEPROM), a magnetic Memory, a magnetic disk, an optical disk, and so on. The memory 902 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 902 of the embodiments of the present application may also be circuitry or any other device capable of performing a storage function for storing program instructions and/or data.

By programming the processor 901, the code corresponding to the method for calculating the checksum described in the foregoing embodiments may be solidified into the chip, so that the chip can execute the steps of the method for calculating the checksum in the embodiment shown in fig. 1 when running. How to program the processor 901 is well known to those skilled in the art and will not be described herein.

Based on the same inventive concept, the present application also provides a storage medium storing computer instructions, which when executed on a computer, cause the computer to perform the method for calculating a checksum discussed above.

In some possible embodiments, the aspects of the method for calculating a checksum provided by the present application may also be implemented in the form of a program product, which includes program code for causing an apparatus to perform the steps of the method for calculating a checksum according to various exemplary embodiments of the present application described above in this specification when the program product is run on the apparatus.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method of calculating a checksum, comprising:

2. The method of claim 1, wherein distributing the first plurality of child data to respective checksum accumulation units comprises:

judging whether second subdata with the byte number smaller than the preset byte number exists in each first subdata or not;

3. The method of claim 2, wherein determining whether there is second sub-data in each first sub-data having a byte number less than a preset byte number comprises:

and acquiring the effective byte number in each first subdata, and judging whether the effective byte number in each first subdata is smaller than the preset byte number.

4. The method of claim 1, wherein obtaining the accumulated result obtained by accumulating the first sub-data by each checksum accumulation unit comprises:

and if the first subdata of the first message to be processed does not exist, accumulating and calculating the first subdata of the first message to be processed continuously.

5. The method of claim 1, wherein obtaining the accumulated result obtained by accumulating the first sub-data by each checksum accumulation unit comprises:

6. An apparatus for calculating a checksum, the apparatus comprising: a data splitting unit, a checksum accumulation unit and a merging unit, the checksum accumulation unit comprising a plurality of checksum accumulation modules, wherein,

7. The apparatus of claim 6, wherein the data splitting unit is specifically configured to determine whether there is second sub-data in each first sub-data, where the number of bytes is less than a preset number of bytes; if the message exists, determining an invalid byte bit and an effective byte in the second subdata according to the total byte number of the message to be processed and the byte number of each first subdata; adding a specified numerical value to the invalid byte bit in the second subdata to obtain third subdata; and sending the effective bytes in the first subdata and the third subdata to a checksum accumulation unit.

8. The apparatus of claim 7, wherein the data splitting unit is specifically configured to obtain an effective number of bytes in each first sub-data, and determine whether the effective number of bytes in each first sub-data is smaller than a preset number of bytes.

9. The apparatus according to claim 6, wherein the checksum accumulation unit is further configured to detect whether there is an end flag indicating an end of data of the first message to be processed; if yes, outputting the accumulated result, and clearing the cached accumulated result; and if the first subdata does not exist, accumulating and calculating the first subdata of the first message to be processed continuously.

10. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the method steps of any one of claims 1-5 when executing the computer program stored on the memory.

11. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any one of claims 1-5.