CN114490449B

CN114490449B - Memory access method and device and processor

Info

Publication number: CN114490449B
Application number: CN202210405382.0A
Authority: CN
Inventors: 邵立松; 闫志伟; 王振
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-04-18
Filing date: 2022-04-18
Publication date: 2022-07-08
Anticipated expiration: 2042-04-18
Also published as: CN114490449A

Abstract

The application provides a memory access method, a device and a processor, which are applied to the technical field of computers, the method carries out secondary address translation based on a virtual address after acquiring a memory access request carrying the virtual address to obtain an intermediate physical address, a first access attribute comprising at least one access strategy corresponding to the intermediate physical address, a physical address and a second access attribute comprising at least one access strategy corresponding to the physical address, further takes the access attribute with less access strategies in the first access attribute and the second access attribute as a target access attribute, and finally accesses a storage space corresponding to the physical address according to the target access attribute, because the target access attribute comprises less access strategies, the limitation to the access process is less, and the possibility of difference generated when the same memory space is accessed by other equipment is greatly reduced, and further effectively reducing the possibility of data read/write abnormality in the process of accessing the memory.

Description

Memory access method and device and processor

Technical Field

The present application relates to the field of computer technologies, and in particular, to a memory access method, apparatus, and processor.

Background

A virtual machine is a computer obtained by software simulation, and can operate as a real physical machine to simulate various physical machine functions. The virtual machine usually needs to perform two-stage address translation from a virtual address to an intermediate physical address and then from the intermediate physical address to the physical address, and independent and mutually isolated memory spaces can be provided for the virtual machine through the two-stage address translation, which is beneficial to improving the utilization rate of hardware resources.

In the two-level address translation process, the access attribute adopted when accessing the memory is also determined. The inventor finds that in the prior art, when the access attribute is selected and the memory is accessed according to the access attribute, the problem of data read/write abnormity is easy to occur, and the normal operation of the virtual machine is influenced.

Disclosure of Invention

In view of this, the present application aims to provide a memory access method, a memory access device, and a processor, so as to solve the problem in the prior art that the normal operation of a virtual machine is affected due to the fact that data read/write abnormality is easily caused during memory access.

In a first aspect, the present application provides a memory access method applied to a memory management unit, where the method includes:

acquiring a memory access request from a virtual machine, wherein the memory access request carries a virtual address;

performing secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address and a second access attribute;

wherein the first access attribute comprises at least one access policy corresponding to the intermediate physical address; the second access attribute comprises at least one access strategy corresponding to the physical address, and the access strategy is used for indicating a mode of accessing a storage space;

acquiring a target access attribute based on the first access attribute and the second access attribute;

the target access attribute is an access attribute with a smaller number of access policies in the first access attribute and the second access attribute;

and accessing the storage space corresponding to the physical address according to the target access attribute.

In the application, a secondary address translation is performed on the basis of a virtual address carried by a memory access request to obtain an intermediate physical address, a first access attribute, a physical address and a second access attribute, and in the first access attribute and the second access attribute, the access attribute with less access strategies is used as a target access attribute, and when memory access is performed according to the target access attribute, the limitation on the access process is less, so that the possibility of difference when other devices access the same memory space is greatly reduced, the possibility of data read/write abnormality in the memory access process is effectively reduced, and the normal operation of a virtual machine is favorably ensured.

In a possible implementation manner, the performing secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address, and a second access attribute includes:

performing first-level address translation based on the virtual address to obtain an intermediate physical address and a first access attribute corresponding to the virtual address;

and performing second-level address translation based on the intermediate physical address to obtain a physical address corresponding to the intermediate physical address and a second access attribute.

In the application, a specific implementation process of the secondary address translation is provided, where an intermediate physical address and a first access attribute are obtained through the primary address translation, and a physical address and a second access attribute are obtained through the secondary address translation, where the intermediate physical address is a physical address from the perspective of the virtual machine. Through the secondary address translation, independent and mutually isolated storage spaces can be provided for different virtual machines, the utilization rate of hardware resources is improved, and meanwhile, corresponding access attributes in the address translation process are obtained.

In one possible implementation, the access policy includes at least one of a cache policy, an address alignment policy, an out-of-order policy, a write merge policy, and a write operation confirmation policy.

In the present application, optional components of the access policies are provided, and a clear optional implementation scheme is provided for a person skilled in the art, and the person skilled in the art can select one or more of the access policies provided in the present application, which is helpful for simplifying the selection process of the access policies.

In a possible implementation manner, the memory access policies are carried in a memory access limit table, in the memory access limit table, for each memory access policy, the memory space is accessed according to a unique specified manner through a first value instruction, and the memory space is accessed according to any specified manner through a second value instruction.

In the application, the access policy is borne by the access limiting table, and the selection condition of the mode of accessing the storage space is further indicated by different values for each access policy, namely, the access is indicated according to the unique specified mode through the first value, and the access can be indicated according to any mode through the second value.

In one possible embodiment, the cache policy is used to indicate whether a data read/write process passes through a cache memory;

the address alignment strategy is used for indicating whether the data reading/writing process needs to carry out address alignment;

the out-of-order policy is used for indicating whether to allow the rearrangement of the memory access instruction;

the write merge policy is used for indicating whether to allow merging processing of a plurality of memory access requests;

and the write operation confirmation strategy is used for indicating whether confirmation information corresponding to the write operation needs to be received or not after any memory write operation is completed.

In the application, the basic content of each access strategy is limited, so that a person skilled in the art can clearly and accurately determine the function of each access strategy in practical application, and the implementation difficulty of the application in the practical process is reduced.

In a second aspect, the present invention provides a memory access apparatus, applied to a memory management unit, the apparatus including:

the device comprises a first obtaining unit, a second obtaining unit and a third obtaining unit, wherein the first obtaining unit is used for obtaining a memory access request from a virtual machine, and the memory access request carries a virtual address;

the translation unit is used for performing secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address and a second access attribute;

a second obtaining unit configured to obtain a target access attribute based on the first access attribute and the second access attribute;

and the access unit is used for accessing the storage space corresponding to the physical address according to the target access attribute.

In a possible implementation manner, the translation unit is configured to perform secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address, and a second access attribute, and includes:

In the application, optional components of the access policies are provided, and clear optional implementation schemes are provided for those skilled in the art, and those skilled in the art can select one or more of the access policies provided in the application, which is helpful for simplifying the selection process of the access policies.

the address alignment strategy is used for indicating whether the data read/write process needs to be subjected to address alignment;

the write merge policy is used for indicating whether to allow the merge processing of a plurality of memory access requests;

In a third aspect, the present application provides a processor comprising: the system comprises a processor core and a memory management unit, wherein a virtual machine is arranged in the processor core;

initiating a memory access request to the memory management unit through the virtual machine;

the memory management unit responds to the memory access request, and executes the memory access method according to any one of the first aspect of the present application to determine a target access attribute, so as to access a storage space corresponding to the physical address according to the target access attribute.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic diagram of a computer architecture according to an embodiment of the present application.

Fig. 2 is a process diagram of two-level address mapping.

FIG. 3 is a diagram of a memory access attribute determination process.

Fig. 4 is a flowchart of a memory access method according to an embodiment of the present invention.

Fig. 5 is a flowchart of another memory access method according to an embodiment of the present invention.

FIG. 6 is a flow diagram illustrating another memory access process.

Fig. 7 is a block diagram of a memory access device according to an embodiment of the present invention.

Fig. 8 is a block diagram of a processor according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

First, relevant software or concepts related to embodiments of the present application will be described:

virtual Machines (VMs) are software-emulated computer systems that have complete hardware system functionality, and can emulate various physical Machine functionality on a physical Machine, providing an independent, isolated computing environment. By running the virtual machine in the physical machine, a user can obtain the use effect of two or even more physical machines under the condition of only preparing one physical machine, and the utilization rate of the hardware resources of the physical machine is effectively improved.

A Virtual Machine Manager (VMM) may be regarded as an intermediate software layer running between a physical Machine and a Virtual Machine, and the Virtual Machine monitor may allow an operating system and corresponding application software in multiple Virtual machines to share hardware resources of the physical Machine. Further, the virtual machine monitor may provide a certain memory protection function on the basis of coordinating hardware resource allocation of the physical machine, for example, the virtual machine monitor may control whether the virtual machine can access a specific physical memory, and set a corresponding relationship between the physical memory and the virtual address space, which is important for the virtual machine monitor to implement isolation between the virtual machines.

QEMU (quick Emulator), which can provide various types of software simulation equipment for the virtual machine by using the physical memory.

Virtual Address Space (Virtual Address Space) and Virtual Address (Virtual Address, VA), in the virtualization technology, the Virtual Address Space is an Address Space directly faced by software or an operating system, and of course, the Virtual Address Space is not a real Space capable of storing data, and the size of the Virtual Address Space is determined by the number of bits of a processor. Accordingly, any address in the virtual address space is considered as a virtual address. Typically, the address used by the application software or operating system to initiate a memory access request is a virtual address.

A Physical Address Space (Physical Address Space) and a Physical Address (Physical Address, PA), where the Physical Address Space is simply referred to as a Physical memory and is an actual capacity of the storage, and the Physical Address is an Address used when accessing the Physical memory. Typically, the physical address space of a computer system is only a subset of the virtual address space.

In this application, the Intermediate Address space may be understood as a Physical Address space from the perspective of the virtual machine, and of course, the Intermediate Address space and the virtual Address space are both virtual storage spaces. Accordingly, any address in the intermediate address space is considered an intermediate physical address.

Two-stage address translation, namely address translation, is a process of determining a physical address corresponding to any virtual address according to a preset mapping relation between the virtual address and the physical address, and based on the process, the physical address corresponding to the virtual address is determined through only one address translation, and the process can be defined as one-stage address translation. Correspondingly, firstly, an intermediate physical address corresponding to the virtual address is determined, and then, a physical address corresponding to the intermediate physical address is determined, namely, a process of determining the physical address corresponding to the virtual address through two address translations is a two-stage address translation.

The Page Table is a data structure for recording mapping relationships between different types of spatial addresses, and is composed of a record representing a mapping rule, and each record is called a Page Table Entry (PTE). In practical applications, the page table has a plurality of specific implementations, which can be selected according to application requirements and will not be expanded in detail here.

A Memory Management Unit (MMU), one of core components of a Central Processing Unit (CPU), is usually integrated inside the CPU, and is a hardware module responsible for Processing Memory access requests of the CPU, and the main functions include address translation, Memory protection, and control of a CPU cache.

Based on the above, referring to fig. 1, fig. 1 is a schematic diagram of a computer architecture provided in an embodiment of the present application, where the computer architecture provided in the embodiment of the present application includes: CPU1, address bus 2, and memory 3, CPU1 further includes CORE (i.e., processor CORE) 11 and MMU 12.

In the embodiment of the present application, the CORE11 refers to other components of the CPU1 except the MMU12, for example, logical operation units, decoders, and register files, and the specific configuration and implementation of the CORE11 are not limited in the present invention.

The MMU12 is connected to the CORE11 via an internal bus (not shown in FIG. 1). The MMU12 is generally responsible for processing memory access requests in which the access address is a virtual address, and therefore requires address translation of the virtual address, i.e., the virtual address is translated to a corresponding physical address. On the basis of address translation, the MMU12 also restricts and restricts the specific process of the CPU1 accessing the memory 3, thereby implementing a memory protection function. The detailed implementation of address translation and memory protection for MMU12 will be described in more detail below and will not be described in detail herein.

The address bus 2 connects the CPU1 and the memory 3, and the CPU1 completes access to the memory 3 through the address bus 2. The present invention is not limited to the specific implementation of the address bus 2 and the memory 3.

Further, at least one virtual machine 111, i.e., VM1-VMn of FIG. 1, may be run in the CORE 11. In the scenario where multiple virtual machines are running in CORE11, the VMM112 may be configured via the host operating system, managing multiple virtual machines via VMM 112.

In the computer architecture shown in fig. 1, one of the main functions of the VMM112 for each VM is to control the memory view of each VM, and specifically, whether a VM can access a specific physical memory, and the location of the physical memory in the memory space of the virtual machine, so that the VM can only see the physical memory allocated to itself.

To accomplish this, the VMM112 provides each VM with an intermediate address space, which, as previously described, is a VM-view physical address space, meaning that if only one address translation is performed, only the IPA corresponding to VA is available. Therefore, the original process of determining PA directly by VA through one-stage address translation is changed into two-stage address translation of determining IPA by VA and determining PA by IPA, and certainly, the method can also be regarded as performing two address translations, wherein IPA is determined by VA for the first address translation and PA is determined by IPA for the second address translation.

Specifically, referring to fig. 2, the two-stage address translation includes two stages, stage1 and stage2, wherein stage1 refers to mapping VA to obtain IPA, and stage2 refers to mapping IPA to obtain final PA.

When two-level address translation is performed, two-level page tables need to be established correspondingly, wherein a page table corresponding to the stage1 is a first page table, and a page table corresponding to the stage2 is a second page table. In practical applications, the first page table is typically allocated and managed by a virtual machine, and the second page table is typically allocated and managed by a virtual machine monitor.

After obtaining the VA (i.e., the target VA) in the memory access request, MMU12 first performs a first level address translation according to the first page table, i.e., determines the target IPA corresponding to the target VA. The MMU12 then further performs a second level address translation, i.e., determines a target PA corresponding to the target IPA, based on the second page table.

It should be noted that, for a physical machine, the QEMU belongs to common application software, and therefore, when a virtual machine accesses a virtual device provided by the QEMU, it is actually accessing a physical address, and secondary address translation is required.

Furthermore, the page table records not only mapping relationships between different types of addresses, but also access attributes of the storage space corresponding to the corresponding addresses, where the access attributes may include two types, namely, a normal attribute and a device attribute, where the normal attribute is also referred to as a memory attribute, and the device attribute is also referred to as a device attribute. The access attribute is represented by different access strategies, and different access attributes influence specific access operation when the CPU accesses the storage space, so that the purpose of memory protection can be achieved by setting the access attribute.

As shown in fig. 3, after the VM initiates a memory access request, the MMU needs to perform two-level address translation, specifically, when performing the address translation of stage1, the MMU determines an access attribute according to the first page table, and records the access attribute as a first access attribute; further, when the stage2 address translation is performed, the MMU determines another access attribute according to the second page table, and records the access attribute as the second access attribute.

It is to be understood that the first access attribute and the second access attribute correspond to the same physical address, i.e. to the same memory space. Also, typically, the first access attribute and the second access attribute are different, and therefore, the MMU selects one of the two as the final access attribute, i.e., the target access attribute.

The inventor finds that in the prior art, when the target access attribute is selected and the memory is accessed according to the target access attribute, the problem of data read/write abnormity is easy to occur, the normal operation of the virtual machine is influenced, and even the operation of the physical machine is influenced.

In order to solve the above problems, the present application provides a memory access method, which takes the access attribute with less access limitation conditions in the first access attribute and the second access attribute as a target access attribute for the memory access process of the VM, accesses the memory according to the access attribute with less access limitation conditions, reduces the possibility of data read/write abnormality, and is helpful to ensure the normal operation of the virtual machine and the physical machine.

The memory access process provided by the embodiment of the present application will be described in detail below with reference to fig. 4 to 6.

Referring to fig. 4, a flowchart of a memory access method provided by an embodiment of the present application is shown, where the method is applied to a processor, and as shown in fig. 4, the method may include the following steps:

and S100, acquiring a memory access request from the virtual machine.

In practical application, application software installed in the VM or the VM operating system itself may generate an access request, i.e., a memory access request, for requesting access to the memory space according to an operation requirement. Further, the memory access request carries a virtual address, where the virtual address is used to indicate a specific memory space targeted by the memory access, and besides, the memory access request may also carry a specific memory access operation, such as writing data into the memory space or reading data in the memory space, and the like.

It should be noted that the memory access method provided in the embodiment of the present application is not only applicable to a scenario where a VM initiates a memory access request and performs a memory read operation, but also applicable to other memory access processes that require two-level address translation.

S110, performing secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address and a second access attribute.

After acquiring a memory access request initiated by a VM, the MMU first performs a first level address translation. As described above, the first page table managed and maintained by the VM is used to implement the first level address translation, and the MMU determines the intermediate physical address corresponding to the virtual address according to the mapping relationship between the virtual address and the intermediate physical address recorded by the first page table.

Meanwhile, the MMU may determine an access attribute corresponding to the intermediate physical address according to the record of the first page table, that is, a first access attribute, where the first access attribute includes at least one access policy.

Further, the MMU performs a second-stage address translation according to a second page table managed and maintained by the VMM, that is, determines a physical address corresponding to the intermediate physical address based on the second page table, and may also determine an access attribute corresponding to the obtained physical address, that is, a second access attribute, according to the second page table. The second access attribute, like the first access attribute, also includes at least one access policy.

It should be noted that the access policy mentioned in the above is used to indicate the manner of accessing the storage space. That is to say, the first access attribute and the second access attribute are respectively characterized by different access policies, in practical application, the selectable access policies have a plurality of items, and different access policies are selected, so that different ways of accessing the storage space can be indicated.

Based on the foregoing, in an exemplary embodiment, the storage space may be divided into two access attributes, such as a normal attribute and a device attribute.

For example, the first access attribute is a normal attribute, and the second access attribute is a device attribute. As another example, the first access attribute is a device attribute and the second access attribute is a normal attribute.

In one example, the access attributes may be characterized by one or more of the access policies shown in Table 1:

TABLE 1

	Caching strategy	Address alignment policy	Out-of-order policy	Write merge strategy	Write operation validation strategy
						Normal Properties	Can select	Can select	Default support	Default support	Does not need to use
Device attribute	No buffer memory	Address alignment	Can select	Can select	Can select

The cache policy is used for indicating whether data read/write process to the memory needs to pass through the cache memory. For the physical memory with normal attribute, the physical memory can be selected to pass through the cache memory or not pass through the cache memory according to the actual access requirement, and under the condition of not passing through the cache memory, the VM can directly access the memory to complete the data read/write operation without passing through the cache memory. For the physical memory with device attribute, the actual access process does not need to pass through a cache memory, and the physical memory can be directly read/written.

Address alignment is a way to arrange data in a computer memory and access data, and when data is read and written in the memory, the data is operated according to integer multiple of a basic unit, the basic unit corresponds to the number of bits of a secondary system processed by a computer processor at the same time, for example, in a 32-bit system, each read/write operation can be completed according to integer multiple of 4 bytes. Accordingly, the address alignment policy is used to indicate whether to start from a specified physical address when performing data read/write operations on the memory, and the specified physical address is determined based on the basic unit of data read/write of the computer system. For the normal attribute physical memory, address alignment may be optionally required or not required, and for the device attribute physical memory, address alignment is required.

The out-of-order policy is used to indicate whether out-of-order access to memory is supported. If the disorder is supported, the memory access instruction is allowed to be rearranged, and if the disorder is not supported, the memory access instruction is not allowed to be rearranged, and the execution is required to be strictly performed according to the instruction sequence. For the normal attribute physical memory, the disorder is supported by default, and for the device attribute physical memory, the selection can be carried out according to the actual requirement, but the default support is not;

the write merge policy is used for indicating whether merge processing is supported for a plurality of memory access requests. The normal attribute physical memory supports the write merge strategy by default, and the device attribute memory can be selected according to the actual situation and is not supported by default.

The write operation confirmation strategy is used for indicating whether confirmation information corresponding to the write operation needs to be received or not after any memory write operation is completed, wherein the confirmation information is fed back by the memory. If the write operation is required to be confirmed, after one-time memory write operation is completed, only the confirmation information is obtained, the subsequent other operations can be executed, if the write operation is not required to be confirmed, after one-time write operation confirmation is completed, the subsequent operations are directly carried out. The normal attribute physical memory does not need to be confirmed by writing operation, and the device attribute physical memory needs to select whether to confirm by writing operation according to actual conditions.

It can be seen from table 1 and the above that different access attributes correspond to different access policies, and the difference in the access policies affects the specific access process and data read/write position of the memory, so that the purpose of restricting the access process and protecting the memory can be achieved by representing the access attributes through the access policies and accessing the memory according to the access attributes.

It should be noted that, the present invention is not limited to the specific contents and requirements of the access policies described in table 1. Further, for the characterization or limitation of the access attribute, the memory access policy is not limited to the five memory access policies provided in table 1, and may also include other memory access policies.

And S120, acquiring the target access attribute based on the first access attribute and the second access attribute.

Based on the above, the first access attribute and the second access attribute are characterized by different numbers of access policies.

For example, for the normal attribute, it is necessary to select whether to pass through the cache in the process of accessing the memory, so the cache policy is one of the access policies for characterizing or defining the normal attribute, correspondingly, for the device attribute, it is necessary to explicitly define that the cache is not required, and it is also necessary to record the selection condition for the cache policy in the page table, so the cache policy is also one of the access policies for characterizing the device attribute.

For another example, for a normal attribute, an address alignment policy needs to support address alignment or does not support address alignment, that is, an explicit selection needs to be made, the address alignment policy may be one of the access policies representing the normal attribute, correspondingly, for a device attribute, address alignment needs to be supported, and the address alignment policy is also the access policy that the device attribute needs to set.

For another example, the disorder policy is a default disorder support policy for the normal attribute, and generally does not need to be changed or selected, in practical applications, the disorder policy may not be set in the page table, and in this case, the disorder policy is not used as the access policy for characterizing the normal attribute. And for the device attribute, whether the disorder policy is supported or not must be selected, and the device attribute must include the access policy, so that the disorder policy is used as the access side rate for representing the device attribute.

In summary, under the optional implementation manner provided in table 1, for the normal attribute, two access policies are included, that is, a cache policy and an address alignment policy, and of course, the normal attribute may also include a write operation confirmation policy, and the device attribute includes five access policies shown in table 1, and obviously, there are fewer access policies corresponding to the normal attribute.

It is understood that the access policy is used to indicate the manner of accessing the memory space, and meanwhile, the access policy may also be understood as the limitation on the memory space access process, such as that the cache must be passed through, the address alignment must be performed, and the program instruction must be executed in program order (i.e. out-of-order is not supported), and the like, which means that the more the access attribute includes the access policy, the more the limitation on the memory space access process is. Based on this, the memory access method provided in this embodiment takes the access attribute with less access policy in the first access attribute and the second access attribute as the target access attribute.

In the former case, the normal attribute comprises two access strategies, the device attribute comprises five access strategies, and the method takes the normal attribute as the target access attribute based on the principle.

And S130, accessing the storage space corresponding to the physical address according to the target access attribute.

Because the access attribute with less number of the included access strategies is used as the finally adopted target access attribute, when the memory access is carried out according to the target access attribute, the access rules which should be followed in the access process are less, the possibility of generating difference when the same memory space is accessed by other equipment is greatly reduced, and the possibility of data read/write errors is further effectively reduced.

It should be noted that, the present invention is not limited to the specific process of performing memory access according to the target access attribute.

In summary, in the memory access method provided in the embodiment of the present invention, the access attribute including less access policies is used as the target access attribute in the first access attribute and the second access attribute, and when the memory access is performed according to the target access attribute, the possibility of difference between the target access attribute and the target access attribute when the memory access is performed and the target access attribute is the same as that when other devices access the same memory space is greatly reduced.

Optionally, referring to fig. 5, fig. 5 is a flowchart of another memory access method provided in the embodiment of the present invention, where a scenario in which a virtual machine accesses a memory is taken as an example to describe a memory access process in the embodiment, and of course, the method is also applicable to other scenarios requiring two levels of address translation, and details are not described here. As shown in fig. 5, the flow of the method may include, but is not limited to, the following steps:

s200, the VM initiates a memory access request.

In practical applications, the memory access request may be initiated by application software running in the VM, or may be initiated by the VM operating system, or of course, the memory access request may also be initiated by other manners. It is important that the memory access request initiated by the VM carries the virtual address targeted by the access, and certainly, the memory access request may also carry specific memory access operations, such as writing data into the memory space or reading data in the memory space, and the like.

S210, the MMU obtains the memory access request.

The specific implementation manner of the MMU obtaining the memory access request may be implemented with reference to the related art, and the present invention is not limited specifically.

S220, the MMU performs first-level address translation based on the virtual address to obtain an intermediate physical address and a first access attribute.

The MMU and the CORE are in communication connection through an internal bus, and after the VM initiates a memory access request, the MMU receives the memory access request through the internal bus, and further resolves the memory access request to obtain a virtual address.

Further, the MMU first performs stage1 address translation, i.e. determines an intermediate physical address corresponding to the virtual address according to the first page table managed and maintained by the VM, and an access attribute corresponding to the intermediate physical address, i.e. a first access attribute.

As described above, the VM can simulate a computer system having complete hardware system functions, and can simulate various physical machine functions on a physical machine, and work like a real physical machine, that is, the VM performs data interaction with peripheral devices in the role of the physical machine, and a memory space accessed by the VM better conforms to the device attribute, so that when a programmer sets the first page table, for an access attribute setting of the memory space corresponding to an intermediate physical address (from the perspective of the VM, the intermediate physical address is a physical address corresponding to a virtual address), in most cases, the device attribute is selected, and based on this, in this embodiment, the first access attribute is the device attribute.

S230, the MMU performs second-level address translation based on the intermediate physical address to obtain a physical address and a second access attribute.

After determining the intermediate physical address, the MMU further performs a stage2 stage address translation according to the second page table, that is, determines a physical address corresponding to the intermediate physical address according to the second page table.

As mentioned above, the second page table is managed and maintained by the VMM, and the VMM is an intermediate software layer between the virtual machine and the physical machine, and the data interaction object of the VMM is the physical machine in most cases, and more specifically, the VMM directly accesses the memory of the physical machine in more cases, so that when setting the second page table of the VMM, a programmer usually considers that the storage space corresponding to each physical address in the second page table better conforms to the normal attribute, and therefore, the second access attribute determined according to the second page table is generally the normal attribute.

S240, the MMU obtains the target access attribute based on the first access attribute and the second access attribute.

Through the foregoing steps, the first access attribute is a device attribute, the second access attribute is a normal attribute, and it can be known from the content corresponding to the step S120 in the embodiment shown in fig. 4 that the access policy corresponding to the normal attribute is less than the access policy of the device attribute, so in this step, the MMU finally takes the normal attribute as the target access attribute.

S250, the MMU accesses the storage space corresponding to the physical address according to the target access attribute.

In an exemplary embodiment, the access policy included in the access attribute is carried in an access restriction table, and the access restriction table may be a page table as described above. Further, the access limit table indicates the selection condition of the corresponding access strategy through different configuration values for each access strategy. Specifically, the memory space is accessed according to a unique specified mode through a first value instruction, and the memory space is accessed according to any specified mode in the memory access strategy through a second value instruction.

For example, taking the out-of-order policy as an example, the memory access restriction table indicates that the out-of-order policy is not supported by the first value, that is, the processor is not allowed to rearrange the memory access instructions, and only can execute each memory access instruction in sequence according to the predetermined instruction sequence, in this case, it is the only specified access manner to execute each memory access instruction in sequence according to the predetermined instruction sequence; correspondingly, the access limiting table represents that the out-of-order strategy is supported through the second value, and the processor can select two access modes according to requirements, namely, any one of two modes of executing the memory access instruction out-of-order and executing the memory access instructions in sequence according to the set instruction sequence is selected.

Illustratively, the first value may be 1; the second value may be 0.

As described above, the access attribute of the storage space is characterized by multiple access policies, or defined by multiple access policies, the page table does not directly record the storage space corresponding to a certain physical address as a normal attribute, certainly, the page table does not directly record the storage space corresponding to a certain physical address as a device attribute, but records the configuration values of the corresponding access attribute for different access policies in a preset field, or can be understood as representing the access attribute corresponding to the corresponding storage space by recording the specific requirements of the access policies in the page table.

For example, for a certain physical address, the access policy recorded in the page table is: caching and address alignment are needed, other access strategies are not included, according to the specific requirements of the access strategies, the access attribute of the storage space corresponding to the physical address can be determined to be a normal attribute by combining the table 1, and on the contrary, if the access attribute is set according to the requirements of each access strategy of the device attribute in the table 1, the access attribute of the storage space corresponding to the physical address is the device attribute.

Based on this, the accessing the storage space corresponding to the physical address according to the target access attribute in this step may specifically be to determine an access manner corresponding to each access policy according to a configuration value of each access policy corresponding to a normal attribute recorded in the access restriction table, and further access the storage space corresponding to the physical address according to each specifically selected access manner. In practical applications, the MMU checks whether the memory access request satisfies each memory access policy of the target access attribute, and if so, sends the physical address to a physical bus in the computer architecture shown in fig. 1, and the CPU further completes the subsequent memory access operation, and if not, the CPU starts the related operation under the condition of memory access failure. As to the completion of the memory access operation according to the physical address and the related operations under the condition of the memory access failure, the present invention is not limited thereto.

Based on the above, referring to fig. 6, for a memory access request initiated by a VM, the MMU first performs address translation of stage1, determines an intermediate physical address corresponding to a virtual address according to the first page table, and determines that a memory access attribute corresponding to stage1 is a device attribute according to the first page table. Then, the MMU translates the address of stage2, determines the physical address corresponding to the intermediate physical address according to the second page table, and determines the memory access attribute corresponding to stage2 as the normal attribute according to the second page table. Further, the MMU sets the device attribute and the normal attribute including the normal attribute with less access policy as the final target access attribute.

It is conceivable that, if the access attributes corresponding to stage1 and stage2 are obtained through two-level address mapping, and then the target access attributes are determined according to the opposite rules, the access attributes including more access policies in the first access attribute and the second access attribute are used as the target access attributes, that is, the device attribute corresponding to stage1 is used as the target access attribute finally adopted when the VM accesses the memory, and the increase of the restriction conditions means that the possibility of generating a difference when accessing the same memory space as other devices is increased, which easily causes data read/write abnormality in the process of accessing the memory.

It can be understood that, in practical applications, the case where the state 1 adopts the normal attribute and the state 2 adopts the device attribute rarely occurs, and even if such a case occurs, according to the memory access method provided by the present application, the memory access attribute finally adopted by the VM after two-level address translation is still the normal attribute, which can also reduce the possibility of data read/write abnormality during the process of accessing the memory, and is helpful to ensure the normal operation of the virtual machine and the physical machine.

Further, for the case that both stage1 and stage2 access the memory according to the device attribute, the memory access method provided by the present application is not applicable, and a programmer needs to adjust the page tables corresponding to the VM and the VMM. Of course, this situation goes against the basic understanding of the VM and VMM performance by programmers and rarely occurs in practical applications.

The memory access device provided by the invention belongs to the same application concept as the memory access method provided by the embodiment of the application, can execute the memory access method provided by any embodiment of the application, and has the corresponding functional modules and beneficial effects of executing the memory access method. For details of the technology that are not described in detail in this embodiment, reference may be made to the memory access method provided in this embodiment, and details are not described here again.

Optionally, referring to fig. 7, fig. 7 is a block diagram of a structure of a memory access device according to an embodiment of the present invention, where the memory access device according to the embodiment includes:

a first obtaining unit 10, configured to obtain a memory access request from a virtual machine, where the memory access request carries a virtual address;

a translation unit 20, configured to perform secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address, and a second access attribute;

wherein the first access attribute comprises at least one access policy corresponding to the intermediate physical address; the second access attribute comprises at least one access strategy corresponding to the physical address, and the access strategy is used for indicating a mode of accessing the storage space;

a second obtaining unit 30 configured to obtain a target access attribute based on the first access attribute and the second access attribute;

the target access attribute is an access attribute with a small number of access strategies in the first access attribute and the second access attribute;

and the accessing unit 40 is configured to access the storage space corresponding to the physical address according to the target access attribute.

In a possible implementation, the translation unit 20 is configured to perform secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address, and a second access attribute, and includes:

In a possible implementation, the access policy is carried in an access limit table, in which, for each access policy, the storage space is accessed in a uniquely specified manner by a first value indication, and the storage space is accessed in any specified manner by a second value indication.

In one possible embodiment, the caching policy is used to indicate whether a data read/write process passes through the cache memory;

the address alignment strategy is used for indicating whether the data read/write process needs to carry out address alignment or not;

the out-of-order strategy is used for indicating whether to allow the rearrangement of the memory access instruction;

the write merge policy is used for indicating whether to allow the merge processing of the multiple memory access requests;

the write operation confirmation strategy is used for indicating whether confirmation information corresponding to the write operation needs to be received or not after any memory write operation is completed.

Further, referring to fig. 8, fig. 8 is a block diagram of a processor according to an embodiment of the present invention, where the processor 100 according to the embodiment includes: the system comprises a processor core 101 and a memory management unit 102, wherein a virtual machine is arranged in the processor core 101;

the processor core 101 is in communication connection with the memory management unit 102;

initiating a memory access request to the memory management unit 102 through the virtual machine;

the memory management unit 102 executes the memory access method provided in any of the above embodiments to determine the target access attribute, so as to access the storage space corresponding to the physical address according to the target access attribute.

In some embodiments, the present embodiment also provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash Memory, a U-disk, an SD (Secure Digital Card) Card, an MMC (Multimedia Card) Card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the one or more instructions cause the processors to execute the Memory access method described above. For related implementation, reference is made to the foregoing description, which is not repeated herein.

In addition to the above methods and apparatus, embodiments of the present application may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the memory access methods according to the various embodiments of the present application described in the above summary of the present specification.

The computer program product may include program code for carrying out operations for embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.

Those skilled in the art will appreciate that the disclosure of the present disclosure is susceptible to numerous variations and modifications. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.

Further, while the present disclosure makes various references to certain elements of a system according to embodiments of the present disclosure, any number of different elements may be used and run on a client and/or server. The units are merely illustrative and different aspects of the systems and methods may use different units.

Flow charts are used in this disclosure to illustrate steps of methods according to embodiments of the disclosure. It should be understood that the preceding or subsequent steps need not be performed in the exact order shown. Rather, various steps may be processed in reverse order or simultaneously. Also, other operations may be added to the processes.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by instructing relevant hardware through a computer program, and the program may be stored in a computer readable storage medium, such as a read-only memory, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A memory access method applied to a memory management unit, the method comprising:

obtaining a target access attribute based on the first access attribute and the second access attribute;

2. The method of claim 1, wherein performing a secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address, and a second access attribute comprises:

3. The method of claim 1, wherein the memory access policy comprises at least one of a cache policy, an address alignment policy, an out-of-order policy, a write merge policy, and a write operation confirmation policy.

4. The method according to claim 3, wherein the access policy is carried in an access restriction table, and in the access restriction table, for each access policy, the storage space is accessed in a unique specified manner through a first value instruction, or the storage space is accessed in any specified manner through a second value instruction.

5. The method of claim 3, wherein the caching policy is used to indicate whether data read/write processes are going through a cache memory;

6. A memory access device applied to a memory management unit, the device comprising:

7. The apparatus of claim 6, wherein the translation unit is configured to perform a secondary address translation based on the virtual address to obtain an intermediate physical address, a first access attribute, a physical address, and a second access attribute, and comprises:

8. The apparatus of claim 6, wherein the memory access policy comprises at least one of a cache policy, an address alignment policy, an out-of-order policy, a write merge policy, and a write operation confirmation policy.

9. The apparatus of claim 8, wherein the access policy is carried in an access restriction table, and in the access restriction table, for each access policy, the memory space is accessed in a unique specified manner through a first value instruction, or the memory space is accessed in any specified manner through a second value instruction.

10. The apparatus of claim 8, wherein the cache policy is used to indicate whether a data read/write process is going through a cache memory;

11. A processor, comprising: the device comprises a processor core and a memory management unit, wherein a virtual machine is arranged in the processor core,

determining a target access attribute by the memory management unit executing the memory access method according to any one of claims 1 to 5 in response to the memory access request, so as to access the storage space corresponding to the physical address according to the target access attribute.