CN114448453B - Method and system for determining radio frequency signal of telemetry transmitter - Google Patents
Method and system for determining radio frequency signal of telemetry transmitter Download PDFInfo
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- CN114448453B CN114448453B CN202111567037.9A CN202111567037A CN114448453B CN 114448453 B CN114448453 B CN 114448453B CN 202111567037 A CN202111567037 A CN 202111567037A CN 114448453 B CN114448453 B CN 114448453B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2209/00—Arrangements in telecontrol or telemetry systems
- H04Q2209/40—Arrangements in telecontrol or telemetry systems using a wireless architecture
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Abstract
The invention relates to a method and a system for determining radio frequency signals of a telemetry transmitter, wherein the method comprises the following steps: the FPGA chip sends 485 communication commands to a 485 data analysis module; if the 485 data analysis module extracts an unlocking command and a frequency point binding command from the 485 communication command, 8-bit frequency point information is searched in a register according to an effective frequency code in the frequency point binding command, and the 8-bit frequency point information is sent to the EEPROM read-write module; the EEPROM read-write module erases the stored frequency point information, stores the first frequency point information and sends the first frequency point information to the configuration module; the configuration module determines a corresponding standard frequency shift keying modulation waveform; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point. The invention realizes the external controllability of the frequency point and solves the problem that the frequency point cannot be adjusted immediately due to the fixed hardware design parameters of the traditional transmitter.
Description
Technical Field
The present invention relates to the field of telemetry transmitters, and in particular, to a method and system for determining a radio frequency signal of a telemetry transmitter.
Background
Along with the function of obtaining data in the test field of telemetry, the function of obtaining data has the effects of providing effective data and shortening the development period for design improvement, the necessity of a space telemetry system in the test and operation stages is higher and higher, telemetry tasks are increased continuously to cause the telemetry frequency band to be crowded and crowded, so that the transmitter frequency adaptation has more severe requirements, and the telemetry transmitter based on digital modulation has prominent advantages due to the frequency point adjustable function.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present invention provides a method and a system for determining a radio frequency signal of a telemetry transmitter.
In a first aspect, the present invention provides a method for determining a radio frequency signal of a telemetry transmitter, comprising:
when receiving a 485 communication command, the FPGA chip sends the 485 communication command to a 485 data analysis module;
if the 485 data analysis module extracts an unlocking command and a frequency point binding command from the 485 communication command, searching corresponding 8-bit frequency point information in a register according to an effective frequency code in the frequency point binding command, recording the 8-bit frequency point information as first frequency point information, and sending the first frequency point information to an EEPROM read-write module;
the EEPROM read-write module erases the stored frequency point information when receiving the first frequency point information, stores the first frequency point information and sends the first frequency point information to a configuration module;
the configuration module determines a corresponding standard frequency shift keying modulation waveform according to the first frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
In a second aspect, the invention provides a radio frequency signal determination system for a telemetry transmitter, comprising:
the FPGA chip is used for sending the 485 communication command to the 485 data analysis module when receiving the 485 communication command;
the 485 data analysis module is used for searching corresponding 8-bit frequency point information in a register according to an effective frequency code in the frequency point binding command if an unlocking command and a frequency point binding command are extracted from the 485 communication command, recording the 8-bit frequency point information as first frequency point information, and sending the first frequency point information to the EEPROM read-write module;
the EEPROM read-write module is used for erasing the stored frequency point information when receiving the first frequency point information, storing the first frequency point information and sending the first frequency point information to the configuration module;
the configuration module is used for determining a corresponding standard frequency shift keying modulation waveform according to the first frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
According to the method and the system for determining the radio frequency signal of the telemetry transmitter, when the 485 communication command input from the outside is received, the 485 data analysis module analyzes the command to obtain the unlocking command and the frequency point binding command, and then corresponding 8-bit frequency point information is searched in the register according to the effective frequency code in the frequency point binding command, and the 8-bit frequency point information is stored in the EEPROM read-write module, so that the configuration module generates a corresponding intermediate frequency signal according to the 8-bit frequency point information. It can be seen that the embodiment of the invention solves the problem that the conventional telemetry transmitter cannot realize multiple-shot alignment due to fixed frequency points, analyzes 485 communication commands and acquires unlocking commands and frequency point binding commands from the commands by designing software codes, ensures that the frequency points are externally controllable, namely, frequency point information is changed or adjusted, and simultaneously solves the problem that the conventional transmitter cannot adjust the frequency points in real time due to fixed hardware design parameters in the process of the outfield flight test.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of a method for determining RF signals of a telemetry transmitter according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of the spot binding in the embodiment of the invention;
FIG. 3 is a flow chart of the intermediate frequency signal output in the embodiment of the invention;
fig. 4 is a schematic flow chart of frequency point reading after power-up in the embodiment of the invention;
fig. 5 is a schematic flow chart of data processing performed in the 485 data receiving module in the embodiment of the invention;
fig. 6 is a schematic flow chart of frequency point extraction performed by the 485 analysis receiving module in the embodiment of the invention;
fig. 7 is a schematic flow chart of a read-write operation of the EEPROM read-write module in the embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In a first aspect, an embodiment of the present invention provides a method for determining a radio frequency signal of a telemetry transmitter, referring to fig. 1 to 3, the method may include steps S110 to S140 as follows:
s110, when receiving a 485 communication command, the FPGA chip sends the 485 communication command to a 485 data analysis module;
it is understood that the 485 communication command is a 485 communication command externally input into the telemetry transmitter.
In the implementation, before the 485 communication command is input to the 485 data analysis module, the S110 sends the 485 communication command to the 485 data receiving module, and the 485 data receiving module processes some data and then sends the data to the 485 data analysis module.
That is, the step S110 may specifically include the following steps:
s111, when receiving a 485 communication command, the FPGA chip sends the 485 communication command to a 485 data receiving module;
and S112, the 485 data receiving module removes frame head and frame tail information of the 485 communication command, performs zero deletion processing on the data after the frame head and frame tail information is removed, stores the data after the zero deletion processing into a memory, performs CRC (cyclic redundancy check) on the data after the zero deletion processing, outputs the data stored in the memory and the corresponding address after the CRC passes, and outputs corresponding data valid enabling information.
In an implementation, the performing zero-puncturing processing on the data from which the header and tail information of the frame is removed may include: and detecting the code element 1 in the data from which the frame head and frame tail information is removed, and deleting the code element 0 after the preset number of continuous code elements 1 after detecting the preset number of continuous code elements 1. The preset number may be set according to a specific scenario, for example, 5 hereinafter.
For example, the 485 data receiving module may implement a 485 data receiving function, output parallel 485 data, 485 data enable, data count, etc., and the 485 data receiving module may specifically include an sdlc_rx sub-module, a delete_insert_zero sub-module, and a CRC16_ccitt_u8 sub-module. The sdlc_rx submodule analyzes 485 communication command according to the requirement of SDLC protocol (namely a data link layer protocol) to obtain data, and the interface module is realized in the FPGA, and referring to fig. 5, the submodule mainly completes the functions of frame head and frame tail identification, address verification, 0 deletion processing and CRC verification. And the SDLC-rx submodule judges the frame head and the frame tail of the received 485 communication command according to the protocol and removes the frame head and the frame tail at the same time. For 485 data, every 5 consecutive symbols "1" would be followed by one symbol "0". Therefore, when 485 communication command is received, symbol 1 is detected for the data with frame head and frame tail removed, when 5 continuous symbols 1 are detected, the following symbols 0 are deleted, and parallel data with the deleted 0 are stored in RAM. And performing CRC (cyclic redundancy check) on the data subjected to the zero deleting operation, outputting the data in the RAM and the corresponding address after the CRC is passed, and generating corresponding data effective enabling. If the CRC check is not passed, the 485 communication command is received with errors, and 485 data is not output.
S120, if the 485 data analysis module extracts an unlocking command and a frequency point binding command from the 485 communication command, searching corresponding 8-bit frequency point information in a register according to an effective frequency code in the frequency point binding command, marking the 8-bit frequency point information as first frequency point information, and sending the first frequency point information to an EEPROM read-write module;
in practice, referring to fig. 6, the 485 data analysis module analyzes the received data, first analyzes the unlocking command, and then waits for analyzing the frequency point binding command. After the frequency point binding command is analyzed, the effective frequency code can be extracted from the frequency point binding command, and then 8-bit frequency point information corresponding to the effective frequency code is searched in the register. For example, if the effective frequency code of two bits is 01, reading the 8-bit frequency point information corresponding to 01 in the register, and sending the 8-bit frequency point information to the EEPROM read-write module.
It can be understood that the 485 data analysis module needs to judge the unlocking command and the frequency point binding command in the received data according to the protocol, complete the command detection under the condition of not overtime, extract the frequency point information of the corresponding position, output the frequency point information and the data enabling, otherwise re-detect the unlocking command and the frequency point binding command.
S130, when the EEPROM read-write module receives the first frequency point information, the stored frequency point information is erased, the first frequency point information is stored, and the first frequency point information is sent to a configuration module;
the EEPROM (i.e. lectrically Erasable Programmable read only memory, electrically erasable programmable read-only memory) read-write module performs a write operation on the received first frequency point information after receiving the first frequency point information, and the frequency point information stored before the write operation needs to be erased before the write operation, and then the write operation is performed after the erase operation.
The EEPROM read-write module can realize the power-on memory function of 485 remote measurement frequency point parameters, and firstly judges whether a read-write instruction sent by the FPGA is high or low. Referring to fig. 7, upon entering a read state, data in the addressed memory cell is serially output to the DO pin. Before outputting the data, one-bit virtual zero is input, and the stored 8-bit data is read and output. When the device is in the erasing and writing prohibition state after being powered on, the erasing and writing enabling instruction is required to be executed before the device is in the writing mode, address bits of erasing data are identified, then erasing and writing operation is performed, after the erasing and writing operation is finished, 11 clock cycles are separated, then writing operation is performed, after 8-bit data are written, the erasing and writing prohibition instruction is executed, and the erasing and writing prohibition state is performed, so that the state machine is finished.
That is, when the EEPROM read-write module writes the first frequency point information, an erasing enabling instruction is required; and after the erasing operation is finished, performing the writing operation after a preset number of clock cycles, and executing an erasing prohibition instruction after writing the first frequency point information.
S140, the configuration module determines a corresponding standard frequency shift keying modulation waveform according to the first frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
The configuration module may be a JDDS9957 configuration module, abbreviated as a DDS configuration module. The purpose of the EEPROM read-write module sending the first frequency point information to the configuration module is to enable the configuration module to generate a corresponding intermediate frequency signal based on the first frequency point information and the PCM signal input from the outside.
After the configuration module receives the first frequency point information, the configuration module analyzes the first frequency point information, generates a standard FSK modulation waveform according to the analyzed first frequency point information and the phase initial value, converts an externally input PCM signal into an FSK modulation waveform of a preset S-band frequency point based on the standard FSK modulation waveform, namely a required intermediate frequency signal, namely a radio frequency signal, and finally can output the radio frequency signal.
The JDDS9957 configuration module may specifically include: the AD9957_cfg_top sub-module, the AD9957_CFG sub-module, the AD9957_ dds _stream sub-module and the spi_controller_v5 sub-module are used for realizing the configuration of the AD 9957. Wherein, the AD9957_cfg_top sub-module can realize the assignment of all registers and output a parallel numerical value to the AD9957_CFG sub-module. The AD9957_cfg sub-module may implement converting all register values into a single register value for sequential output and outputting the result to the spi_controller_v5 sub-module. The spi_controller_v5 sub-module can convert each register value into corresponding serial data according to the communication protocol of the chip, and simultaneously generate a synchronous clock and an enabling signal. The AD9957_ dds _stream submodule generates 18-bit parallel input data of the chip JDS 9957, generates a 0 and 1 cycle skip signal when tx_stb is high, and outputs 18-bit parallel data corresponding to 0 and 1 respectively. The JDDS9957 chip has a plurality of registers therein, wherein the serial I/O port registers have addresses ranging from 0x00 to 0x19 for 26 total, the number of bytes allocated to different registers is not the same, and different byte capacities depend on specific functional requirements thereof, and in the embodiment of the present invention, the JDDS995 may use 6 register modules, namely, CRF1 with address 0x00 (i.e., control function register), CRF2 with address 0x01, CRF3 with address 0x02, AUX DAC with address 0x03 (i.e., auxiliary DAC control register), and Profile registers with addresses 0x0e and 0x0 f.
It can be understood that the steps S110 to S140 are performed when there is a frequency point information replacement requirement. The modules and chips involved in the embodiments of the present invention are modules and chips within a telemetry transmitter.
It can be understood that the embodiment of the invention aims at the problem that the frequency point of the traditional telemetry transmitter cannot be fixed to realize multiple alignment, analyzes 485 communication commands and acquires unlocking commands and frequency point binding commands from the commands by designing software codes, ensures that the frequency point is externally controllable, namely, the frequency point information is changed or adjusted, and simultaneously solves the problem that the traditional transmitter cannot adjust the frequency point in real time due to the fixed hardware design parameters in the external field flight test process.
When the frequency point information is changed when needed, the intermediate frequency signal corresponding to the changed frequency point information can be obtained through the steps. When the telemetry transmitter is powered on, the intermediate frequency signal corresponding to the stored frequency point information can be acquired through the following steps. Referring to fig. 4, the steps include:
s150, after the telemetering transmitter is electrified, the FPGA chip after the electrification sets a register to be in a known state through a reset module;
it will be appreciated that the operation after powering up the telemetry transmitter, voltage conversion may be provided to the various modules and chips, so that the FPGA chip is also powered up. After the FPGA chip is powered on, the state of the reset module and the state of the internal register are set to be a known state, and only the state set to be the known state can read the stored information to perform signal synchronization.
S160, after the register is set to be in a known state, the EEPROM read-write module reads 8-bit frequency point information from the register, marks the 8-bit frequency point information as second frequency point information, and sends the second frequency point information to the configuration module;
it can be understood that after the EEPROM read-write module reads the second frequency point information in the register, the second frequency point information is sent to the configuration module, so that the configuration information is converted into a corresponding intermediate frequency signal.
S170, the configuration module determines a corresponding standard frequency shift keying modulation waveform according to the second frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
It is understood that this step 170 is also to determine a standard FSK modulation waveform based on the frequency point information and the phase initial value, and then generate a frequency shift keying modulation waveform of a preset S-band frequency point, that is, a desired intermediate frequency signal, based on the standard FSK modulation waveform and the PCM signal acquired from the outside, as in the above step S140.
It can be understood that the embodiment of the invention aims at the problem that the default frequency point needs to be reconfigured after the traditional telemetry transmitter is powered on, designs and utilizes the memory function of the EEPROM reading module to read the stored frequency point information after the power on, and realizes FSK modulation according to the corresponding parameters through the configuration module working in the single-frequency modulation mode, thereby solving the problem that the frequency point needs to be reconfigured after the traditional telemetry transmitter is powered on, and reducing the power consumption while improving the working efficiency of the digital telemetry transmitter.
Therefore, the embodiment of the invention realizes the digital baseband board algorithm for realizing the frequency point information adjustment and reading the stored frequency point information after power-on based on the DDS configuration module and the FPGA chip, and solves the problem of transmitter frequency adaptation caused by the increasing crowding of telemetry frequency bands.
It will be appreciated that embodiments of the present invention relate to a plurality of modules: the device comprises a reset module, a 485 data receiving module, a 485 data analyzing module, an EEPROM read-write module, a DDS configuration module, a filtering module and the like. The reset module completes the reset of all registers in the FPGA chip, and sets all storage elements to be in a known state, so that the effect of synchronizing signals is achieved. The filtering module carries out filtering treatment on the input 485 serial data; the 485 data receiving module realizes a 485 data receiving function, outputs 485 data in parallel, enables 485 data and counts data; 485 data analysis module judges unlocking command and frequency point binding command in the data according to the protocol, completes command detection under the condition of not overtime, extracts frequency point data at corresponding position in the protocol, and outputs frequency point data and data enabling; the parameter conversion module realizes the conversion of 485 frequency point parameters; the EEPROM read-write module realizes the power-on memory function of 485 frequency point information; the DDS configuration module completes the configuration of the chip register according to the communication protocol, and realizes the output of 220MHz signals and intermediate frequency signals with appointed modulation degrees.
It can be understood that, based on the digital frequency synthesis technology, the embodiment of the invention generates the intermediate frequency signal with high resolution and adjustable frequency offset through the DDS configuration module, the FPGA chip controls the EEPROM reading module by using the serial communication mode to realize the local oscillation configuration, the stored frequency point information is electrically read, and the telemetering frequency point binding is realized according to the received command. The invention is based on a field programmable gate array and has the main functions of 485 data receiving and protocol analysis, frequency point output control, power-on frequency point information reading and intermediate frequency signal output.
It can be understood that the invention is based on digital frequency synthesis technology, uses a Field Programmable Gate Array (FPGA), obtains an unlocking command and a frequency point binding command from the FPGA by analyzing 485 communication commands, finishes frequency point storage and reading by utilizing the memory function of the EEPROM reading module, realizes data communication with the DDS configuration module and external PCM signals, and converts PCM code streams into radio frequency signals for output after FSK modulation.
In a second aspect, an embodiment of the present invention provides a radio frequency signal determination system for a telemetry transmitter, comprising:
the FPGA chip is used for sending the 485 communication command to the 485 data analysis module when receiving the 485 communication command;
the 485 data analysis module is used for searching corresponding 8-bit frequency point information in a register according to an effective frequency code in the frequency point binding command if an unlocking command and a frequency point binding command are extracted from the 485 communication command, recording the 8-bit frequency point information as first frequency point information, and sending the first frequency point information to the EEPROM read-write module;
the EEPROM read-write module is used for erasing the stored frequency point information when receiving the first frequency point information, storing the first frequency point information and sending the first frequency point information to the configuration module;
the configuration module is used for determining a corresponding standard frequency shift keying modulation waveform according to the first frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
In some embodiments, the FPGA chip is specifically configured to: when a 485 communication command is received, the 485 communication command is sent to a 485 data receiving module; correspondingly, the system further comprises: the 485 data receiving module is configured to remove header and footer information of the 485 communication command, perform zero deletion processing on data from which the header and footer information is removed, store the zero deletion processed data in a memory, perform CRC check on the zero deletion processed data, output the data stored in the memory and a corresponding address to the 485 data analyzing module after the CRC check is passed, and output corresponding data valid enabling information to the 485 data analyzing module.
In some embodiments, the performing zero-puncturing processing on the data from which the header and end information of the frame is removed in the 485 data receiving module includes: and detecting the code element 1 in the data from which the frame head and frame tail information is removed, and deleting the code element 0 after the preset number of continuous code elements 1 after detecting the preset number of continuous code elements 1.
In some embodiments, the EEPROM read-write module performs an erasing enabling instruction when writing the first frequency point information; and after the erasing operation is finished, performing the writing operation after a preset number of clock cycles, and executing an erasing prohibition instruction after writing the first frequency point information.
In some embodiments, the FPGA chip is further to: setting a register to a known state through a reset module after power-on; the EEPROM read-write module is also used for: reading 8-bit frequency point information from the register after the register is set to be in a known state, marking the 8-bit frequency point information as second frequency point information, and sending the second frequency point information to the configuration module; the configuration module is further configured to: determining a corresponding standard frequency shift keying modulation waveform according to the second frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
It may be appreciated that, the apparatus provided in this aspect corresponds to the method provided in the first aspect, and examples, embodiments, benefits and the like of the content may refer to corresponding parts in the first aspect, which are not described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. RON/RAN, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (8)
1. A method of determining a radio frequency signal for a telemetry transmitter, comprising:
when receiving a 485 communication command, the FPGA chip sends the 485 communication command to a 485 data analysis module;
if the 485 data analysis module extracts an unlocking command and a frequency point binding command from the 485 communication command, searching corresponding 8-bit frequency point information in a register according to an effective frequency code in the frequency point binding command, recording the 8-bit frequency point information as first frequency point information, and sending the first frequency point information to an EEPROM read-write module;
the EEPROM read-write module erases the stored frequency point information when receiving the first frequency point information, stores the first frequency point information and sends the first frequency point information to a configuration module;
the configuration module determines a corresponding standard frequency shift keying modulation waveform according to the first frequency point information and the phase initial value; according to the standard frequency shift keying modulation waveform, converting a pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point;
after the telemetering transmitter is electrified, the FPGA chip after the electrification sets a register to a known state through a reset module;
after the register is set to be in a known state, the EEPROM read-write module reads 8-bit frequency point information from the register, marks the 8-bit frequency point information as second frequency point information, and sends the second frequency point information to the configuration module;
the configuration module determines a corresponding standard frequency shift keying modulation waveform according to the second frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
2. The method of claim 1, wherein the FPGA chip, upon receiving a 485 communication command, sends the 485 communication command to a 485 data parsing module, comprising:
when receiving a 485 communication command, the FPGA chip sends the 485 communication command to a 485 data receiving module;
and the 485 data receiving module removes frame head and frame tail information of the 485 communication command, performs zero deletion processing on the data after the frame head and frame tail information is removed, stores the data after the zero deletion processing into a memory, performs CRC (cyclic redundancy check) on the data after the zero deletion processing, outputs the data stored in the memory and a corresponding address after the CRC passes, and outputs corresponding data valid enabling information.
3. The method of claim 2, wherein the performing zero-puncturing processing on the data from which the header and end information is removed comprises: and detecting the code element 1 in the data from which the frame head and frame tail information is removed, and deleting the code element 0 after the preset number of continuous code elements 1 after detecting the preset number of continuous code elements 1.
4. The method of claim 1, wherein the EEPROM read-write module performs an erasure enabling instruction when writing the first frequency point information; and after the erasing operation is finished, performing the writing operation after a preset number of clock cycles, and executing an erasing prohibition instruction after writing the first frequency point information.
5. A radio frequency signal determination system for a telemetry transmitter, comprising:
the FPGA chip is used for sending the 485 communication command to the 485 data analysis module when receiving the 485 communication command;
the 485 data analysis module is used for searching corresponding 8-bit frequency point information in a register according to an effective frequency code in the frequency point binding command if an unlocking command and a frequency point binding command are extracted from the 485 communication command, recording the 8-bit frequency point information as first frequency point information, and sending the first frequency point information to the EEPROM read-write module;
the EEPROM read-write module is used for erasing the stored frequency point information when receiving the first frequency point information, storing the first frequency point information and sending the first frequency point information to the configuration module;
the configuration module is used for determining a corresponding standard frequency shift keying modulation waveform according to the first frequency point information and the phase initial value; according to the standard frequency shift keying modulation waveform, converting a pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point;
the FPGA chip is further configured to: setting a register to a known state through a reset module after power-on;
the EEPROM read-write module is also used for: reading 8-bit frequency point information from the register after the register is set to be in a known state, marking the 8-bit frequency point information as second frequency point information, and sending the second frequency point information to the configuration module;
the configuration module is further configured to: determining a corresponding standard frequency shift keying modulation waveform according to the second frequency point information and the phase initial value; and converting the pulse code modulation signal into a frequency shift keying modulation waveform of a preset S-band frequency point according to the standard frequency shift keying modulation waveform, and outputting the frequency shift keying modulation waveform of the preset S-band frequency point.
6. The system of claim 5, wherein the FPGA chip is specifically configured to: when a 485 communication command is received, the 485 communication command is sent to a 485 data receiving module; correspondingly, the system further comprises:
the 485 data receiving module is configured to remove header and footer information of the 485 communication command, perform zero deletion processing on data from which the header and footer information is removed, store the zero deletion processed data in a memory, perform CRC check on the zero deletion processed data, output the data stored in the memory and a corresponding address to the 485 data analyzing module after the CRC check is passed, and output corresponding data valid enabling information to the 485 data analyzing module.
7. The system of claim 6, wherein the performing, in the 485 data receiving module, zero-puncturing the data from which the header and end information is removed, comprises: and detecting the code element 1 in the data from which the frame head and frame tail information is removed, and deleting the code element 0 after the preset number of continuous code elements 1 after detecting the preset number of continuous code elements 1.
8. The system of claim 7, wherein the EEPROM read-write module performs an erasure enabling instruction when writing the first frequency point information; and after the erasing operation is finished, performing the writing operation after a preset number of clock cycles, and executing an erasing prohibition instruction after writing the first frequency point information.
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