CN114442960A - Solid-state storage scheme free of fear abnormal power failure and capable of prolonging service life - Google Patents
Solid-state storage scheme free of fear abnormal power failure and capable of prolonging service life Download PDFInfo
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- CN114442960A CN114442960A CN202210111855.6A CN202210111855A CN114442960A CN 114442960 A CN114442960 A CN 114442960A CN 202210111855 A CN202210111855 A CN 202210111855A CN 114442960 A CN114442960 A CN 114442960A
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- 230000002159 abnormal effect Effects 0.000 title claims abstract description 26
- 239000007787 solid Substances 0.000 claims abstract description 36
- 230000005540 biological transmission Effects 0.000 claims abstract description 20
- 238000013507 mapping Methods 0.000 claims description 20
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 claims description 7
- 238000012986 modification Methods 0.000 claims description 4
- 230000004048 modification Effects 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 3
- 230000002035 prolonged effect Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000004146 energy storage Methods 0.000 description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0643—Management of files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a solid state storage scheme without fear of abnormal power failure and capable of prolonging service life. The invention can realize that no data is lost in abnormal power failure, save precious data for users, continuously receive data which is not transmitted at the 'breakpoint' position of the abnormal power failure, save the time of repeated transmission, greatly improve the stability and the reliability of the solid state disk by adopting the method of storing the file system in the MRAM, can be widely applied to medical electronics, data centers, military electronics and the like, can greatly improve the service life of the solid state disk, and can greatly improve the random writing performance of the solid state disk.
Description
Technical Field
The invention relates to the technical field of solid-state storage, in particular to a solid-state storage scheme which is free of abnormal power failure and capable of prolonging service life.
Background
The solid state disk is a hard disk made of a solid state electronic storage chip array.
The solid state disk generally comprises a controller, a cache chip (DDR) and a memory chip (NAND), wherein the controller acquires external data through an SATA or PCIE interface and temporarily stores the external data in the DDR chip, the external data is stored in the NAND chip after a certain amount of data is acquired, and meanwhile, the controller reads an original file system mapping table from the NAND chip and temporarily stores the mapping table in the DDR chip; and when all external data are stored in the NAND chip, the controller updates the file system mapping table and stores the file system mapping table in the NAND chip.
If the external data is in the transmission process, suddenly and abnormally powering down; data temporarily stored in the DDR chip will be lost entirely, and data already stored in the NAND chip will also be discarded by default as defective data.
If the controller is updating the mapping table of the file system, suddenly and abnormally powering down; the file system mapping tables temporarily stored in the DDR chip are all lost, which results in that all the received external data are discarded, and even the whole file system runs short, and the hard disk cannot be used.
Because the minimum write unit of the NAND is a page (page) and the minimum erase unit of the NAND is a block (block), when the controller acquires external small-capacity data and directly stores the data into the NAND, the erase frequency of the NAND is increased, and the service life of the solid state disk is shortened.
The file system mapping table belongs to small-capacity data, frequent updating and storing in the NAND can increase the erasing times of the NAND and reduce the service life of the solid state disk.
When the controller needs to modify the random data in the NAND, the controller reads the stored data from the NAND into the DDR, completes the modification and stores the data back into the NAND. Because NAND has the disadvantage of erasing first and then writing, and the number of times of erasing is limited; if the random write operation is frequently performed, the service life of the solid state disk is greatly reduced, and the performance of the random write operation is very low.
There are two treatment options currently on the market.
In the first scheme, an energy storage capacitor is added in a solid state disk, so that a controller can rapidly process data temporarily stored in a DDR chip, but the first scheme has many defects: 1, the volume and the quantity of the energy storage capacitors are large, so that the solid state disk cannot be miniaturized or the storage capacity of the solid state disk is reduced in the same physical space; 2, the energy storage capacitor has explosion risk, so that the solid state disk cannot be applied to the fields of medical treatment, military industry, automobiles and the like; and 3, the low-temperature characteristic of the energy storage capacitor is poor, so that the solid state disk cannot play a role in protection in a low-temperature environment.
The scheme II is a scheme without a cache chip, the solid state disk is composed of a controller and a storage chip, the controller directly stores external data into the NAND chip, and meanwhile, the file system mapping table is updated at high frequency and is rapidly stored into the NAND chip, and the scheme also has a plurality of defects: 1, because the storage rate of the NAND chip is low, if external small-capacity data is directly stored in the NAND chip, the storage rate of the whole solid state disk is very low; 2, the service life of the whole solid state disk is greatly shortened due to the fact that the NAND chip is limited in service life and the file system mapping table is updated at high frequency.
Disclosure of Invention
Based on the technical problems in the background art, the invention provides a solid-state storage scheme which is free of abnormal power failure and prolongs the service life.
The invention provides a solid-state storage scheme without fear of abnormal power failure and capable of prolonging service life, which comprises a solid-state hard disk and is characterized in that the solid-state hard disk comprises four MRAM chips, an NAND chip and a controller, the four MRAM chips form a data buffer, and the solid-state storage scheme is as follows:
s1, when the controller obtains external small-capacity data, the data are temporarily stored in the MRAM chip, and when a certain amount of data is obtained, the data are merged, packed, transferred and stored into the NAND chip;
s2, when the controller needs to modify the random data in the NAND chip, it can directly complete the modification in the MRAM chip and temporarily store in the MRAM chip; when the temporarily stored random data reaches a certain amount, merging, packaging and storing the random data into the NAND chip;
s3, in the data transmission process, if abnormal power failure occurs, the part of data which has been transmitted cannot be lost;
s4 when the power supply is recovered to normal, the data which is not transmitted before the power failure can be continuously received and stored at the breakpoint, and the data repeat transmission time is saved.
Preferably, the MRAM chip is an MRAM chip of EVERSPIN company, the model is EMD4E001G08G1-150CAS2, and the transmission bandwidth is 1333 MT/s.
Preferably, the data buffer has the following characteristics: the capacity is 4Gb, the bandwidth is 32 bits, the transmission rate is 1333MT/s, the interface is compatible with DDR4, and the data is not lost when power is lost.
Preferably, the file system mapping table of the external small-capacity data is directly stored in the data buffer, and even if the solid state disk is updating the file system mapping table, the abnormal power failure is found, and the file system mapping table cannot be lost based on the nonvolatile characteristic of the MRAM data.
Preferably, the MRAM adopted by the solid state disk is compatible with a DDR4 interface.
According to the solid-state storage scheme which is free of fear of abnormal power failure and prolongs the service life, the abnormal power failure can be free of any data loss, precious data can be stored for a user, data which are not transmitted can be continuously received at a breakpoint of the abnormal power failure, repeated transmission time is saved, the method of storing the file system in the MRAM is adopted, the stability and the reliability of the solid-state hard disk can be greatly improved, the solid-state hard disk can be widely applied to medical electronics, data centers, military electronics and the like, the service life of the solid-state hard disk can be greatly prolonged, and the random writing performance of the solid-state hard disk can be greatly improved.
Drawings
Fig. 1 is a schematic diagram of a solid-state storage scheme of the present invention, which is free of abnormal power failure and has an increased service life.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Referring to fig. 1, a solid state storage scheme without fear of abnormal power failure and with increased service life includes a solid state disk, and is characterized in that the solid state disk includes four MRAM chips, a NAND chip, and a controller, the four MRAM chips constitute a data buffer, and the solid state storage scheme is as follows:
s1, when the controller acquires external small-capacity data, the data are temporarily stored in the MRAM chip, and when a certain amount of data is obtained, the data are merged, packaged, transferred and stored into the NAND chip, so that the erasing times of the NAND chip can be greatly reduced, and the service life of the solid state disk is prolonged;
s2, when the controller needs to modify the random data in the NAND chip, it can directly complete the modification in the MRAM chip and temporarily store in the MRAM chip; when the temporarily stored random data reaches a certain amount, the random data is combined, packaged and stored in the NAND chip, so that the erasing frequency of the NAND chip can be greatly reduced, and the service life of the solid state disk is prolonged; the random writing performance of the hard disk can be greatly improved;
s3, in the data transmission process, if abnormal power failure occurs, the part of data which has been transmitted cannot be lost;
s4 when the power supply is recovered to normal, the data which is not transmitted before the power failure can be continuously received and stored at the breakpoint, and the data repeat transmission time is saved.
In the invention, the MRAM chip is an MRAM chip of EVERSPIN company, the model is EMD4E001G08G1-150CAS2, and the transmission bandwidth is 1333 MT/s.
In the invention, the data buffer has the following characteristics: the capacity is 4Gb, the bandwidth is 32 bits, the transmission rate is 1333MT/s, the interface is compatible with DDR4, and power-down data are not lost.
In the invention, the file system mapping table of the external small-capacity data is directly stored in the data buffer, even if the solid state disk updates the file system mapping table, abnormal power failure is found, the file system mapping table cannot be lost based on the nonvolatile characteristic of MRAM data, the file system mapping table is directly stored in the MRAM data buffer, high-frequency storage in NAND is not needed, the erasing times of the NAND can be reduced, and the service life of the solid state disk is prolonged.
In the invention, the MRAM adopted by the solid state disk is compatible with a DDR4 interface.
The invention comprises the following steps: the data nonvolatile memory MRAM is adopted as a buffer of the solid state disk, so that abnormal power failure is not feared; in the transmission process, stored data can not be lost, the file system mapping table is directly stored in the MRAM, the system running abnormal rate of the solid state disk can be reduced, the stability and the service life of the hard disk are improved, the MRAM is used as a temporary storage for small-capacity data and random data, the erasing frequency of NAND can be greatly reduced, the service life of the solid state disk is prolonged, the adopted MRAM is compatible with a DDR4 interface, the design of a controller hardware circuit is not influenced, the adopted MRAM chip has the characteristics that the transmission bandwidth can reach 1333MT/s, the transmission rate of the solid state disk is not influenced and the like, the MRAM is used as a nonvolatile buffer for the random data, and the random writing performance of the solid state disk can be greatly improved.
When the controller acquires external small-capacity data, the data are temporarily stored in the MRAM chip, and when a certain amount of data is obtained, the data are combined, packaged and transferred into the NAND chip; when the controller needs to modify the random data in the NAND chip, the controller can directly modify the random data in the MRAM chip and temporarily store the random data in the MRAM chip; when the temporarily stored random data reaches a certain amount, merging, packaging and storing the random data into the NAND chip; in the data transmission process, if abnormal power failure occurs, the part of data which is transmitted cannot be lost; after the power supply is recovered to normal, the data which is not transmitted before the power failure can be continuously received and stored at the breakpoint, and the repeated data transmission time is saved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (5)
1. The solid-state storage scheme comprises a solid-state hard disk, and is characterized in that the solid-state hard disk comprises four MRAM chips, an NAND chip and a controller, the four MRAM chips form a data buffer, and the solid-state storage scheme is as follows:
s1, when the controller obtains external small-capacity data, the data are temporarily stored in the MRAM chip, and when a certain amount of data is obtained, the data are merged, packed, transferred and stored into the NAND chip;
s2, when the controller needs to modify the random data in the NAND chip, it can directly complete the modification in the MRAM chip and temporarily store in the MRAM chip; when the temporarily stored random data reaches a certain amount, merging, packaging and storing the random data into the NAND chip;
s3, in the data transmission process, if abnormal power failure occurs, the part of data which has been transmitted cannot be lost;
s4 when the power supply is recovered to normal, the data which is not transmitted before the power failure can be continuously received and stored at the breakpoint, and the data repeat transmission time is saved.
2. The solid-state storage scheme with no fear of abnormal power failure and increased service life of claim 1, wherein the MRAM chip is an MRAM chip of EVERSPIN corporation, model number EMD4E001G08G1-150CAS2, and transmission bandwidth is 1333 MT/s.
3. The solid-state storage scheme with no fear of abnormal power failure and increased service life of claim 1, wherein the data buffer has the following characteristics: the capacity is 4Gb, the bandwidth is 32 bits, the transmission rate is 1333MT/s, the interface is compatible with DDR4, and the data is not lost when power is lost.
4. The solid-state storage scheme with no fear of abnormal power failure and increased service life of claim 1, wherein the file system mapping table of the external small-capacity data is directly stored in the data buffer, and even if the solid-state hard disk is updating the file system mapping table, the file system mapping table is not lost based on the nonvolatile property of the MRAM data when abnormal power failure is found.
5. The solid state storage scheme with no fear of abnormal power failure and increased service life of claim 1, wherein the solid state disk adopts an MRAM compatible with DDR4 interface.
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| CN202210111855.6A CN114442960A (en) | 2022-01-27 | 2022-01-27 | Solid-state storage scheme free of fear abnormal power failure and capable of prolonging service life |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115878033A (en) * | 2022-11-30 | 2023-03-31 | 合肥腾芯微电子有限公司 | Solid state disk and mapping table management method thereof |
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| CN105632534A (en) * | 2015-03-24 | 2016-06-01 | 上海磁宇信息科技有限公司 | Solid-state drive with mixed use of DRAM (Dynamic Random Access Memory) and MRAM (Magnetic Random Access Memory) |
| CN105630692A (en) * | 2015-05-22 | 2016-06-01 | 上海磁宇信息科技有限公司 | File storage system storing file directory by using MRAM |
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- 2022-01-27 CN CN202210111855.6A patent/CN114442960A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104503710A (en) * | 2015-01-23 | 2015-04-08 | 福州瑞芯微电子有限公司 | Method and device for increasing writing speed of nand flash |
| CN105632534A (en) * | 2015-03-24 | 2016-06-01 | 上海磁宇信息科技有限公司 | Solid-state drive with mixed use of DRAM (Dynamic Random Access Memory) and MRAM (Magnetic Random Access Memory) |
| CN105589912A (en) * | 2015-03-27 | 2016-05-18 | 上海磁宇信息科技有限公司 | Method and storage structure for processing frequently written document with MRAM (Magnetic Random Access Memory) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115878033A (en) * | 2022-11-30 | 2023-03-31 | 合肥腾芯微电子有限公司 | Solid state disk and mapping table management method thereof |
| CN115878033B (en) * | 2022-11-30 | 2023-09-15 | 合肥腾芯微电子有限公司 | Solid state disk and mapping table management method thereof |
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