CN114429746B - Display device and electronic apparatus - Google Patents
Display device and electronic apparatus Download PDFInfo
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- CN114429746B CN114429746B CN202210054107.9A CN202210054107A CN114429746B CN 114429746 B CN114429746 B CN 114429746B CN 202210054107 A CN202210054107 A CN 202210054107A CN 114429746 B CN114429746 B CN 114429746B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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Abstract
The application discloses display device and electronic equipment, this display device includes time sequence controller, display panel and first interface extension circuit, through an input/output interface connection first interface extension circuit at time sequence controller, can divide into two-way output to display panel through the first output of first interface extension circuit, the second output respectively, can provide two-way logic control signal for display panel, that is to say, an input/output interface of time sequence controller can divide into two-way different logic control signal with an initial logic control signal through first interface extension circuit to provide to display panel, time sequence controller can satisfy display panel's different display requirement with less input/output interface.
Description
Technical Field
The application relates to the technical field of display, in particular to a display device and electronic equipment.
Background
In the related display technology, the input/output interface of the timing controller directly outputs the corresponding logic control signal to the display panel so as to meet the normal display requirement of the display panel. With the evolution of various display technology indicators, the variety and/or number of logic control signals required increases. However, only one input/output interface of the timing controller may provide one logic control signal, that is, each time one logic control signal is added, one input/output interface is correspondingly required to be added to the timing controller.
However, since the number of input/output interfaces that the timing controller itself can carry is limited, it is necessary to provide a display device having an interface expansion function.
It should be noted that the above description of the background art is only for the purpose of facilitating a clear and complete understanding of the technical solutions of the present application. Therefore, the technical solutions referred to above are not considered to be known to those skilled in the art, simply because they appear in the background of the present application.
Disclosure of Invention
The application provides a display device and electronic equipment to alleviate the less technical problem of its input/output interface quantity.
In a first aspect, the present application provides a display device, including a timing controller, a display panel, and a first interface expansion circuit, where a first input/output interface of the timing controller is used to transmit an initial logic control signal; the first trigger end of the first interface expansion circuit is electrically connected with the first input/output interface of the time schedule controller, the first output end of the first interface expansion circuit is electrically connected with the display panel, and the second output end of the first interface expansion circuit is electrically connected with the display panel.
In some embodiments, the first interface expansion circuit includes a first trigger circuit, a first level conversion circuit, and a first potential determining circuit, a trigger terminal of the first trigger circuit is a first trigger terminal of the first interface expansion circuit, and an output terminal of the first trigger circuit is a first output terminal of the first interface expansion circuit; the input end of the first level conversion circuit is electrically connected with the output end of the first trigger circuit; the control end of the first potential determining circuit is electrically connected with the output end of the first level converting circuit, and the output end of the first potential determining circuit is electrically connected with the output end of the first level converting circuit and serves as the second output end of the first interface expanding circuit.
In some embodiments, the first output terminal of the first interface expansion circuit is configured to output a first logic control signal, where the first logic control signal has a first potential and a second potential, and the first potential is higher than the second potential; the second output end of the first interface expansion circuit is used for outputting a second logic control signal, the second logic control signal has a third potential and a fourth potential, and the third potential is higher than the fourth potential; and the third potential is different from the first potential.
In some of these embodiments, the phase of the first logic control signal is the same as the phase of the second logic control signal.
In some embodiments, the display device further includes a second interface extension circuit, a second trigger end of the second interface extension circuit is electrically connected to the first input/output interface of the timing controller, a third output end of the second interface extension circuit is electrically connected to the display panel, a fourth output end of the second interface extension circuit is electrically connected to the display panel, and a fifth output end of the second interface extension circuit is electrically connected to the display panel.
In some embodiments, the second interface expansion circuit includes a second trigger circuit, a phase adjustment circuit, a second level conversion circuit, and a second potential determination circuit, a trigger terminal of the second trigger circuit is used as a second trigger terminal of the second interface expansion circuit, and an output terminal of the second trigger circuit is used as a third output terminal of the second interface expansion circuit; the trigger end of the phase adjusting circuit is electrically connected with the trigger end of the second trigger circuit, the input end of the phase adjusting circuit is electrically connected with the output end of the second trigger circuit, and the output end of the phase adjusting circuit is used as a fourth output end of the second interface expanding circuit; the input end of the second level conversion circuit is electrically connected with the output end of the phase adjustment circuit, and the output end of the second level conversion circuit is used as a fifth output end of the second interface expansion circuit; the input end of the second potential determining circuit is electrically connected with the output end of the second level converting circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
In some embodiments, the third output terminal of the second interface expansion circuit is configured to output a third logic control signal, the fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and the fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is different from that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is the same as that of the fourth logic control signal; the phase of the fourth logic control signal is the same as the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is different from the pulse amplitude of the fifth logic control signal.
In some embodiments, the second interface expansion circuit includes a second trigger circuit, a phase adjustment circuit, a second level conversion circuit, and a second potential determination circuit, a trigger terminal of the second trigger circuit is used as a second trigger terminal of the second interface expansion circuit, and an output terminal of the second trigger circuit is used as a third output terminal of the second interface expansion circuit; the input end of the second level conversion circuit is electrically connected with the output end of the second trigger circuit, and the output end of the second level conversion circuit is used as a fourth output end of the second interface expansion circuit; the trigger end of the phase adjusting circuit is electrically connected with the trigger end of the second trigger circuit, the input end of the phase adjusting circuit is electrically connected with the output end of the second level converting circuit, and the output end of the phase adjusting circuit is used as a fifth output end of the second interface expanding circuit; the input end of the second potential determining circuit is electrically connected with the output end of the phase adjusting circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
In some embodiments, the third output terminal of the second interface expansion circuit is configured to output a third logic control signal, the fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and the fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is the same as that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is different from that of the fourth logic control signal; the phase of the fourth logic control signal is different from the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is the same as the pulse amplitude of the fifth logic control signal.
In a second aspect, the present application provides an electronic device, which includes the display device in at least one embodiment.
According to the display device and the electronic equipment, the first interface expansion circuit is connected with the input/output interface of the time sequence controller, an initial logic control signal can be respectively output to the display panel in two ways through the first output end and the second output end of the first interface expansion circuit, and two ways of logic control signals can be provided for the display panel, namely, one input/output interface of the time sequence controller can be used for dividing the initial logic control signal into two ways of different logic control signals through the first interface expansion circuit and is provided for the display panel, and the time sequence controller can meet different display requirements of the display panel through a small number of input/output interfaces.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a first structure of a display device according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a second structure of the display device according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In view of the technical problem that the number of input/output interfaces of the display device is small, the present embodiment provides a display device, as shown in fig. 1 and 2, which includes a timing controller 100, a display panel 200, and a first interface expansion circuit 300, where the first input/output interface of the timing controller 100 is used for transmitting an initial logic control signal; the first trigger end of the first interface expansion circuit 300 is electrically connected to the first input/output interface of the timing controller 100, the first output end A1 of the first interface expansion circuit 300 is electrically connected to the display panel 200, and the second output end A2 of the first interface expansion circuit 300 is electrically connected to the display panel 200.
It can be understood that, in the display device provided in this embodiment, by connecting an input/output interface of the timing controller 100 with a first interface expansion circuit 300, an initial logic control signal can be respectively output to the display panel 200 in two ways through the first output end A1 and the second output end A2 of the first interface expansion circuit 300, and two logic control signals can be provided to the display panel 200, that is, one input/output interface of the timing controller 100 can be respectively output in two ways through the first interface expansion circuit 300, and can be provided to the display panel 200.
It should be noted that, the timing controller 100 may further include a second input/output interface, a third input/output interface, a fourth input/output interface, and so on, and the number of the input/output interfaces is not specifically limited herein.
The initial logic control signal may be a clock signal, which may be a square wave signal or a pulse signal.
In one embodiment, as shown in fig. 1 or fig. 2, the first interface extension circuit 300 includes a first trigger circuit 310, a first level conversion circuit 320, and a first potential determining circuit 330, where a trigger terminal of the first trigger circuit 310 is a first trigger terminal of the first interface extension circuit 300, and an output terminal of the first trigger circuit 310 is a first output terminal A1 of the first interface extension circuit 300; the input end of the first level shifter 320 is electrically connected to the output end of the first trigger circuit 310; the control end of the first potential determining circuit 330 is electrically connected to the output end of the first level shifter circuit 320, and the output end of the first potential determining circuit 330 is electrically connected to the output end of the first level shifter circuit 320 and serves as the second output end A2 of the first interface expanding circuit 300.
The first trigger circuit 310 may output the potential outputted through the first potential determining circuit 330 according to the rising edge of the initial logic control signal. The first level conversion circuit 320 may convert the electric potential output by the first trigger circuit 310, or convert the electric potential into an electric potential with a higher amplitude, or convert the electric potential into an electric potential with a lower amplitude, and may be flexibly set as required.
In one embodiment, the first trigger circuit 310 may include a first trigger D1, wherein a trigger end of the first trigger D1 is electrically connected to the first input/output interface of the timing controller 100, an input end of the first trigger D1 is electrically connected to the output end of the first potential determining circuit 330, and an output end of the first trigger D1 is electrically connected to the input end of the first level converting circuit 320.
The first flip-flop D1 may be a D flip-flop.
In one embodiment, the first trigger circuit 310 may further include a first resistor R1, one end of the first resistor R1 is electrically connected to the output end of the first trigger D1, and the other end of the first resistor R1 is grounded. It should be noted that the first resistor R1 may be used to initialize the output terminal of the first trigger circuit 310 to a low potential.
In one embodiment, the first potential determining circuit 330 may include a first transistor M1 and a second transistor M2, one of the source/drain electrodes of the first transistor M1 is connected to the first voltage signal VDD1, the other of the source/drain electrodes of the first transistor M1 is electrically connected to one of the source/drain electrodes of the second transistor M2, the other of the source/drain electrodes of the second transistor M2 is grounded, and the gate electrode of the first transistor M1 is electrically connected to the gate electrode of the second transistor M2 and the output terminal of the first level converting circuit 320.
The first transistor M1 and the second transistor M2 may be field effect transistors, specifically, the first transistor M1 may also be a P-channel field effect transistor, and the second transistor M2 may also be an N-channel field effect transistor.
In one embodiment, the potential of the first voltage signal VDD1 may be the same as the pulse amplitude of the initial logic control signal, so that the first logic control signal and the initial logic control signal may be guaranteed to be the same.
In one embodiment, the first output terminal A1 of the first interface expansion circuit 300 is configured to output a first logic control signal, where the first logic control signal has a first potential and a second potential, and the first potential is higher than the second potential; the second output terminal A2 of the first interface expansion circuit 300 is configured to output a second logic control signal, where the second logic control signal has a third potential and a fourth potential, and the third potential is higher than the fourth potential; and the third potential is different from the first potential.
It can be appreciated that in this embodiment, the first potential and the third potential may be pulse amplitudes of corresponding logic control signals, respectively. The third potential may be higher than the first potential, or the first potential may be higher than the third potential, so that flexible setting may be performed as needed.
In one embodiment, the phase of the first logic control signal is the same as the phase of the second logic control signal.
In one embodiment, as shown in fig. 1 or fig. 2, the display device further includes a second interface extension circuit 400, a second trigger end of the second interface extension circuit 400 is electrically connected to the first input/output interface of the timing controller 100, a third output end B1 of the second interface extension circuit 400 is electrically connected to the display panel 200, a fourth output end B2 of the second interface extension circuit 400 is electrically connected to the display panel 200, and a fifth output end B3 of the second interface extension circuit 400 is electrically connected to the display panel 200.
It will be appreciated that in this embodiment, one input/output interface of the timing controller 100 may be extended to three, and the number of interfaces of the timing controller 100 may be further increased.
In one embodiment, as shown in fig. 1, the second interface extension circuit 400 includes a second trigger circuit 410, a phase adjustment circuit 420, a second level conversion circuit 430, and a second potential determination circuit 440, where a trigger terminal of the second trigger circuit 410 is a second trigger terminal of the second interface extension circuit 400, and an output terminal of the second trigger circuit 410 is a third output terminal B1 of the second interface extension circuit 400; the trigger end of the phase adjustment circuit 420 is electrically connected with the trigger end of the second trigger circuit 410, the input end of the phase adjustment circuit 420 is electrically connected with the output end of the second trigger circuit 410, and the output end of the phase adjustment circuit 420 is used as a fourth output end B2 of the second interface expansion circuit 400; the input end of the second level shifter circuit 430 is electrically connected to the output end of the phase adjustment circuit 420, and the output end of the second level shifter circuit 430 is used as the fifth output end B3 of the second interface expansion circuit 400; the input end of the second potential determining circuit 440 is electrically connected to the output end of the second level converting circuit 430, and the output end of the second potential determining circuit 440 is electrically connected to the input end of the second trigger circuit 410.
In one embodiment, the second trigger circuit 410 may include a second trigger D2, wherein a trigger end of the second trigger D2 is electrically connected to the first input/output interface of the timing controller 100, an input end of the second trigger D2 is electrically connected to an output end of the second potential determining circuit 440, and an output end of the second trigger D2 is electrically connected to an input end of the second level converting circuit 430.
The second flip-flop D2 may be a D flip-flop.
In one embodiment, the second trigger circuit 410 may further include a second resistor R2, wherein one end of the second resistor R2 is electrically connected to the output end of the second trigger D2, and the other end of the second resistor R2 is grounded. It should be noted that the second resistor R2 may be used to initialize the output terminal of the second trigger circuit 410 to a low voltage.
In one embodiment, the phase adjustment circuit 420 may include a third flip-flop D3, wherein a trigger end of the third flip-flop D3 is electrically connected to the first input/output interface of the timing controller 100, an input end of the third flip-flop D3 is electrically connected to an output end of the second flip-flop D2, and an output end of the third flip-flop D3 is electrically connected to an input end of the second level conversion circuit 430.
It will be appreciated that the phase adjustment circuit 420 may delay the signal output by the second flip-flop D2 correspondingly to achieve the phase adjustment thereof.
The third flip-flop D3 may be a D flip-flop.
In one embodiment, the phase adjustment circuit 420 further includes a third resistor R3, one end of the third resistor R3 is electrically connected to the output end of the third flip-flop D3, and the other end of the third resistor R3 is grounded. The third resistor R3 may be used to initialize the output terminal of the third trigger circuit to a low potential.
In one embodiment, the second potential determining circuit 440 may include a third transistor M3 and a fourth transistor M4, one of the source/drain electrodes of the third transistor M3 is connected to the second voltage signal VDD2, the other of the source/drain electrodes of the third transistor M3 is electrically connected to one of the source/drain electrodes of the fourth transistor M4, the other of the source/drain electrodes of the fourth transistor M4 is grounded, and the gate electrode of the third transistor M3 is electrically connected to the gate electrode of the fourth transistor M4 and the output terminal of the second level converting circuit 430.
The third transistor M3 and the fourth transistor M4 may be field effect transistors, specifically, the third transistor M3 may also be a P-channel field effect transistor, and the fourth transistor M4 may also be an N-channel field effect transistor.
The first voltage signal VDD1 and the second voltage signal VDD2 are constant voltage signals, and the potential of the first voltage signal VDD1 is different from the potential of the second voltage signal VDD 2.
In one embodiment, the third output terminal B1 of the second interface expansion circuit 400 is configured to output a third logic control signal, the fourth output terminal B2 of the second interface expansion circuit 400 is configured to output a fourth logic control signal, and the fifth output terminal B3 of the second interface expansion circuit 400 is configured to output a fifth logic control signal; the phase of the third logic control signal is different from that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is the same as that of the fourth logic control signal; the phase of the fourth logic control signal is the same as the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is different from the pulse amplitude of the fifth logic control signal.
It can be appreciated that the third logic control signal, the fourth logic control signal and the fifth logic control signal provided in the present embodiment are different from each other, so as to meet more display requirements of the display panel 200.
In one embodiment, as shown in fig. 2, the second interface extension circuit 400 includes a second trigger circuit 410, a phase adjustment circuit 420, a second level conversion circuit 430, and a second potential determination circuit 440, where a trigger terminal of the second trigger circuit 410 is used as a second trigger terminal of the second interface extension circuit 400, and an output terminal of the second trigger circuit 410 is used as a third output terminal B1 of the second interface extension circuit 400; the input end of the second level shifter circuit 430 is electrically connected to the output end of the second trigger circuit 410, and the output end of the second level shifter circuit 430 is used as the fourth output end B2 of the second interface expansion circuit 400; the trigger end of the phase adjustment circuit 420 is electrically connected with the trigger end of the second trigger circuit 410, the input end of the phase adjustment circuit 420 is electrically connected with the output end of the second level conversion circuit 430, and the output end of the phase adjustment circuit 420 is used as a fifth output end B3 of the second interface expansion circuit 400; the input end of the second potential determining circuit 440 is electrically connected to the output end of the phase adjusting circuit 420, and the output end of the second potential determining circuit 440 is electrically connected to the input end of the second triggering circuit 410.
It should be noted that, compared to fig. 1, the position of the phase adjustment circuit 420 is exchanged with that of the second level conversion circuit 430 in the present embodiment, and accordingly, some connection relationships are changed, which will not be described in detail herein, and reference may be made to fig. 2 or the connection relationships described above.
In one embodiment, the third output terminal B1 of the second interface expansion circuit 400 is configured to output a third logic control signal, the fourth output terminal B2 of the second interface expansion circuit 400 is configured to output a fourth logic control signal, and the fifth output terminal B3 of the second interface expansion circuit 400 is configured to output a fifth logic control signal; the phase of the third logic control signal is the same as that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is different from that of the fourth logic control signal; the phase of the fourth logic control signal is different from the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is the same as the pulse amplitude of the fifth logic control signal.
It should be noted that, in the above embodiment, the timing controller 100 may be a timing control chip, and each input/output interface may be a pin or a pin of the timing control chip. It is understood that the integration level of the timing control chip is higher, and the area or volume of the display device can be further reduced.
In one embodiment, the present embodiment provides an electronic device, which includes the display device in at least one embodiment.
It can be understood that, in the electronic device provided in this embodiment, by connecting an input/output interface of the timing controller 100 to the first interface extension circuit 300, an initial logic control signal can be respectively output to the display panel 200 in two ways through the first output end A1 and the second output end A2 of the first interface extension circuit 300, and two logic control signals can be provided to the display panel 200, that is, one input/output interface of the timing controller 100 can be respectively output to the display panel 200 in two ways through the first interface extension circuit 300, and the timing controller 100 can meet different display requirements of the display panel 200 with a smaller number of input/output interfaces.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display device and the electronic device provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present application, where the description of the above embodiments is only for helping to understand the technical solution and core ideas of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (8)
1. A display device, comprising:
the first input/output interface of the time schedule controller is used for transmitting an initial logic control signal;
a display panel; and
the first trigger end of the first interface expansion circuit is electrically connected with a first input/output interface of the time schedule controller, the first output end of the first interface expansion circuit is electrically connected with the display panel, and the second output end of the first interface expansion circuit is electrically connected with the display panel;
the first output end of the first interface expansion circuit is used for outputting a first logic control signal, the first logic control signal has a first potential and a second potential, and the first potential is higher than the second potential; the second output end of the first interface expansion circuit is used for outputting a second logic control signal, the second logic control signal is provided with a third potential and a fourth potential, the third potential is higher than the fourth potential, and the third potential is higher than the first potential and is used for improving the driving capability of the second logic control signal;
wherein the first interface expansion circuit includes:
the first trigger circuit, the trigger end of the said first trigger circuit is regarded as the first trigger end of the said first interface expansion circuit, the output end of the said first trigger circuit is regarded as the first output end of the said first interface expansion circuit;
the input end of the first level conversion circuit is electrically connected with the output end of the first trigger circuit; and
the control end of the first potential determining circuit is electrically connected with the output end of the first level converting circuit and serves as the second output end of the first interface expanding circuit, and the output end of the first potential determining circuit is electrically connected with the input end of the first trigger circuit;
the first level conversion circuit is used for providing a second logic control signal with higher driving capability than the first logic control signal and improving the reliability of the first interface expansion circuit.
2. The display device according to claim 1, wherein a phase of the first logic control signal is the same as a phase of the second logic control signal.
3. The display device of claim 1, further comprising a second interface extension circuit, wherein a second trigger end of the second interface extension circuit is electrically connected to the first input/output interface of the timing controller, a third output end of the second interface extension circuit is electrically connected to the display panel, a fourth output end of the second interface extension circuit is electrically connected to the display panel, and a fifth output end of the second interface extension circuit is electrically connected to the display panel.
4. A display device according to claim 3, wherein the second interface expansion circuit comprises:
the trigger end of the second trigger circuit is used as a second trigger end of the second interface expansion circuit, and the output end of the second trigger circuit is used as a third output end of the second interface expansion circuit;
the trigger end of the phase adjusting circuit is electrically connected with the trigger end of the second trigger circuit, the input end of the phase adjusting circuit is electrically connected with the output end of the second trigger circuit, and the output end of the phase adjusting circuit is used as the fourth output end of the second interface expanding circuit;
the input end of the second level conversion circuit is electrically connected with the output end of the phase adjustment circuit, and the output end of the second level conversion circuit is used as a fifth output end of the second interface expansion circuit; and
the input end of the second potential determining circuit is electrically connected with the output end of the second level converting circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second triggering circuit.
5. The display device according to claim 4, wherein a third output terminal of the second interface expansion circuit is configured to output a third logic control signal, a fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and a fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is different from the phase of the fourth logic control signal, and the pulse amplitude of the third logic control signal is the same as the pulse amplitude of the fourth logic control signal; the phase of the fourth logic control signal is the same as the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is different from the pulse amplitude of the fifth logic control signal.
6. A display device according to claim 3, wherein the second interface expansion circuit comprises:
the trigger end of the second trigger circuit is used as a second trigger end of the second interface expansion circuit, and the output end of the second trigger circuit is used as a third output end of the second interface expansion circuit;
the input end of the second level conversion circuit is electrically connected with the output end of the second trigger circuit, and the output end of the second level conversion circuit is used as a fourth output end of the second interface expansion circuit;
the trigger end of the phase adjusting circuit is electrically connected with the trigger end of the second trigger circuit, the input end of the phase adjusting circuit is electrically connected with the output end of the second level converting circuit, and the output end of the phase adjusting circuit is used as the fifth output end of the second interface expanding circuit;
the input end of the second potential determining circuit is electrically connected with the output end of the phase adjusting circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
7. The display device according to claim 6, wherein a third output terminal of the second interface expansion circuit is configured to output a third logic control signal, a fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and a fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is the same as the phase of the fourth logic control signal, and the pulse amplitude of the third logic control signal is different from the pulse amplitude of the fourth logic control signal; the phase of the fourth logic control signal is different from the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is the same as the pulse amplitude of the fifth logic control signal.
8. An electronic device comprising the display device according to any one of claims 1 to 7.
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| CN202210054107.9A CN114429746B (en) | 2022-01-18 | 2022-01-18 | Display device and electronic apparatus |
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| CN202210054107.9A CN114429746B (en) | 2022-01-18 | 2022-01-18 | Display device and electronic apparatus |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208208297U (en) * | 2018-05-31 | 2018-12-07 | 昆山龙腾光电有限公司 | A kind of Interface Expanding circuit and display device |
| CN109064982A (en) * | 2018-08-06 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit driving system and GOA circuit drive method and display device |
| CN109166547A (en) * | 2018-09-30 | 2019-01-08 | 惠科股份有限公司 | Driving circuit, display device and the display panel of display device |
| CN113178174A (en) * | 2021-03-22 | 2021-07-27 | 重庆惠科金渝光电科技有限公司 | Grid driving module, grid control signal generation method and display device |
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| CN109256103A (en) * | 2018-11-09 | 2019-01-22 | 惠科股份有限公司 | A kind of driving circuit of display device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208208297U (en) * | 2018-05-31 | 2018-12-07 | 昆山龙腾光电有限公司 | A kind of Interface Expanding circuit and display device |
| CN109064982A (en) * | 2018-08-06 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit driving system and GOA circuit drive method and display device |
| CN109166547A (en) * | 2018-09-30 | 2019-01-08 | 惠科股份有限公司 | Driving circuit, display device and the display panel of display device |
| CN113178174A (en) * | 2021-03-22 | 2021-07-27 | 重庆惠科金渝光电科技有限公司 | Grid driving module, grid control signal generation method and display device |
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