CN114417761B - Chip verification method, device and system, control server and medium - Google Patents

Chip verification method, device and system, control server and medium Download PDF

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CN114417761B
CN114417761B CN202210322718.7A CN202210322718A CN114417761B CN 114417761 B CN114417761 B CN 114417761B CN 202210322718 A CN202210322718 A CN 202210322718A CN 114417761 B CN114417761 B CN 114417761B
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verified
msid
address space
chip
address
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CN114417761A (en
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李毅
刘李玮玮
彭赢
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New H3C Semiconductor Technology Co Ltd
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New H3C Semiconductor Technology Co Ltd
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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Abstract

The embodiment of the application provides a chip verification method, a chip verification device, a chip verification system, a control server and a control medium, and relates to the technical field of testing. The technical scheme of the embodiment of the application comprises the following steps: the control server determines a first MSID and a first offset value corresponding to the current address space to be verified, wherein each MSID corresponds to a section of address space of the chip to be verified, and the first offset value is used for representing the offset value of the starting address of the address space to be verified relative to the starting address of the address space corresponding to the first MSID. And then sending a write operation command to the chip to be verified, and then sending a read operation command to the chip to be verified. And then verifying the chip to be verified based on the data to be written and the target data read from the chip to be verified. And then returning to the step of determining the first MSID and the first offset value until the verification of all address spaces of the chip to be verified is completed. The method and the device can comprehensively verify the address range of the chip on the basis of saving manpower.

Description

Chip verification method, device and system, control server and medium
Technical Field
The invention relates to the technical field of testing, in particular to a chip verification method, a chip verification device, a chip verification system, a control server and a control medium.
Background
In the process of chip design, prototype verification of the chip is an important link, and the problems existing in the chip design can be found before the chip is manufactured through verification of the chip, so that development cost is reduced.
At present, a chip is mainly verified through a simulation platform, but the running frequency of the simulation platform is relatively slow, and the running frequency of a real environment is generally more than one thousand times or even three or four thousand times of the running frequency of the simulation platform. Assuming that a real chip requires one minute to perform an operation, a chip in the emulation platform requires three to four thousand minutes to perform the same operation. If the range of address space that the chip needs to access is large, a large range of address space, such as 4 gigabytes (G) or even hundreds of G, needs to be traversed in order to verify the chip on the emulation platform. Because the time required for traversing a large-scale address space in a simulation platform is long, a part of addresses are generally selected manually for verification at present, the address range required to be accessed by a chip cannot be covered comprehensively, and a large amount of manpower is wasted.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, an apparatus, a system, a control server, and a medium for verifying a chip, so as to implement comprehensive verification of an address range of the chip on the basis of saving labor. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a chip verification method, which is applied to a control server, and the method includes:
determining a first memory space identifier MSID and a first offset value corresponding to a current address space to be verified, wherein each MSID corresponds to a section of address space of a chip to be verified, and the first offset value is used for representing the offset value of the initial address of the address space to be verified relative to the initial address of the address space corresponding to the first MSID;
sending a write operation command to the chip to be verified, wherein the write operation command comprises the first MSID, the first offset value and data to be written;
sending a read operation command to the chip to be verified, wherein the read operation command comprises the first MSID and the first offset value;
verifying the chip to be verified based on the data to be written and the target data read from the chip to be verified;
and returning to the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified until the verification of all address spaces of the chip to be verified is completed.
Optionally, determining the first MSID and the first offset value corresponding to the current address space to be verified includes:
acquiring a second MSID and a second deviation value corresponding to the last verified address space and the length of the last verified address space;
if the address space corresponding to the second MSID is not completely verified, taking the second MSID as the first MSID, and taking the sum of the second offset value and the address space length as the first offset value;
and if the address space corresponding to the second MSID is completely verified, taking the next MSID adjacent to the second MSID as the first MSID and taking 0 as the first deviation value.
Optionally, the determining a first MSID and a first offset value corresponding to the current address space to be verified includes:
acquiring a second MSID and a second deviation value corresponding to the last verified address space;
and taking the next MSID adjacent to the second MSID as the first MSID, and taking the offset value between the unverified first address in the address space corresponding to the next MSID and the starting address of the address space corresponding to the next MSID as the first offset value.
Optionally, the sending a write operation command to the chip to be verified includes:
sending the write operation command to an address conversion unit ATU of the chip to be verified through a PCIE (peripheral component interface express) interface of a high-speed serial computer expansion bus, so that the ATU calculates an address to be written based on the first MSID and the first offset value, and writes the data to be written into the address to be written;
the sending of the read operation command to the chip to be verified includes:
and sending the read operation command to an ATU of the chip to be verified through a PCIE interface, so that the ATU calculates an address to be read based on the first MSID and the first offset value, reads the target data from the address to be read, and sends the target data to the control server.
Optionally, before determining the first MSID and the first offset value corresponding to the current address space to be verified, the method further includes:
and configuring a mapping relation between the MSID and the address space for the ATU of the chip to be verified through the PCIE interface in the process of initializing the ATU of the chip to be verified.
Optionally, determining the first MSID and the first offset value corresponding to the current address space to be verified includes:
under the condition that the control server is in an idle state, executing the step of determining a first MSID and a first offset value corresponding to the current address space to be verified;
the method further comprises the following steps:
under the condition that the control server is in a non-idle state, the step of determining a first MSID and a first deviation value corresponding to the current address space to be verified is suspended, and a second MSID and a second deviation value corresponding to the last verified address space and the length of the last verified address space are recorded;
and when the control server restores the idle state, continuously executing the step of determining the first MSID and the first offset value corresponding to the current address space to be verified.
In a second aspect, an embodiment of the present application provides a chip verification apparatus, which is applied to a control server, and includes:
the verification module is used for verifying the address space to be verified, and the initial address of the address space to be verified is obtained by the first MSID;
a sending module, configured to send a write operation command to the chip to be verified, where the write operation command includes the first MSID, the first offset value, and data to be written;
the sending module is further configured to send a read operation command to the chip to be verified, where the read operation command includes the first MSID and the first offset value;
the verification module is used for verifying the chip to be verified based on the data to be written and the target data read from the chip to be verified;
and the returning module is used for returning the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified until the verification of all address spaces of the chip to be verified is completed.
Optionally, the determining module is specifically configured to:
acquiring a second MSID and a second deviation value corresponding to the last verified address space and the last verified address space length;
if the address space corresponding to the second MSID is not completely verified, taking the second MSID as the first MSID, and taking the sum of the second offset value and the address space length as the first offset value;
and if the address space corresponding to the second MSID is completely verified, taking the next MSID adjacent to the second MSID as the first MSID and taking 0 as the first deviation value.
Optionally, the determining module is specifically configured to:
acquiring a second MSID and a second offset value corresponding to the last verified address space;
and taking the next MSID adjacent to the second MSID as the first MSID, and taking the offset value between the unverified first address in the address space corresponding to the next MSID and the starting address of the address space corresponding to the next MSID as the first offset value.
Optionally, the sending module is specifically configured to:
sending the write operation command to an address conversion unit ATU of the chip to be verified through a PCIE (peripheral component interface express) interface of a high-speed serial computer expansion bus, so that the ATU calculates an address to be written based on the first MSID and the first offset value, and writes the data to be written into the address to be written;
the sending module is specifically configured to:
and sending the read operation command to an ATU of the chip to be verified through a PCIE interface, so that the ATU calculates an address to be read based on the first MSID and the first offset value, reads the target data from the address to be read, and sends the target data to the control server.
Optionally, the apparatus further comprises:
and the configuration module is used for configuring the mapping relation between the MSID and the address space for the ATU of the chip to be verified through the PCIE interface in the process of initializing the ATU of the chip to be verified before determining the first MSID and the first deviation value corresponding to the current address space to be verified.
Optionally, the determining module is specifically configured to:
under the condition that the control server is in an idle state, executing the step of determining a first MSID and a first offset value corresponding to the current address space to be verified;
the device further comprises:
a suspending module, configured to suspend execution of the steps of determining a first MSID and a first offset value corresponding to a current address space to be verified when the control server is in a non-idle state, and record a second MSID and a second offset value corresponding to a last verified address space and a last verified address space length;
and the recovery module is used for continuously executing the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified when the control server recovers the idle state.
In a third aspect, an embodiment of the present application provides a chip verification system, where the system includes: the system comprises a control server and a chip to be verified;
the control server is configured to perform the method of any one of the first aspect;
the chip to be verified is used for receiving a write operation command sent by the control server and writing data to be written into a physical address indicated by the write operation command; and the control server is further used for receiving a read operation command sent by the control server, reading target data from a physical address indicated by the read operation command, and sending the read target data to the control server.
In a fourth aspect, an embodiment of the present application further provides a control server, including a processor, a communication interface, a memory, and a communication bus, where the processor and the communication interface complete communication between the memory and the processor through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing any one of the chip verification method steps when executing the program stored in the memory.
In a fifth aspect, the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the chip verification method in the first aspect is implemented.
In a sixth aspect, embodiments of the present application further provide a computer program product containing instructions, which when run on a computer, cause the computer to execute the chip verification method described in the first aspect.
The embodiment of the application has the following beneficial effects:
according to the chip verification method, the device, the system, the control server and the medium provided by the embodiment of the application, the control server can determine the first MSID and the first deviation value corresponding to the current address space to be verified, then send a write operation command to the chip to be verified, and send a read operation command to the chip to be verified. And then verifying the chip to be verified based on the data to be written in the chip to be verified and the target data read from the chip to be verified. And then, returning to the step of determining the first MSID and the first offset value corresponding to the current address space to be verified until the verification of all the address spaces of the chip to be verified is completed. Therefore, the control server can automatically verify all address spaces of the chip to be verified without manual traversal, so that the labor consumed in the chip verification process is reduced, and the comprehensive coverage of all address spaces of the chip can be realized.
Of course, it is not necessary for any product or method to achieve all of the above-described advantages at the same time for practicing the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by referring to these drawings.
Fig. 1 is a schematic structural diagram of a chip verification system according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a chip verification method according to an embodiment of the present disclosure;
FIG. 3 is an exemplary diagram of an address space provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of another chip verification system provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a control server according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived from the embodiments given herein by one of ordinary skill in the art, are within the scope of the invention.
Different verification platforms may be used for the prototype verification of different modules of the chip and the whole chip system level, for example, the verification platform may be Electronic Design Automation (EDA), simulation (emulation) or Field Programmable Gate Array (FPGA). Because the scale of simulation and the frequency of simulation of the EDA are relatively slow, the EDA is mainly used for verifying a module-level or small-system-level chip, and the emulation and FPGA platforms are mainly used for verifying a complete-level chip.
In order to comprehensively verify the address range of a chip on the basis of saving manpower, the chip verification method provided by the embodiment of the present application may be applied to a chip verification system, as shown in fig. 1, where the chip verification system includes: a chip 101 to be verified and a control server 102. Wherein the content of the first and second substances,
and the control server 102 is used for controlling the chip 101 to be verified to read or write data from the address space to be verified.
And the chip to be verified 101 is used for reading or writing data from the address space to be verified under the control of the control server 102.
With reference to fig. 1, an embodiment of the present application provides a chip verification method, which is applied to a control server in fig. 1, and as shown in fig. 2, the method includes the following steps:
s201, determining a first Memory Space Identifier (MSID) and a first offset value corresponding to a current address Space to be verified.
In the embodiment of the present application, a total address space included in a Double Data Rate (DDR) granule connected to a chip to be verified may be divided into multiple segments, and each segment corresponds to one MSID. Therefore, each MSID corresponds to a section of address space of the chip to be verified, no intersection exists between the address spaces corresponding to each MSID, and the union of the address spaces corresponding to the MSIDs is all the address spaces of the chip to be verified.
The length of the address space verified each time is smaller than the length of the address space corresponding to each MSID, so that the current address space to be verified can be regarded as a subspace of the address space corresponding to the first MSID.
The first offset value is used to indicate an offset (offset) of the start address of the address space to be verified relative to the start address of the address space corresponding to the first MSID. For example, when the first offset value is 0, it indicates that the start address of the address space to be verified is the start address of the address space corresponding to the first MSID.
S202, sending a write operation command to the chip to be verified. The write operation command comprises the first MSID, a first offset value and data to be written.
The control server may send the first MSID to the chip to be verified, and then send the first offset value and the data to be written to the chip to be verified, so that the chip to be verified determines the start address of the current address space to be verified according to the first MSID and the first offset value, and writes the data to be written from the start address of the current address space to be verified.
Optionally, the data to be written may be preset, the content of the data to be written is not limited in the embodiment of the present application, and the data written each time may be the same or different. To simplify the verification process, the data to be written to each address space to be verified may be the same.
The write operation command may also include the data length of the data to be written. For example, the data length of data to be written is 4 bytes. So that the chip to be verified writes the data to be written with the data length from the initial address of the address space to be verified.
It can be understood that, since each address of the DDR granule corresponds to one byte of address space, the data length of the data to be written is equal to the length of the current address space to be verified. To simplify the verification process, the data length of the data to be written in each writing can be set to be the same, so that the address space length in each verification is the same.
And S203, sending a read operation command to the chip to be verified. Wherein the read operation command includes the first MSID and a first offset value.
The control server may send the first MSID to the chip to be verified, and then send the first offset value to the chip to be verified, so that the chip to be verified determines the starting address of the current address space to be verified according to the first MSID and the first offset value, reads the target data from the starting address of the current address space to be verified, and then returns the read target data to the control server.
The read operation command may further include a data length to be read, so that the chip to be verified reads data of the data length from the start address of the address space to be verified, where the read data is target data. The length of the data to be read is equal to the length of the data to be written in the current address space to be verified.
And S204, verifying the chip to be verified based on the data to be written and the target data read from the chip to be verified.
In one implementation, the control server may compare whether the data to be written is the same as the target data read from the chip to be verified. If the address space to be verified is the same as the address space to be verified, the verification of the current address space to be verified is passed. If not, the verification of the current address space to be verified is not passed.
And when the current address space to be verified is not verified, indicating that the read-write of the address space to be verified of the chip to be verified has errors.
S205, the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified is returned until the verification of all the address spaces of the chip to be verified is completed.
Optionally, in order not to repeatedly verify the address space of the chip to be verified, in the embodiment of the present application, the current address space to be verified may be selected according to the arrangement order of the address spaces. For example, when the lengths of the address spaces to be verified are all specified lengths, when S201 is executed for the first time, the address space of the first section of the specified length of all the address spaces of the chip to be verified is selected as the current address space to be verified, and verification of the current address space to be verified is performed. And then according to the arrangement sequence of the address spaces, selecting a next address space with a specified length from the unverified address spaces as the current address space to be verified, and further executing S202-S205 based on the redetermined current address space to be verified until the verification of all the address spaces of the chip to be verified is completed.
In the chip verification method provided by the embodiment of the application, the control server may determine the first MSID and the first offset value corresponding to the current address space to be verified, then send a write operation command to the chip to be verified, and send a read operation command to the chip to be verified. And then verifying the chip to be verified based on the data to be written in the chip to be verified and the target data read from the chip to be verified. And then, returning to the step of determining the first MSID and the first offset value corresponding to the current address space to be verified until the verification of all the address spaces of the chip to be verified is completed. Therefore, the control server can automatically verify all address spaces of the chip to be verified without manual traversal, so that the labor consumed in the chip verification process is reduced, and the comprehensive coverage of all address spaces of the chip can be realized.
In an embodiment of the present application, in the above manner that the control server determines the first MSID and the first offset value corresponding to the current address space to be verified in S201, there are the following two manners:
and in the first mode, the second MSID and the second deviation value corresponding to the last verified address space and the last verified address space length are obtained. And if the address space corresponding to the second MSID is not completely verified, taking the second MSID as the first MSID, and taking the sum of the second offset value and the address space length as the first offset value. If the address space corresponding to the second MSID has been completely verified, the next MSID adjacent to the second MSID is used as the first MSID, and 0 is used as the first offset value.
Wherein, the starting address of the last verified address space is the sum of the starting address of the second MSID and the second offset value. The last verified address space length is the address space length occupied by the last data written in the address space to be verified, that is, the address space length occupied by the last target data read in the address space to be verified. To simplify the verification process, the address space length for each verification may be the same.
In one implementation, the control server may determine whether the starting address of the last verified address space + the length of the last verified address space is equal to the end address of the address space corresponding to the second MSID. If yes, determining that the address space corresponding to the second MSID is completely verified; and if not, determining that the address space corresponding to the second MSID is not completely verified.
And the next MSID adjacent to the second MSID is the MSID of the address space next to the address space corresponding to the second MSID.
It can be seen that, in the first mode, the subspaces can be sequentially verified according to the arrangement sequence of the subspaces in the address space corresponding to each MSID. For example, in conjunction with fig. 3, a total of 16 MSIDs are shown in fig. 3, each MSID corresponding to a 4G address space, and a total of 64G address spaces. Assuming that the length of the address space to be verified each time is 4 bytes, when the control server determines the current address space to be verified for the first time, the control server takes the first 4-byte address space of the chip to be verified as the current address space to be verified, that is, the starting addresses of all the address spaces of the chip to be verified as the starting addresses of the current address space to be verified, that is, the MSID0 is taken as the first MSID, and the first offset value is determined to be 0. The next time the current address to be verified is determined, since the address space corresponding to the MSID0 was not fully verified, the MSID0 is still taken as the first MSID, and the first offset value is set to 0+4= 4. And so on until the address space corresponding to MSID15 is fully verified.
By determining the first MSID and the first deviation value in the first mode, the address spaces to be verified can be selected according to the sequence of the sub-spaces in all the address spaces of the chip to be verified and verified in sequence, and all the address spaces of the chip to be verified can be verified automatically and comprehensively.
And a second mode is to obtain a second MSID and a second deviation value corresponding to the last verified address space. And then taking the next MSID adjacent to the second MSID as the first MSID, and taking the offset value between the unverified first address in the address space corresponding to the next MSID and the starting address of the address space corresponding to the next MSID as the first offset value.
In one implementation, if the address space corresponding to the second MSID is not the last segment of all address spaces of the chip to be verified, the MSID of the address space of the next segment of the address space corresponding to the second MSID is taken as the first MSID. The total length of the next address space that has been verified is used as the first offset value. And if the address space corresponding to the second MSID is the last section of all the address spaces of the chip to be verified, taking the MSID of the first section of the address space of all the address spaces of the chip to be verified as the first MSID, and taking the total length of the first section of the address space which is verified as a first deviation value.
In order to simplify the verification process, the length of the address space for each verification may be the same, i.e. a fixed value. In this case, if the address space corresponding to the second MSID is not the last segment of all address spaces of the chip to be verified, the second offset value is taken as the first offset value. And if the address space corresponding to the second MSID is the last section of all the address spaces of the chip to be verified, adding a fixed value to the second offset value to serve as a first offset value.
For example, with reference to fig. 3, assuming that the length of the address space to be verified each time is 4 bytes, when the control server determines the current address space to be verified for the first time, the control server takes the first 4-byte address space of all address spaces of the chip to be verified as the current address space to be verified, that is, takes the start addresses of all address spaces of the chip to be verified as the start addresses of the current address space to be verified, that is, the MSID0 is taken as the first MSID, and determines that the first offset value is 0. The next time the current address space to be verified is determined, the next MSID of the MSIDs 0, namely MSID1, is taken as the first MSID, and the first offset value is maintained at 0. And by analogy, after the first 4 bytes of the address space corresponding to the MSID15 are verified, the address space of the second segment of 4 bytes in the address space corresponding to the verification MSID0 is returned, that is, the MSID0 is used as the first MSID, and 0+4=4 is used as the first offset value. And so on until the address space corresponding to MSID15 is fully verified.
The first MSID and the first offset value are determined in a segmented discontinuous mode, and the first MSID and the first offset value can be quickly covered to the address space corresponding to each MSID. If an error exists in the design of a certain MSID in the chip design, the error can be quickly found through the second mode, so that the iteration cycle of the chip is accelerated, and the verification efficiency of the chip is improved.
By adopting the first mode and the second mode, automatic traversal can be realized, and when the range of the address space needing to be verified is large, the required verification time is long, so that the control server in the embodiment of the application can not finish verification of all the address spaces at one time, when the control server is not in an idle state, traversal of the address spaces can be suspended, when the control server is restored to the idle state, traversal can be continued from the last verified address space by adopting the first mode or the second mode, and by adopting the multiple automatic verification mode, complete coverage of the address spaces needing to be verified can be realized, the utilization rate of the control server is improved, manpower is released, and chip verification can be efficiently finished. In addition, since the transmission to the Address Translation Unit (ATU) in the embodiment of the present application is not a real physical address, but an MSID and an offset value, a way for the ATU to access the DDR particles based on the physical address is greatly different from a way for the ATU to access the DDR particles based on the MSID and the offset value, and the accuracy of the operating mechanism of the ATU can be verified through the embodiment of the present application.
In an embodiment of the present application, the manner that the S202 controls the server to send the write operation command to the chip to be verified may be implemented as follows: and sending a write operation command to an ATU (advanced technology Unit) of the chip to be verified through a Peripheral Component Interconnect Express (PCIE) interface so that the ATU calculates an address to be written based on the first MSID and the first offset value and writes data to be written into the address to be written. The address to be written is the initial address of the current address space to be verified.
Correspondingly, the manner of the S203 controlling the server to send the read operation command to the chip to be verified may be implemented as follows: and sending a reading operation command to the ATU of the chip to be verified through the PCIE interface, so that the ATU calculates an address to be read based on the first MSID and the first offset value, reads target data from the address to be read, and sends the read target data to the control server. The address to be read is the initial address of the current address space to be verified.
Referring to fig. 4, an Application (APP) is installed in the control server, and the control server completes the chip verification method provided by the embodiment of the present application by running the APP. The control server is provided with a PCIE drive and a PCIE interface, and when the control server runs the APP to carry out chip verification, data transmitted between the APP and a chip to be verified need to pass through the PCIE drive and the PCIE interface.
The Device Under Test (DUT) in fig. 4 represents a simulation environment, the to-be-verified chip runs in the DUT, and the to-be-verified chip includes a Central Processing Unit (CPU), an ATU, a PCIE interface, and an address mapping unit. The CPU is provided with a core Board Support Package (core BSP). The right-most squares in fig. 4 represent DDR grains, and each square represents 4G of address space. The address space represented by the DDR granule shown in fig. 4 is 64G, and each MSID corresponds to an address space of 4G, all address spaces of the actual chip to be verified are not limited thereto, and the address space corresponding to each MSID is not limited thereto.
Because the chip to be verified operates in the simulation environment and the control server operates in the real environment, the control server has a PCIE interface in the real environment, and the chip to be verified has a simulated PCIE interface. Because a frequency reduction ratio exists between the real environment and the simulation environment, and the difference between the processing rates of the real environment and the simulation environment is large, as shown in fig. 4, the PCIE interface of the control server may be connected to the PCIE interface of the chip to be verified through a Speed Bridge (Speed Bridge), so as to implement rate matching between the control server and the chip to be verified.
The control server can send the first MSID and the first deviation value to the ATU through the PCIE interface, and then the ATU performs address conversion on the received first MSID and the first deviation value to obtain a physical address. And then the ATU sends a physical address to an address mapping unit, so that the address mapping unit maps to the DDR particles according to the physical address to write data to be written, or read target data.
The range of the address space accessible by the chip is associated with the bit width of the address bus, and when the address bus of the chip is 32 bits, the chip can access 2 at most32Address space of =4G, when the address bus is 64 bits, the chip can access 2 at most64=16 octets: (Exabyte, EB). However, in some specially designed chips, the address bus is only 32 bits, but the required address space of the DDR granule exceeds 4G, in order to enable the chip to access the address space exceeding 4G, the embodiment of the present invention extends the address space accessible by the chip through the MSID, fig. 4 takes the address bus of the chip to be verified as 32 as an example, the address space corresponding to each MSID is 4G, and of course, in the case that the address bus of the chip to be verified is 32, the address space corresponding to each MSID may also be set to other values not exceeding 4G.
In addition, in the related art, the PCIE interface of the control server maps the Address space of the chip through a Base Address Register (BAR) space, but currently, the BAR cannot map the Address space exceeding 4G. In the embodiment of the present application, since the MSID represents a segment of address space and the offset value represents an offset in the segment of address space, the ATU can determine a specific physical address through the MSID and the offset value. Therefore, the control server does not need to send a real physical address to the ATU, but sends the MSID and the offset value, and the address space range is expanded through the MSID, so that the control server can control the chip to be verified to access a larger address space range.
In an embodiment of the present application, before determining the first MSID and the first offset value corresponding to the current address space to be verified in the S201, the ATU of the chip to be verified also needs to be initialized in the embodiment of the present application, and in the process of initializing the ATU of the chip to be verified, the mapping relationship between the MSID and the address space may be configured for the ATU of the chip to be verified through the PCIE interface.
In one implementation, the control server may send the start address and the end address of the address space corresponding to each MSID to the ATU through the PCIE interface.
Optionally, with reference to fig. 4, when initializing the DUT, the DUT may be powered on first, and then the initialization operation of the minimal system on chip is completed through the core BSP configured in the CPU of the DUT, so that some critical interfaces including the PCIE interface in the DUT may work normally. Then, the control server may send the mapping relationship between the MSID and the address space to the ATU through the PCIE interface, so as to initialize the ATU.
In addition, the control server can also carry out initialization configuration on other modules of the chip simulated by the DUT, so that the DUT can work normally. In this embodiment, only the ATU included in the DUT is shown in fig. 4, and other modules may also be included in the DUT, which is not specifically limited in this embodiment.
Optionally, with reference to fig. 4, an APP or a script for performing chip verification is configured in the control server, where the chip verification process shown in fig. 2 and the initialization process performed on the DUT may be integrated in the same APP or script, or may also be completed by different APPs or scripts.
In the embodiment of the application, a PCIE driver is configured in an Operating System (OS) kernel of the control server, and after the control server opens the APP or the script, the control server opens a file corresponding to the PCIE interface, determines data that needs to be sent to the ATU, and sends the data that needs to be sent to the PCIE interface through the PCIE driver, so that the data is transmitted to the ATU through the PCIE interface.
The APP is applied to a user mode, namely, the verification process of the chip to be verified and the initialization process of the DUT can be interrupted by other processes at any time, and the influence of the verification of the chip to be verified on other works is reduced.
In an embodiment of the present application, a manner of determining the first MSID and the first offset value corresponding to the current address space to be verified in S201 may be implemented as follows: and under the condition that the control server is in an idle state, executing the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified.
Correspondingly, under the condition that the control server is in a non-idle state, the step of determining the first MSID and the first offset value corresponding to the current address space to be verified is suspended, and the second MSID and the second offset value corresponding to the last verified address space and the length of the last verified address space are recorded. And when the control server restores the idle state, continuously executing the step of determining the first MSID and the first offset value corresponding to the current address space to be verified.
Optionally, the control server may be set to be in an idle state for a specified time period, for example, the specified time period is 22:00-5: 00. Or, the control server may monitor its own operating data such as CPU occupancy, memory occupancy, and the like, and determine whether it is in an idle state based on the operating data. Therefore, chip verification is performed in an idle state, and the influence of the chip verification on other work of the control server is reduced.
Because the operating frequency of the simulation environment is different from that of the real environment, that is, the operating frequency of the control server is much higher than that of the chip to be verified, for example, the operating frequency of the real chip is generally several gigahertz, and the operating frequency of the simulation platform where the chip to be verified is located is generally several hundred kilo (kilo, K) to several mega (mega, M) hertz, it takes a long time to traverse the complete address space of the chip to be verified. Moreover, a simulation platform for running the chip to be verified is relatively expensive, and belongs to a scarce resource for prototype verification of the chip. If the chip verification is carried out in a manual mode, a large amount of manpower is wasted, and the simulation platform is greatly occupied in the working peak period. The embodiment of the application can automatically verify the chip to be verified when the control server is relatively idle, so that the labor consumed by chip verification is reduced, and the occupation of a simulation platform in a working peak period is reduced.
In addition, when the address space of the chip to be verified is large, the time consumed for verifying all the address spaces of the chip is too long. In the embodiment of the application, the control server can verify the address space of the chip to be verified for multiple times, and record the current verification position after each verification, so that the verification is continued from the position next time until the comprehensive verification of all the address spaces is completed. Therefore, the chip verification method provided by the embodiment of the application can improve the utilization rate of the control server, release manpower and efficiently complete comprehensive verification of the chip address space.
Based on the same inventive concept, corresponding to the above method embodiments, the embodiments of the present application provide a chip verification system, which includes: the control server and the chip to be verified.
The control server is used for executing the method steps executed by the method embodiment;
the chip to be verified is used for receiving the write operation command sent by the control server and writing data to be written into the physical address indicated by the write operation command; the control server is also used for receiving a read operation command sent by the control server, reading target data from a physical address indicated by the read operation command, and sending the read target data to the control server.
In one embodiment of the present application, the system may further include: speed Bridge. The PCIE interface of the control server is connected with the PCIE interface of the chip to be verified through a Speed Bridge.
The Speed Bridge is provided with two PCIE interfaces with different frequencies, receives data sent by the control server through one PCIE interface, and forwards the data to the other PCIE interface for reducing the frequency after buffering the data, and forwards the buffered data to the chip to be verified through the other PCIE interface, so that the communication between the chip to be verified for reducing the frequency and the control server is transparent. By adding the Speed Bridge between the control server and the chip to be verified, the embodiment of the application can realize frequency matching between the control server and the chip to be verified.
Based on the same inventive concept, corresponding to the above method embodiment, an embodiment of the present application provides a chip verification apparatus, which is applied to a control server, and as shown in fig. 5, the apparatus includes: a determination module 501, a sending module 502, a verification module 503 and a return module 504;
a determining module 501, configured to determine a first memory space identifier MSID and a first offset value corresponding to a current address space to be verified, where each MSID corresponds to a segment of address space of a chip to be verified, and the first offset value is used to indicate an offset value of a starting address of the address space to be verified relative to a starting address of the address space corresponding to the first MSID;
a sending module 502, configured to send a write operation command to a chip to be verified, where the write operation command includes the first MSID, the first offset value, and data to be written;
a sending module 502, further configured to send a read operation command to the chip to be verified, where the read operation command includes the first MSID and the first offset value;
the verification module 503 is configured to verify the chip to be verified based on the data to be written and the target data read from the chip to be verified;
a returning module 504, configured to return the step of determining the first MSID and the first offset value corresponding to the current address space to be verified until the verification of all address spaces of the chip to be verified is completed.
In an embodiment of the present application, the determining module 501 is specifically configured to:
acquiring a second MSID and a second deviation value corresponding to the last verified address space and the length of the last verified address space;
if the address space corresponding to the second MSID is not completely verified, taking the second MSID as the first MSID, and taking the sum of the second offset value and the address space length as the first offset value;
if the address space corresponding to the second MSID has been completely verified, the next MSID adjacent to the second MSID is used as the first MSID, and 0 is used as the first offset value.
In an embodiment of the present application, the determining module 501 is specifically configured to:
acquiring a second MSID and a second deviation value corresponding to the last verified address space;
and taking the next MSID adjacent to the second MSID as a first MSID, and taking the offset value between the unverified first address in the address space corresponding to the next MSID and the starting address of the address space corresponding to the next MSID as a first offset value.
In an embodiment of the present application, the sending module 502 is specifically configured to:
sending a write operation command to an address conversion unit ATU of a chip to be verified through a PCIE interface of a high-speed serial computer expansion bus, so that the ATU calculates an address to be written based on the first MSID and the first offset value, and writes data to be written into the address to be written;
the sending module 502 is specifically configured to:
and sending a read operation command to the ATU of the chip to be verified through the PCIE interface, so that the ATU calculates an address to be read based on the first MSID and the first offset value, reads target data from the address to be read, and sends the target data to the control server.
In one embodiment of the present application, the apparatus further comprises:
and the configuration module is used for configuring the mapping relation between the MSID and the address space for the ATU of the chip to be verified through the PCIE interface in the process of initializing the ATU of the chip to be verified before determining the first MSID and the first deviation value corresponding to the current address space to be verified.
In an embodiment of the present application, the determining module 501 is specifically configured to:
under the condition that the control server is in an idle state, executing the step of determining a first MSID and a first offset value corresponding to the current address space to be verified;
the device still includes:
the system comprises a pause module, a verification module and a verification module, wherein the pause module is used for pausing and executing the steps of determining a first MSID and a first deviation value corresponding to the current address space to be verified under the condition that a control server is in a non-idle state, and recording a second MSID and a second deviation value corresponding to the last verified address space and the length of the last verified address space;
and the recovery module is used for continuously executing the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified when the control server recovers the idle state.
The embodiment of the present application further provides a control server, as shown in fig. 6, which includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, where the processor 601, the communication interface 602, and the memory 603 complete mutual communication through the communication bus 604,
a memory 603 for storing a computer program;
the processor 601 is configured to implement the method steps in the above method embodiments when executing the program stored in the memory 603.
The communication bus mentioned above for the control server may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this is not intended to represent only one bus or type of bus.
The communication interface is used for communication between the control server and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In another embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program realizes the steps of any one of the chip verification methods when executed by a processor.
In yet another embodiment, the present invention further provides a computer program product containing instructions, which when run on a computer, causes the computer to execute any of the chip verification methods in the above embodiments.
In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to be performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments. In particular, as for the apparatus and system embodiments, since they are substantially similar to the method embodiments, the description is relatively simple and reference may be made to the partial description of the method embodiments for relevant points.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims (11)

1. A chip verification method is applied to a control server, and comprises the following steps:
determining a first memory space identifier MSID and a first offset value corresponding to a current address space to be verified, wherein each MSID corresponds to a section of address space of a chip to be verified, and the first offset value is used for representing the offset value of the initial address of the address space to be verified relative to the initial address of the address space corresponding to the first MSID;
sending a write operation command to the chip to be verified, wherein the write operation command comprises the first MSID, the first offset value and data to be written;
sending a read operation command to the chip to be verified, wherein the read operation command comprises the first MSID and the first offset value;
verifying the chip to be verified based on the data to be written and the target data read from the chip to be verified;
returning to the step of determining the first MSID and the first offset value corresponding to the current address space to be verified until the verification of all the address spaces of the chip to be verified is completed;
the sending of the write operation command to the chip to be verified includes:
sending the write operation command to an address conversion unit ATU of the chip to be verified through a PCIE (peripheral component interface express) interface of a high-speed serial computer expansion bus, so that the ATU calculates an address to be written based on the first MSID and the first offset value, and writes the data to be written into the address to be written;
the sending of the read operation command to the chip to be verified includes:
sending the read operation command to an ATU of the chip to be verified through a PCIE interface, so that the ATU calculates an address to be read based on the first MSID and the first offset value, reads the target data from the address to be read, and sends the target data to the control server;
before determining the first MSID and the first offset value corresponding to the current address space to be verified, the method further includes:
and configuring a mapping relation between the MSID and the address space for the ATU of the chip to be verified through the PCIE interface in the process of initializing the ATU of the chip to be verified.
2. The method of claim 1, wherein determining the first MSID and the first offset value corresponding to the current address space to be verified comprises:
acquiring a second MSID and a second deviation value corresponding to the last verified address space and the last verified address space length;
if the address space corresponding to the second MSID is not completely verified, taking the second MSID as the first MSID, and taking the sum of the second offset value and the address space length as the first offset value;
and if the address space corresponding to the second MSID is completely verified, taking the next MSID adjacent to the second MSID as the first MSID and taking 0 as the first deviation value.
3. The method of claim 1, wherein determining the first MSID and the first offset value corresponding to the current address space to be verified comprises:
acquiring a second MSID and a second deviation value corresponding to the last verified address space;
and taking the next MSID adjacent to the second MSID as the first MSID, and taking the offset value between the unverified first address in the address space corresponding to the next MSID and the starting address of the address space corresponding to the next MSID as the first offset value.
4. The method of claim 1, wherein determining the first MSID and the first offset value corresponding to the current address space to be verified comprises:
under the condition that the control server is in an idle state, executing the step of determining a first MSID and a first offset value corresponding to the current address space to be verified;
the method further comprises the following steps:
under the condition that the control server is in a non-idle state, the step of determining a first MSID and a first deviation value corresponding to the current address space to be verified is suspended, and a second MSID and a second deviation value corresponding to the last verified address space and the length of the last verified address space are recorded;
and when the control server restores the idle state, continuously executing the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified.
5. A chip verification apparatus, applied to a control server, the apparatus comprising:
the verification module is used for verifying a first Memory Space Identifier (MSID) and a first offset value corresponding to a current address space to be verified, wherein each MSID corresponds to a section of address space of a chip to be verified, and the first offset value is used for representing an offset value of a starting address of the address space to be verified relative to a starting address of the address space corresponding to the first MSID;
a sending module, configured to send a write operation command to the to-be-verified chip, where the write operation command includes the first MSID, the first offset value, and to-be-written data;
the sending module is further configured to send a read operation command to the chip to be verified, where the read operation command includes the first MSID and the first offset value;
the verification module is used for verifying the chip to be verified based on the data to be written and the target data read from the chip to be verified;
the return module is used for returning to the step of determining the first MSID and the first offset value corresponding to the current address space to be verified until the verification of all the address spaces of the chip to be verified is completed;
the sending module is specifically configured to:
sending the write operation command to an address conversion unit ATU of the chip to be verified through a PCIE (peripheral component interface express) interface of a high-speed serial computer expansion bus, so that the ATU calculates an address to be written based on the first MSID and the first offset value, and writes the data to be written into the address to be written;
the sending module is specifically configured to:
sending the read operation command to an ATU of the chip to be verified through a PCIE interface, so that the ATU calculates an address to be read based on the first MSID and the first offset value, reads the target data from the address to be read, and sends the target data to the control server;
the device further comprises:
and the configuration module is used for configuring the mapping relation between the MSID and the address space for the ATU of the chip to be verified through the PCIE interface in the process of initializing the ATU of the chip to be verified before determining the first MSID and the first deviation value corresponding to the current address space to be verified.
6. The apparatus of claim 5, wherein the determining module is specifically configured to:
acquiring a second MSID and a second deviation value corresponding to the last verified address space and the length of the last verified address space;
if the address space corresponding to the second MSID is not completely verified, taking the second MSID as the first MSID, and taking the sum of the second deviation value and the address space length as the first deviation value;
and if the address space corresponding to the second MSID is completely verified, taking the next MSID adjacent to the second MSID as the first MSID and taking 0 as the first deviation value.
7. The apparatus of claim 5, wherein the determining module is specifically configured to:
acquiring a second MSID and a second offset value corresponding to the last verified address space;
and taking the next MSID adjacent to the second MSID as the first MSID, and taking the offset value between the unverified first address in the address space corresponding to the next MSID and the starting address of the address space corresponding to the next MSID as the first offset value.
8. The apparatus of claim 5, wherein the determining module is specifically configured to:
under the condition that the control server is in an idle state, executing the step of determining a first MSID and a first offset value corresponding to the current address space to be verified;
the device further comprises:
a suspending module, configured to suspend execution of the steps of determining a first MSID and a first offset value corresponding to a current address space to be verified when the control server is in a non-idle state, and record a second MSID and a second offset value corresponding to a last verified address space and a last verified address space length;
and the recovery module is used for continuously executing the step of determining the first MSID and the first deviation value corresponding to the current address space to be verified when the control server recovers the idle state.
9. A chip verification system, the system comprising: the method comprises the steps of controlling a server and a chip to be verified;
the control server is configured to perform the method of any one of claims 1-4;
the chip to be verified is used for receiving a write operation command sent by the control server and writing data to be written into a physical address indicated by the write operation command; the control server is further configured to receive a read operation command sent by the control server, read target data from a physical address indicated by the read operation command, and send the read target data to the control server.
10. The control server is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing the communication between the processor and the memory through the communication bus;
a memory for storing a computer program;
a processor for implementing the method of any one of claims 1 to 4 when executing a program stored in the memory.
11. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 1 to 4.
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