CN114417378A - Key exchange or public key cipher encryption optimization method and system based on Messen number - Google Patents

Abstract

The invention discloses a key exchange or public key cipher encryption optimization method and system based on a Messen number, which comprises the following steps: in an application scene of key exchange or public key cryptography calculation, selecting or constructing a modulus of a modulus operation mod, and replacing the modulus operation mod with a first modulus operation or a second modulus operation according to the modulus; when the selected modulus is the Meisen number or the modulus in the algorithm is constructed to be just the Meisen number, replacing the modulus operation mod with a first modulus operation; the modulo operation mod is replaced with a second modulo operation when the modulus of the selected or constructed is a positive integer that is similar in form to the meisen number. The invention can optimize the operations of modular addition, modular multiplication and modular exponentiation by utilizing the mathematical characteristics of the Meisen number, obviously reduce the complexity of calculation and improve the speed of key exchange and public key cipher encryption and decryption.

Description

Key exchange or public key cipher encryption optimization method and system based on Messen number

Technical Field

The invention relates to the technical field of information security encryption authentication, in particular to a key exchange or public key cryptography encryption optimization method and system based on a Messen number.

Background

In the current world of rapid development of information technology, information security protection plays a very important role. In the aspects of e-commerce, APP application related to personal information, and the like, security protection methods such as encryption and authentication are often required, such as key exchange, public key encryption and decryption, and the like. Examples are as follows:

1. key exchange

An example of a key exchange algorithm is the DHM (Diffie-Hellman-Merkle) algorithm (old called DH algorithm). The algorithm is based on the discrete logarithm problem and is a classical algorithm for creating a public key cryptosystem. The DHM key exchange does not require a complete public key cipher (a pair of public and private keys) to encrypt the transmission session key K, as long as both parties negotiate a session key K.

After the key exchange, the obtained K is used as a key, and a single-key algorithm such as AES is used for decryption algorithms of the two parties A and B, because the DHM algorithm can only exchange the key and cannot directly encrypt and decrypt the plaintext.

The rough process of encrypted transmission by the DHM + AES algorithm is as follows: the two parties respectively generate a random number in a secret way, then exchange information through a DHM algorithm, combine the two random numbers to form a random key K which is used as a session key for AES encryption and decryption, and then the two parties carry out encryption communication by using the AES algorithm.

2. Public key cryptography

Public key cryptography has a wide range of applications, including digital signatures, and also session key exchanges. For example, among pgp (pretty Good privacy) protocols, there is an encryption protocol supporting RSA + AES, where RSA is a public key cipher, AES is a single key cipher, and the combined encryption communication process of the two is similar to the communication process of the aforementioned DHM key exchange, except that the DHM algorithm is changed into RSA algorithm, the number of interactions is 1 less than that of the DHM algorithm, and the complete random key K is encrypted and decrypted instead of the negotiated K value.

The rough process of encrypting transmission by the RSA + AES algorithm is as follows: party A randomly generates a session key K, then uses public key of party B of RSA to encrypt the K, and transmits the K to party B, party B uses its private key to decrypt the K, and then both parties can use the session key K to carry out AES encryption communication.

The encrypted communication of the actual content is performed by the AES algorithm, rather than directly by the RSA algorithm (which is possible in principle), because the RSA algorithm is much slower than AES, it takes little time to encrypt a random key K, and it takes much time to encrypt the plaintext of the entire communication.

In addition to the RSA algorithm (based on the prime factorization puzzle), there are other public key cryptographic algorithms, such as the Elgamal algorithm (based on the discrete logarithm puzzle).

The above-mentioned key exchange and public key cryptography algorithms such as DHM, RSA, Elgamal, etc. have a common disadvantage that the calculation speed is relatively slow. One important reason for the slow speed is that these mathematical problem-based encryption and decryption algorithms involve long integer arithmetic (long integers are usually more than 1024 bits in length) and must be implemented through many complex operations using a typical 32-bit, 64-bit computer (Michael welschenbach. crypto. C and C + + implementation of encryption method (second edition) [ M ]. electronics industry press, 2003.).

One key operation in these calculations is modulus (i.e., integer division takes the remainder), and the operator is denoted by mod. The modular operation is a common operation which needs to be performed once in almost every step of calculation, but various existing algorithms do not refer to the meisen number, such as modular addition, modular multiplication, modular exponentiation and the like.

Die addition: y is A + B mod M

Modular multiplication: y is A B mod M

Modular exponentiation: y is A^B mod M

Where M is referred to as the modulus, i.e., the divisor in a modulo (integer division by remainder) operation. Just as this mod operation significantly slows down computation, especially modular exponentiations, a modular exponentiation requires up to 2048 mod operations (involving 1024 base squares, 1024 iterative multiplications), assuming A, B, M are all 1024 bit integers. Therefore, how to increase the operation speed becomes an important issue.

Brief introduction to the related art

1. Hardware parallel acceleration

The algorithm is not changed, and the parallelism of calculation is directly improved by hardware, so that the acceleration effect is achieved. Such as with array multipliers, FPGA custom acceleration circuits (e.g., dividers), ASIC specific circuits (e.g., RSA acceleration chips), etc.

The hardware method has the defects that the algorithm is not simplified, so that the hardware is complex, the cost is high, the power consumption is large, and when the encryption algorithm software is transplanted to a platform without hardware acceleration, only pure software calculation can be carried out, so that the acceleration effect disappears.

2. Software algorithm optimization, exemplified by Montgomery (Montgomery) algorithm

The Montgomery algorithm is optimized for modular exponentiation, and the main idea is to reduce division operation, thereby reducing time consumption.

Although the software optimization algorithm like the Montgomery algorithm can improve the speed, the algorithm is complex and is not easy to realize by hardware (hardware acceleration). Even if the hardware is used for realizing the method, the circuit is complex and the cost is high.

Regarding the Merson number, the Merson number is 2ⁿA positive integer of 1, which has some favorable mathematical properties. If a Merson number is a prime number, it is called Merson prime. Let P be 2ⁿIf-1 is the Mersen number, then for all key exchange and public key cryptographic algorithms based on the discrete logarithm problem, such as DHM and Elgamal algorithms, if the Mersen prime number M is used as a modulus, or the Mersen number M is constructed as a modulus in other algorithms such as RSA which do not use prime numbers as moduli, then the operations of modular addition, modular multiplication and modular exponentiation in the calculation process do not need to be divided, and a new fast method can be adopted.

Disclosure of Invention

The invention aims to overcome the speed deficiency of the existing encryption calculation, provides a key exchange or public key encryption optimization method and system based on the Mersen number, and provides a corresponding key exchange or public key encryption calculation core circuit logic system based on the Mersen number, so that the mathematical characteristics of the Mersen number can be utilized to optimize modular exponentiation, the calculation complexity is obviously reduced, the calculation speed is improved, the circuit design can be simplified on hardware, the performance is improved, and the power consumption is reduced.

The invention is realized by at least one of the following technical schemes.

The key exchange or public key cipher encryption optimization method based on the Messen number comprises the following steps: in the application scene of key exchange or public key cryptography calculation, selecting or constructing a modulus of a modulus operation mod, and replacing the modulus operation mod with a first modulus operation mod1 or a second modulus operation mod2 according to the modulus; when the selected modulus is the Mersen number M-2ⁿ-1, or replacing the modulo operation mod with a first modulo operation mod1, where n is a positive integer, when the modulus in the algorithm is constructed to be exactly the meisen number;

when the modulus of the selected or constructed structure is a positive integer K-2 similar to the Mersen numberⁿL, the modulo operation mod is replaced with a second modulo operation mod 2.

Further, the application scenarios include the adoption of algorithms based on discrete logarithm problem, algorithms based on prime factor decomposition problem, algorithms based on discrete elliptic curve problem and other algorithms with modular addition, modular multiplication and modular exponentiation as main operation quantity.

Further, the first modulo operation mod1 is a fast modulo operation without division.

Further, the first modulo operation mod1 is as follows:

let M be the Messen number, i.e. M2ⁿ1, the result of the first modulo operation mod1 is the same as the original modulo operation mod:

die addition: y + a mod 1M + a + B mod (2)ⁿ-1), wherein a, B represent two addends of a modulo addition operation;

modular multiplication: y ═ a × B mod 1M ═ a × B mod (2)ⁿ-1), wherein A, B represent a modular multiplication operationTwo multipliers of (a);

modular exponentiation: y is A^B mod1 M＝A^B mod(2ⁿ-1), wherein a represents the base of a modular exponentiation and B represents the exponent of the modular exponentiation.

Further, the operation flow of the first modulo operation mod1 includes the following steps:

s101, taking an n-bit positive integer A and an n-bit positive integer B;

step S102, judging whether the operation is modular addition operation or modular multiplication operation, and respectively turning to the steps S103 and S104;

step S103, calculating addition result Y before modulus₀Go to step S105;

step S104, calculating multiplication result Y before modulus₀＝A*B；

Step S105, processing Y₀Splitting into lower n-bits Y₁High n-position Y₂；

Step S106, calculating Y ═ Y₁+Y₂；

Step S107, judging whether Y is equal to M, if not, turning to step S109, wherein the modulus M is a Mersen number;

step S108, carrying out overflow condition processing, and enabling Y to be 0;

step S109, the process ends, and Y is the result of mod1 operation.

Further, the second modulo operation mod2 is a fast modulo operation without division.

Further, the second modulo operation mod2 is as follows:

modulus is positive integer K ═ 2ⁿ-L, where L is a small positive integer, usually L<2⁶64, the operation has no division operation:

die addition: y + a mod 2K + a + B mod (2)ⁿ-L), wherein a, B represent two addends of a modulo addition operation;

modular multiplication: y ═ a × B mod 2K ═ a × B mod (2)ⁿ-L), where a, B represent two multipliers of a modular multiplication operation;

modular exponentiation: y is A^B mod2 K＝A^B mod(2ⁿ-L), whereinA denotes the base of the modular exponentiation, and B denotes the exponent of the modular exponentiation.

Further, the operation flow of the second modulo operation mod2 includes the following steps:

step S201, taking an n-bit positive integer A, n bit positive integer B and a 6-bit positive integer L;

step S202, judging whether the operation is modular addition operation or modular multiplication operation, and respectively turning to step S203 and step S204;

step S203, calculating addition result Y before modulus₀Go to step S205;

step S204, calculating multiplication result Y before modulus₀＝A*B；

Step S205, processing Y₀Splitting into lower n-bits Y₁High n-position Y₂；

Step S206, calculating Y ═ Y₁+Y₂*L；

Step S207, if Y is less than K, then go to step S209, wherein the modulus K is a positive integer with a shape similar to the Mersen number;

step S208, processing the overflow condition, and making Y₀Y-K, and in a hardware implementation, let Y₀＝Y+L-2ⁿThen go to step S205;

in step S209, the flow ends, and Y is the result of mod2 operation.

Further, one or more fast modulo arithmetic logic circuit components C1, capable of supporting the first modulo operation mod 1; the fast modulo arithmetic logic circuit component C1 includes:

the n-bit register RegA is used for temporarily storing the input number A;

the n-bit register RegB is used for temporarily storing the input number B;

an n-bit adder ADD1 for adding two numbers and outputting n-bit integer and carry flag C;

an n-bit multiplier MUL for multiplying two numbers and outputting a 2 n-bit integer;

a 2 n-bit register RegY0 for temporarily storing intermediate data;

the n-bit adder ADD2 is used for finishing the fast modular computation and outputting an n-bit integer and a carry flag C;

the logic gate circuit comprises n AND gates and 1 NOT gate;

an n-bit register RegY for temporarily storing the output number Y;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit adder ADD 1;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit multiplier MUL;

the adder ADD1 outputs to bits 0 to n-1 of the register RegY0, and the carry flag C outputs to bit n of RegY 0;

the multiplier MUL outputs to bits 0 to 2n-1 of the register RegY 0;

the low n bits and the high n bits of the register RegY0 are respectively output to two input ends of an n-bit adder ADD 2;

the adder ADD2 outputs to one input end of n AND gates, the carry flag C outputs to 1 NOT gate, and the NOT gate outputs to the other input end of n AND gates;

the n AND gates output to bits 0 to n-1 of register RegY.

Further, one or more fast modulo arithmetic logic circuit components C2 are included capable of supporting the second modulo operation mod 2; the fast modulo arithmetic logic circuit component C2 includes:

the n-bit register RegA is used for temporarily storing the input number A;

the n-bit register RegB is used for temporarily storing the input number B;

an n-bit adder ADD1 for adding two numbers and outputting n-bit integer and carry flag C;

an n-bit multiplier MUL1 for multiplying two numbers and outputting 2 n-bit integer;

a 2 n-bit register RegY0 for temporarily storing intermediate data;

an L-bit register RegL for temporarily storing an input number L;

an n-bit multiplier MUL2 for calculating a correction value in the modulo calculation;

an n + 6-bit adder ADD2, configured to complete fast modulo computation, and output an n + 6-bit integer and a carry flag C (n.. n +5), that is, if the n-th to n + 5-th bits output all 0's and there is no higher carry, C (n.. n +5) is 0, otherwise C (n.. n +5) is 1;

a logic gate circuit having 1 NOT gate;

an n +6 bit demultiplexer DMUX, one of two outputs;

an n-bit register RegY for temporarily storing the output number Y;

an n-bit adder ADD3 for performing overflow processing of low n bits;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit adder ADD 1;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit multiplier MUL 1;

the adder ADD1 outputs to bits 0 to n-1 of the register RegY0, and the carry flag C outputs to bit n of RegY 0;

the multiplier MUL1 outputs to bits 0 to 2n-1 of register RegY 0;

the lower n bits of the register RegY0 are output to the lower n bits of one input end of the n + 6-bit adder ADD 2;

the high n bits of the register RegY0 are output to one input of an n-bit multiplier MUL 2;

the register RegL outputs the lower 6 bits to the other input of the n-bit multiplier MUL 2;

the multiplier MUL2 outputs to the other input terminal of the n + 6-bit adder ADD 2;

the adder ADD2 outputs to the n + 6-bit demultiplexer DMUX, the flag bit C (n.. n +5) outputs to 1 NOT gate, and the NOT gate outputs to the alternative selection end of the demultiplexer DMUX;

when the selection end inputs 0, the low n bits of one path in the demultiplexer DMUX are output to one input end of the adder ADD3, the n th to n +5 th bits of the same path are output to the n th to n +5 th bits of the register RegY0, and when the selection end inputs 1, the low n bits of the other path are output to the 0 th to n-1 bits of the register RegY;

the register RegL outputs bits 0 to 5 to the other input terminal of the adder ADD 3;

the adder ADD3 outputs to bits 0 through n-1 of the register RegY 0.

Compared with the prior art, the invention has the following advantages and beneficial effects:

the method of the invention adopts the Mersen number or the approximate Mersen number as the modulus, so that the time complexity of the modulus operation can be greatly reduced, thereby optimizing the operations of the modulus addition, the modulus multiplication and the modulus exponentiation and improving the speed of the key exchange and the encryption and decryption of the public key cipher.

The system of the invention is a core circuit logic system based on the quick key exchange of the Meisen number and the calculation of the public key cryptography, and an improved logic system, which can simplify the circuit design, improve the performance and reduce the power consumption.

Drawings

FIG. 1 is a flowchart of a first modulo operation mod1 with a Mersen number as a modulus according to a method for optimizing a key exchange or public key cryptography based on the Mersen number of the present invention;

FIG. 2 is a flow chart of a second modulo operation mod2 according to the present invention with the approximate Meisen number as the modulus;

FIG. 3 is a circuit diagram of a first modulo operation C1 according to the present invention using the Mersen number as the modulus;

FIG. 4 is a circuit diagram of a second modulo operation C2 according to the present invention with the approximate Meisen number as the modulus.

Detailed Description

One embodiment of the present invention based on the meisen number (mod1/C1) and another improved embodiment based on the approximate meisen number (mod2/C2) are described in further detail below with reference to the following examples and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

A key exchange or public key cryptography encryption optimization method based on a Mersen number comprises the steps of selecting or constructing a modulus of a modulus operation mod in an application scene of key exchange or public key cryptography calculation, and replacing the modulus operation mod with a first modulus operation mod1 or a second modulus operation mod2 according to the modulus; when the selected modulus is the Mersen number M-2ⁿ-1, or when the modulus in the algorithm is constructed to be exactly the meisen number, replacing the modulo operation mod with a first modulo operation mod1, where n is a positive integer;

when the modulus of the selected or constructed structure is similar to the Meisen numberPositive integer of (2)ⁿL, the modulo operation mod is replaced with a second modulo operation mod 2.

Example 1

A key exchange or public key encryption optimization method based on a Messen number comprises the following combination of implementation modes:

in the key exchange or the public key cryptography-related calculation, the Elgamal algorithm is selected and may be selected as the DHM algorithm.

In the Elgamal algorithm used, a Messen prime number M2 is selectedⁿ-1 as modulus of a modulo operation mod, where n is a positive integer and enables M to be prime, e.g. n 1279;

in the corresponding modular addition, modular multiplication and modular exponentiation processes, the original modular operation mod is replaced by a specific first modular operation mod1 without division, wherein the first modular operation mod1 is expressed as follows:

die addition: y + a mod 1M + a + B mod (2)ⁿ-1)，

Modular multiplication: y ═ a × B mod 1M ═ a × B mod (2)ⁿ-1)，

Modular exponentiation: y is A^B mod1 M＝A^B mod(2ⁿ-1), and the modular exponentiation is essentially split into iterations of modular multiplication operations of a multi-round loop, so only the first modulo operation mod1 implementation of the modular addition, modular multiplication operations need to be considered;

the first modulo operation mod1 is implemented such that the division becomes an addition according to a specific calculation procedure as follows (as shown in fig. 1):

step S101, taking an n-bit positive integer A, n bit positive integer B;

step S102, judging whether the operation is modular addition operation or modular multiplication operation, and respectively turning to step S103 and step S104;

step S103, calculating addition result Y before modulus₀Go to step S105;

step S104, calculating multiplication result Y before modulus₀＝A*B；

Step S105, processing Y₀Splitting into lower n bits (Y)₁) High n-position (Y)₂) Two parts;

step S106, calculating Y ═ Y₁+Y₂；

Step S107, determining whether Y is equal to M, and if not, going to step S109;

step S108, carrying out overflow condition processing, and enabling Y to be 0;

step S109, the process ends, and Y is the result of mod1 operation.

Example 2

The system for realizing the key exchange or public key encryption optimization method based on the Messen number comprises one or more than one fast modular arithmetic logic circuit component C1, and can support a first modular arithmetic mod 1;

the logic circuit assembly C1 includes the following components (shown in fig. 3):

an n-bit register RegA (301) for temporarily storing an input number a;

an n-bit register RegB (302) for temporarily storing an input number B;

an n-bit adder ADD1(303) for adding two numbers and outputting an n-bit integer and a carry flag C;

an n-bit multiplier MUL (304) for multiplying two numbers and outputting a 2 n-bit integer;

a 2 n-bit register RegY0(305) for temporarily storing intermediate data;

an n-bit adder ADD2(306) for performing fast modulo computation and outputting an n-bit integer and carry flag C;

the logic gate circuit comprises n AND gates (308) and 1 NOT gate (307);

an n-bit register RegY (309) for temporarily storing the output number Y.

Example 3

A key exchange or public key encryption optimization method based on a Messen number comprises the following combination of implementation modes:

in the key exchange or public key cryptography calculation, the RSA algorithm is selected and adopted in the embodiment;

in the RSA algorithm used, the product K of two prime numbers is constructed, and exactly K2ⁿL as the modulus of the modulo operation mod, where n is oneA positive integer, L is a very small positive integer, L<2⁶＝64；

In the corresponding modular addition, modular multiplication and modular exponentiation processes, the original modular operation mod is replaced by a specific second modular operation mod2 of fast modular operation without division, wherein the second modular operation mod2 is expressed as follows:

die addition: y + a mod 2K + a + B mod (2)ⁿ-L)，

Modular multiplication: y ═ a × B mod 2K ═ a × B mod (2)ⁿ-L)，

Modular exponentiation: y is A^B mod2 K＝A^B mod(2ⁿL) and the modular exponentiation is essentially split into iterations of modular multiplication operations in a multi-round loop, so only mod2 implementations of both modular addition and modular multiplication operations need to be considered;

the second modulo operation mod2 is implemented by converting the division into addition and multiplication according to a specific calculation flow, which is as follows (as shown in fig. 2):

step S201, taking an n-bit positive integer A, n bit positive integer B and a 6-bit positive integer L;

step S202, judging whether the operation is modular addition operation or modular multiplication operation, and respectively turning to steps S203 and S204;

step S203, calculating addition result Y before modulus₀Go to step S205;

step S204, calculating multiplication result Y before modulus₀＝A*B；

Step S205, processing Y₀Splitting into lower n bits (Y)₁) High n-position (Y)₂) Two parts;

step S206, calculating Y ═ Y₁+Y₂*L；

Step S207, if Y < K, go to step S209;

step S208, processing overflow condition, in pure software implementation, making Y₀Y-K, and in a hardware implementation, let Y₀＝Y+L-2ⁿThen go to step S205;

step S209 ends the process, and Y is the result of mod2 operation.

A system based on a Messen number key exchange or public key cryptography encryption optimization method comprises one or more fast modular arithmetic logic circuit components C2, and can support a second modular arithmetic mod 2;

the logic circuit assembly C2 includes the following components (shown in fig. 4):

an n-bit register RegA (401) for temporarily storing an input number a;

an n-bit register RegB (402) for temporarily storing an input number B;

an n-bit adder ADD1(403) for adding two numbers and outputting an n-bit integer and a carry flag C;

an n-bit multiplier MUL1(404) for multiplying two numbers and outputting a 2 n-bit integer;

a 2 n-bit register RegY0(405) for temporarily storing intermediate data;

an L-bit register RegL (406) for temporarily storing an input number L;

an n-bit multiplier MUL2(407) for calculating a correction value in the modulo calculation;

an n + 6-bit adder ADD2(408) for performing fast modulo calculation, outputting an n + 6-bit integer and a carry flag C (n.. n +5), i.e., if the n-th to n + 5-th bits output all 0's and there is no higher carry, C (n.. n +5) is 0, otherwise C (n.. n +5) is 1;

a logic gate circuit having 1 NOT gate (410);

an n +6 bit demultiplexer DMUX (409), either one of which is output;

an n-bit register RegY (411) for temporarily storing the output number Y;

the n-bit adder ADD3(412) is used for overflow processing of the lower n bits.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims (10)

1. A key exchange or public key encryption optimization method based on the Messen number is characterized in that,the method comprises the following steps: in the application scene of key exchange or public key cryptography calculation, selecting or constructing a modulus of a modulus operation mod, and replacing the modulus operation mod with a first modulus operation mod1 or a second modulus operation mod2 according to the modulus; when the selected modulus is the Mersen number M-2ⁿ-1, or replacing the modulo operation mod with a first modulo operation mod1, where n is a positive integer, when the modulus in the algorithm is constructed to be exactly the meisen number;

when the modulus of the selected or constructed structure is a positive integer K-2 similar to the Mersen numberⁿL, the modulo operation mod is replaced with a second modulo operation mod 2.

2. The metson-based key exchange or public key cryptography optimization method of claim 1, wherein the application scenarios include using discrete logarithm puzzle-based algorithms, prime factorization puzzle-based algorithms, discrete elliptic curve puzzle-based algorithms, and other algorithms with modular addition, modular multiplication, and modular exponentiation as main operands.

3. The metson-based key exchange or public key cryptographic optimization method of claim 1, wherein the first modulo operation mod1 is a fast modulo operation without division.

4. The metson-based key exchange or public key cryptographic optimization method of claim 1, wherein the first modulo operation mod1 is as follows:

let M be the Messen number, i.e. M2ⁿ1, where n is a positive integer, the result of the first modulo operation mod1 is the same as the original modulo operation mod:

die addition: y + a mod 1M + a + B mod (2)ⁿ-1), wherein a, B represent two addends of a modulo addition operation;

modular multiplication: y ═ a × B mod 1M ═ a × B mod (2)ⁿ-1), wherein a, B represent two multipliers of a modular multiplication operation;

modular exponentiation: y is A^B mod1 M＝A^B mod(2ⁿ-1)，Where A represents the base of the modular exponentiation and B represents the exponent of the modular exponentiation.

5. The metson-based key exchange or public key cryptography optimization method of claim 1, wherein the operation flow of the first modulo operation mod1 comprises the following steps:

s101, taking an n-bit positive integer A and an n-bit positive integer B;

step S102, judging whether the operation is modular addition operation or modular multiplication operation, and respectively turning to the steps S103 and S104;

step S103, calculating addition result Y before modulus₀Go to step S105;

step S104, calculating multiplication result Y before modulus₀＝A*B；

Step S105, processing Y₀Splitting into lower n-bits Y₁High n-position Y₂；

Step S106, calculating Y ═ Y₁+Y₂；

Step S107, judging whether Y is equal to M, if not, turning to step S109, wherein the modulus M is a Mersen number;

step S108, carrying out overflow condition processing, and enabling Y to be 0;

step S109, the process ends, and Y is the result of mod1 operation.

6. The metson-based key exchange or public key cryptographic optimization method of claim 1, wherein the second modulo operation mod2 is a fast modulo operation without division.

7. The metson-based key exchange or public key cryptographic optimization method of claim 1, wherein the second modulo operation mod2 is as follows:

modulus is positive integer K ═ 2ⁿ-L, where n is a positive integer and L is a positive integer, taking L<2⁶The second modulo operation mod2 has no division:

die addition: y + a mod 2K + a + B mod (2)ⁿ-L), wherein a, B represent two addends of a modulo addition operation;

modular multiplication: y ═ a × B mod 2K ═ a × B mod (2)ⁿ-L), where a, B represent two multipliers of a modular multiplication operation;

modular exponentiation: y is A^B mod2 K＝A^B mod(2ⁿ-L), where a represents the base of the modular exponentiation and B represents the exponent of the modular exponentiation.

8. The method for optimizing the key exchange or the public key cryptography encryption based on the Meisen number according to any one of claims 1 to 7, wherein the operation flow of the second modulo operation mod2 comprises the following steps:

step S201, taking an n-bit positive integer A, n bit positive integer B and a 6-bit positive integer L;

step S202, judging whether the operation is modular addition operation or modular multiplication operation, and respectively turning to step S203 and step S204;

step S203, calculating addition result Y before modulus₀Go to step S205;

step S204, calculating multiplication result Y before modulus₀＝A*B；

Step S205, processing Y₀Splitting into lower n-bits Y₁High n-position Y₂；

Step S206, calculating Y ═ Y₁+Y₂*L；

Step S207, if Y is less than K, then go to step S209, wherein the modulus K is a positive integer with a shape similar to the Mersen number;

step S208, processing the overflow condition, and making Y₀Y-K, and in a hardware implementation, let Y₀＝Y+L-2ⁿThen go to step S205;

in step S209, the flow ends, and Y is the result of mod2 operation.

9. A system for implementing the metson number based key exchange or public key cryptography optimization method of claim 1, characterized in that: comprises one or more fast modulo arithmetic logic circuit components C1 capable of supporting the first modulo operation mod 1; the fast modulo arithmetic logic circuit component C1 includes:

the n-bit register RegA is used for temporarily storing the input number A;

the n-bit register RegB is used for temporarily storing the input number B;

an n-bit adder ADD1 for adding two numbers and outputting n-bit integer and carry flag C;

an n-bit multiplier MUL for multiplying two numbers and outputting a 2 n-bit integer;

a 2 n-bit register RegY0 for temporarily storing intermediate data;

the n-bit adder ADD2 is used for finishing the fast modular computation and outputting an n-bit integer and a carry flag C;

the logic gate circuit comprises n AND gates and 1 NOT gate;

an n-bit register RegY for temporarily storing the output number Y;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit adder ADD 1;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit multiplier MUL;

the adder ADD1 outputs to bits 0 to n-1 of the register RegY0, and the carry flag C outputs to bit n of RegY 0;

the multiplier MUL outputs to bits 0 to 2n-1 of the register RegY 0;

the low n bits and the high n bits of the register RegY0 are respectively output to two input ends of an n-bit adder ADD 2;

the adder ADD2 outputs to one input end of n AND gates, the carry flag C outputs to 1 NOT gate, and the NOT gate outputs to the other input end of n AND gates;

the n AND gates output to bits 0 to n-1 of register RegY.

10. A system for implementing the metson number based key exchange or public key cryptography optimization method of claim 1, characterized in that: comprises one or more fast modulo arithmetic logic circuit components C2 capable of supporting the second modulo operation mod 2; the fast modulo arithmetic logic circuit component C2 includes:

the n-bit register RegA is used for temporarily storing the input number A;

the n-bit register RegB is used for temporarily storing the input number B;

an n-bit adder ADD1 for adding two numbers and outputting n-bit integer and carry flag C;

an n-bit multiplier MUL1 for multiplying two numbers and outputting 2 n-bit integer;

a 2 n-bit register RegY0 for temporarily storing intermediate data;

an L-bit register RegL for temporarily storing an input number L;

an n-bit multiplier MUL2 for calculating a correction value in the modulo calculation;

an n + 6-bit adder ADD2, configured to complete fast modulo computation, and output an n + 6-bit integer and a carry flag C (n.. n +5), that is, if the n-th to n + 5-th bits output all 0's and there is no higher carry, C (n.. n +5) is 0, otherwise C (n.. n +5) is 1;

a logic gate circuit having 1 NOT gate;

an n +6 bit demultiplexer DMUX, one of two outputs;

an n-bit register RegY for temporarily storing the output number Y;

an n-bit adder ADD3 for performing overflow processing of low n bits;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit adder ADD 1;

the bits 0 to n-1 of the registers RegA and RegB are respectively output to two input ends of an n-bit multiplier MUL 1;

the adder ADD1 outputs to bits 0 to n-1 of the register RegY0, and the carry flag C outputs to bit n of RegY 0;

the multiplier MUL1 outputs to bits 0 to 2n-1 of register RegY 0;

the lower n bits of the register RegY0 are output to the lower n bits of one input end of the n + 6-bit adder ADD 2;

the high n bits of the register RegY0 are output to one input of an n-bit multiplier MUL 2;

the register RegL outputs the lower 6 bits to the other input of the n-bit multiplier MUL 2;

the multiplier MUL2 outputs to the other input terminal of the n + 6-bit adder ADD 2;

the adder ADD2 outputs to the n + 6-bit demultiplexer DMUX, the flag bit C (n.. n +5) outputs to 1 NOT gate, and the NOT gate outputs to the alternative selection end of the demultiplexer DMUX;

when the selection end inputs 0, the low n bits of one path in the demultiplexer DMUX are output to one input end of the adder ADD3, the n th to n +5 th bits of the same path are output to the n th to n +5 th bits of the register RegY0, and when the selection end inputs 1, the low n bits of the other path are output to the 0 th to n-1 bits of the register RegY;

the register RegL outputs bits 0 to 5 to the other input terminal of the adder ADD 3;

the adder ADD3 outputs to bits 0 through n-1 of the register RegY 0.

Images