CN114403883A - Circuit for neural interface - Google Patents

Circuit for neural interface Download PDF

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Publication number
CN114403883A
CN114403883A CN202210023147.7A CN202210023147A CN114403883A CN 114403883 A CN114403883 A CN 114403883A CN 202210023147 A CN202210023147 A CN 202210023147A CN 114403883 A CN114403883 A CN 114403883A
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Prior art keywords
circuit
chip
acquisition circuit
output
data processing
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CN202210023147.7A
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Chinese (zh)
Inventor
黄立
黄晟
李凯
李谋涛
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Wuhan Zhonghua Brain Computer Integration Technology Development Co Ltd
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Wuhan Zhonghua Brain Computer Integration Technology Development Co Ltd
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Priority to CN202210023147.7A priority Critical patent/CN114403883A/en
Publication of CN114403883A publication Critical patent/CN114403883A/en
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    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61BDIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00Measuring for diagnostic purposes; Identification of persons
    • A61B5/24Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/25Bioelectric electrodes therefor
    • A61B5/279Bioelectric electrodes therefor specially adapted for particular uses
    • A61B5/291Bioelectric electrodes therefor specially adapted for particular uses for electroencephalography [EEG]
    • A61B5/293Invasive
    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61BDIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00Measuring for diagnostic purposes; Identification of persons
    • A61B5/24Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/25Bioelectric electrodes therefor
    • A61B5/262Needle electrodes
    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61BDIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00Measuring for diagnostic purposes; Identification of persons
    • A61B5/24Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30Input circuits therefor
    • A61B5/304Switching circuits
    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61BDIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00Measuring for diagnostic purposes; Identification of persons
    • A61B5/24Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30Input circuits therefor
    • A61B5/307Input circuits therefor specially adapted for particular uses
    • A61B5/31Input circuits therefor specially adapted for particular uses for electroencephalography [EEG]

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  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Medical Informatics (AREA)
  • Biophysics (AREA)
  • Pathology (AREA)
  • Engineering & Computer Science (AREA)
  • Biomedical Technology (AREA)
  • Heart & Thoracic Surgery (AREA)
  • Physics & Mathematics (AREA)
  • Molecular Biology (AREA)
  • Surgery (AREA)
  • Animal Behavior & Ethology (AREA)
  • General Health & Medical Sciences (AREA)
  • Public Health (AREA)
  • Veterinary Medicine (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)

Abstract

The invention relates to a circuit for a neural interface, comprising: the micro-needle comprises at least one acquisition circuit chip and a data processing chip, wherein the acquisition circuit chip comprises a welding spot and a reading circuit which are connected with the micro-needle body, the welding spot on the acquisition circuit chip is connected with the reading circuit, and the reading circuit is connected with the data processing chip. The invention electrically connects at least one acquisition circuit chip and a data processing chip, acquires nerve signals through the acquisition circuit chip, and converges and processes the nerve signals through the data processing chip, so that the nerve signals can be recorded through a multi-electrode contact, and the spatial resolution and the signal accuracy are improved; meanwhile, the acquisition circuit chip is combined with the data processing chip, so that the input and output functions of signals can be realized, and the problem that the existing invasive micro-needle can only realize a single brain wave signal acquisition function is effectively solved.

Description

Circuit for neural interface
Technical Field
The invention belongs to the field of neural interfaces, and particularly relates to a circuit for a neural interface.
Background
The nerve interface provides a channel for connecting the nerve cell with an external device, and can stimulate the nerve cell to generate action potential through the external device and record the action potential generated by the nerve cell so as to realize the bidirectional communication between the nerve cell and the external device. Therefore, neural interfaces are widely used in research and treatment of various neurological diseases, such as parkinson's disease, epilepsy, depression, essential tremor, and the like.
The neural interface device is mainly divided into an implanted type and a non-implanted type, and compared with a non-implanted type neural electrode, the implanted type neural electrode is focused by scholars at home and abroad due to high resolution. The silicon-based tube micro-needle type neural interface device with the traditional structure can only realize extraction of electroencephalogram signals, has single function and fewer electrode recording points, and cannot meet the current clinical requirements.
And for a large array neural interface circuit, especially when applied to an electrode array of thousands to tens of thousands of points, signal output connection and signal processing of dense electrodes become one of the main factors restricting the array scale, in an electrode array of tens of to hundreds of micrometers, thousands of signal lines need to be communicated and connected to a processing circuit, the workload is large, the circuits are disordered, the connection is easy to make mistakes, the production efficiency is low, and the like.
Disclosure of Invention
The present invention is directed to a circuit for a neural interface that addresses at least some of the deficiencies of the prior art.
The technical scheme of the invention is realized as follows: there is provided a circuit for a neural interface, comprising: at least one acquisition circuit chip and a data processing chip, wherein the acquisition circuit chip comprises a welding spot and a reading circuit which are connected with the micro needle body,
the welding spot on the acquisition circuit chip is connected with the reading circuit, and the reading circuit is connected with the data processing chip.
As an optional first embodiment, the number of the acquisition circuit chips is multiple, and the multiple acquisition circuit chips are stacked.
As an alternative embodiment, each acquisition circuit chip is electrically connected to the data processing chip through a through hole contact.
As a first optional embodiment, the circuit further includes an output unit, where the output unit includes at least one output channel, and the output channel includes a first switch, and the first switch is selectively turned on to enable the output channel to output a corresponding neural signal.
As an optional first embodiment, the circuit further includes a control unit, and the first switch is connected to the control unit, and the control unit controls the first switch to be turned on or turned off.
As an alternative embodiment, the output unit includes a data conversion unit, and the data conversion unit is configured to perform parallel-to-serial conversion on the neural signal.
As a first optional embodiment, the readout circuit includes at least one sampling unit, and the sampling unit includes at least one sampling channel, and the sampling channel is connected to the corresponding output channel.
As an optional first embodiment, the circuit further includes an AD conversion module, an input end of the AD conversion module is connected to an output end of the sampling channel, and an output end of the AD conversion module is connected to an input end of the output unit.
As an alternative first embodiment, the sampling channel includes a second switch, and the second switch is selectively turned on to enable the sampling channel to acquire the corresponding neural signal.
As an alternative first embodiment, the second switch is connected to the control unit, and the control unit controls the second switch to be turned on or off.
The invention has at least the following beneficial effects: the at least one acquisition circuit chip is electrically connected with the data processing chip, the acquisition circuit chip acquires nerve signals, the data processing chip collects and processes the nerve signals, the nerve signals can be recorded through the multi-electrode contact, and the spatial resolution and the signal accuracy are improved; meanwhile, the acquisition circuit chip is combined with the data processing chip, so that the input and output functions of signals can be realized, and the problem that the existing invasive micro-needle can only realize a single brain wave signal acquisition function is effectively solved.
Furthermore, the TSV technology is adopted to realize the electric connection among the micro pin body, the acquisition circuit chip and the data processing chip, so that connecting wires are reduced, the connection is more reliable, and the production efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a microneedle according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a circuit for a neural interface according to one embodiment of the present invention;
fig. 3 is a schematic diagram of an output unit according to an embodiment of the invention.
In the attached figure, 1 is a micro needle body, 2 is a body electrode, 3 is an electrode point, and 4 is an acquisition circuit chip.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, the meaning of "plurality" or "a plurality" is two or more unless otherwise specified.
The first embodiment is as follows:
the present embodiments provide a circuit for a neural interface, comprising: the micro-needle comprises at least one acquisition circuit chip and a data processing chip, wherein the acquisition circuit chip comprises a welding spot and a reading circuit which are connected with the micro-needle body, the welding spot on the acquisition circuit chip is connected with the reading circuit, and the reading circuit is connected with the data processing chip.
The number of the acquisition circuit chips is multiple, and the acquisition circuit chips are stacked. Specifically, the sampling unit sets up on the micro needle body, and a plurality of micro needle body stack sets up, and that is, the micro needle body is as bearing the carrier, will be a plurality of the sampling unit stacks up the setting together, forms the neural interface circuit of big array for gather thousands to several tens of thousands neural signal.
In this embodiment, each acquisition circuit chip is electrically connected to the data processing chip through a through-hole contact. The through hole contact can be a connecting through hole, and the connecting through hole is cylindrical, truncated cone-shaped or square. The connection via may be a TSV via.
At least one seed layer is arranged on the inner wall of the connecting through hole, and the seed layer is made of titanium or copper. The surface of the seed layer is provided with a filling layer, and the filling layer is made of conductive metal filled with conductive metal. Wherein the conductive metal comprises copper, tungsten, nickel, tin, or gold.
In this embodiment, the electrical connection between the acquisition circuit chip and the data processing chip is realized based on the TSV interconnection technology, the connection reliability is high, the accuracy and reliability of signal acquisition and transmission can be improved, meanwhile, the connection scheme based on the TSV interconnection technology can better meet the requirement for extension of microneedles, the accuracy, comprehensiveness and effectiveness of signal acquisition are improved, and clinical application is facilitated.
In this embodiment, the circuit further includes an output unit, where the output unit includes at least one output channel, and the output channel includes a first switch, and the first switch is selectively turned on to enable the output channel to output a corresponding neural signal. The circuit further comprises a control unit, wherein the first switch is connected with the control unit, and the control unit controls the first switch to be switched on or switched off. The control unit may be disposed on the data processing chip, the acquisition circuit chip, or independently from the data processing chip and the acquisition circuit chip, which is not limited herein.
Further, the output unit includes a data conversion unit for performing parallel-to-serial conversion on the neural signal to convert low-speed parallel data into high-speed serial data. The readout circuit comprises at least one sampling unit, the sampling unit comprises at least one sampling channel, and the sampling channel is connected with the corresponding output channel. Wherein the sampling channel includes a second switch that is selectively turned on to cause the sampling channel to acquire a corresponding neural signal. The second switch is connected with the control unit, and the control unit controls the second switch to be switched on or switched off.
In this embodiment, the circuit further includes an AD conversion module, an input end of the AD conversion module is connected to an output end of the sampling channel, and an output end of the AD conversion module is connected to an input end of the output unit.
Example two:
referring to fig. 1 and 2, an embodiment of the present invention discloses a circuit for a neural interface, including at least one acquisition circuit chip 4 and a data processing chip, where the acquisition circuit chip 4 includes a solder joint and a readout circuit connected to a micro-needle body 1, each micro-needle body includes a base and a plurality of body electrodes 2 (i.e., electrode body electrodes) disposed on the base, each body electrode is provided with an electrode point 3 (or electrode contact), each acquisition circuit chip is provided with a plurality of solder joints, the plurality of solder joints of each acquisition circuit chip are respectively electrically connected to the plurality of electrode points of the micro-needle body in a one-to-one correspondence manner, and the plurality of acquisition circuit chips are respectively electrically connected to the data processing chip.
As one embodiment, the bases of the plurality of micro-needles and the plurality of acquisition circuit chips are fixedly connected together to form an integrated micro-needle. The base of the micro needle body and the acquisition circuit chip can be fixedly connected in a welding mode. Wherein, the base of the micro needle body and the body electrode are integrally formed.
As one embodiment, the data processing chip, the bases of the micro-needle bodies and the acquisition circuit chips are fixedly connected together to form an integrated electrode array structure; and after being attached to the data processing chip, each acquisition circuit chip is electrically connected with the data processing chip through a TSV (through silicon via) technology. The data processing chip, the acquisition circuit chip and the base of the micro needle body can be fixedly connected in a welding mode. The data processing chip can be fixed at the bottom or the side wall of the microneedle according to the requirement to form an integrated microneedle array structure.
As one embodiment, one micro needle body corresponds to at least one acquisition circuit chip, the acquisition circuit chip is fixed on the side wall of the base corresponding to the micro needle body, and the acquisition circuit chip is attached to the base corresponding to the micro needle body and then is electrically connected through a TSV technology; the electrode points of each micro needle body are respectively and correspondingly electrically connected with the welding points of the corresponding acquisition circuit chip. Preferably, one micro needle body corresponds to one acquisition circuit chip. The multiple body electrodes of each micro needle body are arranged on the base at intervals along a straight line to form a row of body electrodes. Referring to fig. 3, the body electrode is erected on the upper end surface of the base.
A plurality of micro needle bodies, namely a plurality of rows of body electrodes, are arranged at intervals, an acquisition circuit chip is fixed in the interval between two adjacent micro needle bodies, and the two sides of the acquisition circuit chip are respectively and fixedly connected with the bases of the micro needle bodies on the two sides of the acquisition circuit chip. When there are m rows of body electrodes, each row of body electrodes has a branch body electrodes, and each body electrode has b electrode points, a three-dimensional electrode body electrode array of m a b can be formed.
For example, the three-dimensional brain electrode body electrode array of 32 × 64, the number of electrode needles is 32 × 32, the number of single-needle electrode points is 64, the invention divides the body electrode array into 32 rows of body electrodes, each row of body electrodes has 32 body electrodes, the electrode point on each body electrode can be connected to the welding point of each row of needle bases through a connecting wire, thus 32 micro needle bodies with base welding points are shared, and 32 identical reading circuits with welding points and acquisition circuit chips are designed, thus 32 micro needle bodies and 32 acquisition circuit chips can be connected together by inverse welding to form an integrated body electrode array structure. At the moment, 32 same acquisition circuit chips of a common processing function circuit module for integrating nerve electrical signal acquisition, amplification filtering, gating and the like are required to be designed, a data processing chip for integrating signal integral processing and parallel-serial conversion output is simultaneously designed, the 32 acquisition circuit chips and the data processing chip are interconnected through a TSV technology, the acquisition circuit chips transmit signals acquired from electrodes to the data processing chip through TSV through holes shown in the figure after filtering, amplification and the like, and meanwhile, the acquisition circuit chips can receive control and gating signals sent from the data processing chip, so that a multi-layer IC communication unified working mode is realized.
As one embodiment, the electrode point on each body electrode is connected to the corresponding welding point of the corresponding base through a lead; one or more electrode points are provided on each bulk electrode.
As one embodiment, each readout circuit on the acquisition circuit chip 4 is provided with at least one sampling channel, each sampling channel is connected in series with a second switch, the input end of each sampling channel is connected with the welding point in a one-to-one correspondence manner, the output end of each sampling channel is connected with the input end of the output unit, and the control end of the second switch is electrically connected with the control unit. The second switch of the present invention may adopt a multiplexer MUX, or of course, may adopt a relay, etc.
If the single-point sampling frequency of the nerve electrode is designed to be 20K Hz, n welding spots of each acquisition circuit chip are filtered and amplified after acquiring a nerve electric signal, a plurality of second switches S1-Sn of each acquisition circuit chip are sequentially gated for sampling, the sampling frequency is 20KHz, and the signals obtained by sampling are subjected to AD conversion to obtain final digital data, namely the sampling process of one acquisition circuit chip. The invention adopts the sampling scheme to solve the technical problems of overhigh sampling speed, high design difficulty and easy signal distortion when the traditional scheme is applied to an electrode array with tens of thousands of points. The m acquisition circuit chips work repeatedly at the same time, and digital data of the full array electrode can be obtained. The m groups of data are subjected to parallel-serial conversion through digital processing, and digital data of all the electrodes can be output.
As one embodiment, the sampling unit includes a sampling capacitor, an output end of the sampling channel is connected to one end of the sampling capacitor, and the other end of the sampling capacitor is grounded;
the sampling unit further comprises an operational amplifier, and the output end of the sampling channel is respectively connected with one end of the sampling capacitor and the non-inverting input end of the operational amplifier; the inverting input end of the operational amplifier is connected with the output end of the operational amplifier; and the output end of the operational amplifier is connected with the AD conversion module. The circuit of the sampling unit of the present invention is not limited to the above-mentioned embodiments, and all sampling circuits satisfying the sampling requirement of the present invention can be used in the present invention.
Furthermore, each sampling channel is also provided with a signal processing unit, and the signal processing unit and the second switch of each sampling channel are connected in series. The signal processing unit of the present embodiment is located in front of the gate switch. Of course, the signal processing unit may also be placed behind the gating switch.
Further, the signal processing unit comprises a filter circuit and an amplifying circuit, and the filter circuit is connected with the amplifying circuit in series. The filter circuit of the present embodiment is located in front of the amplifier circuit. Of course, the filter circuit may be placed after the amplifier circuit.
Furthermore, the circuit also comprises an AD conversion module, the output end of each acquisition circuit chip is connected with the input end of the AD conversion module, and the output end of the AD conversion module is connected with the control unit. The control unit of the present invention may be an MCU, but is not limited to an MCU.
Example three:
the difference between this embodiment and the first embodiment is: the data processing chip of this embodiment is further provided with an output unit, referring to fig. 3, where the output unit includes a parallel-to-serial conversion module and a plurality of output channels, and input ends of the plurality of output channels are connected with a plurality of output ends of the AD conversion module in a one-to-one correspondence manner, so as to implement the one-to-one correspondence between the plurality of output channels and outputs of the plurality of acquisition circuit chips;
the output ends of the plurality of output channels are connected with the input end of the parallel-serial conversion module, and the output end of the parallel-serial conversion module is connected with the control unit;
each output channel is connected with a first switch in series, the first switch is connected with the control unit, and the control unit controls the on or off of the first switch. The first switch of the present invention may adopt a multiplexer MUX, or of course, may adopt a relay, etc.
Aiming at a large array of thousands to tens of thousands of nerve electrodes, the circuit can be divided into m groups corresponding to m acquisition circuit chips, when sampling is carried out, each electrode acquires a nerve electrical signal, a gating switch S1-Sn of each acquisition circuit chip is controlled to gate in sequence, sampling is carried out through a sampling unit, and finally digital data are obtained by AD conversion of signals obtained by sampling; the m acquisition circuit chips work simultaneously and output m groups of data; by controlling the on-off state of the first switch of each output channel, the selectable switchable output of each group of data is realized, and the parallel-serial conversion module is used for performing parallel-serial conversion on the output data, so that the reduction of the data output rate can be realized, and the overall power consumption is reduced.
Example four:
compared with the scheme that each sampling channel of each acquisition circuit chip is connected with a signal processing unit in series in the first embodiment, each acquisition circuit chip of the first embodiment is only provided with one signal processing unit, and the specific scheme can be as follows:
each acquisition circuit chip also comprises a signal processing unit, the signal processing unit is positioned between the output end of the sampling channel and the sampling unit, and the signal processing unit is connected with the sampling unit in series. For other technical features of this embodiment, reference is made to embodiment one, and details are not described herein.
The circuit for neural interface of the present invention can be used in fields including, but not limited to, cranial nerves, optic nerves, and motor nerves.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A circuit for a neural interface, comprising: at least one acquisition circuit chip and a data processing chip, wherein the acquisition circuit chip comprises a welding spot and a reading circuit which are connected with the micro needle body,
the welding spot on the acquisition circuit chip is connected with the reading circuit, and the reading circuit is connected with the data processing chip.
2. The circuit of claim 1, wherein the number of the acquisition circuit chips is plural, and the plural acquisition circuit chips are stacked.
3. The circuit of claim 1, wherein each acquisition circuit chip is electrically connected to the data processing chip by via contacts.
4. The circuit of claim 1, further comprising an output unit comprising at least one output channel comprising a first switch that is selectively turned on to cause the output channel to output a corresponding neural signal.
5. The circuit of claim 4, further comprising a control unit, wherein the first switch is connected to the control unit, and wherein the control unit controls the first switch to be turned on or off.
6. The circuit of claim 4, wherein the output unit comprises a data conversion unit to parallel-to-serial convert the neural signal.
7. The circuit of claim 4, wherein the readout circuit comprises at least one sampling cell comprising at least one sampling channel, the sampling channel connected to a respective one of the output channels.
8. The circuit of claim 7, further comprising an AD conversion module having an input connected to the output of the sampling channel and an output connected to the input of the output unit.
9. The circuit of claim 7, wherein the sampling channel includes a second switch that is selectively conductive to cause the sampling channel to acquire a corresponding neural signal.
10. The circuit of claim 9, wherein the second switch is connected to the control unit, and the control unit controls the second switch to be turned on or off.
CN202210023147.7A 2022-01-10 2022-01-10 Circuit for neural interface Pending CN114403883A (en)

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Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070167815A1 (en) * 2005-12-12 2007-07-19 Sarcos Investments Lc Multi-element probe array
JP2008188123A (en) * 2007-02-01 2008-08-21 National Cardiovascular Center Nerve signal probe, nerve signal output device, nerve signal recorder, nerve stimulator, and nerve signal input/output device
CN101248994A (en) * 2007-10-10 2008-08-27 天津大学 Active neuro micro-electrode
US20090240314A1 (en) * 2008-03-24 2009-09-24 Kong K C Implantable electrode lead system with a three dimensional arrangement and method of making the same
CN103732284A (en) * 2011-03-17 2014-04-16 布朗大学 Implantable wireless neural device
CN203138474U (en) * 2013-01-30 2013-08-21 北京蓬阳丰业医疗设备有限公司 18-lead ECG (electrocardiograph) workstation
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CN109893132A (en) * 2019-04-08 2019-06-18 上海大学 A kind of Surface Electromyography Signal Acquisition System

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