CN114384405A - Multi-rate sampling rate frequency-adjustable measurement ASIC chip - Google Patents

Abstract

The invention discloses a multi-rate adjustable sampling rate frequency measurement ASIC chip, comprising: the period counting module is used for synchronizing an analog oscillation signal F of the silicon micro-resonance accelerometer to be tested to a reference clock clk provided by a crystal oscillator, counting the synchronized analog oscillation signal by using the reference clock and outputting a count value N; the nonlinear compensation module is used for converting the count value N into a fixed point number M which is in direct proportion to the square of the frequency, aligning the fixed point number M with the input oscillation signal F and then outputting an aligned fixed point number Dout; the arbitrary sampling rate adjusting module is used for adjusting the sampling rate of the output fixed point number Dout and realizing the output final fixed point value Dout3 with arbitrary sampling rate; and the digital interface module is used for communicating with the upper computer and comprises a configuration register and outputs data to the upper computer. The invention can realize the digitalized output of the silicon micro-resonance accelerometer and solve the problem of nonlinear output of the silicon micro-resonance accelerometer.

Description

Multi-rate sampling rate frequency-adjustable measurement ASIC chip

Technical Field

The invention relates to the field of digital signal processing and hardware programming, in particular to a measurement ASIC (application Specific Integrated circuit) chip with multi-rate and adjustable sampling rate frequency, which relates to the realization of a frequency measurement algorithm on a special Integrated circuit.

Background

Frequency is one of the most basic physical quantities, and particularly in the fields of electronic technology and digital signal processing, due to the advantages of high anti-interference performance and convenient transmission of frequency signals, sensors using frequency as an output quantity are continuously started in the fields of aerospace, navigation, satellite positioning, reverse guidance systems and the like, and a low-power-consumption and high-precision frequency measurement method becomes a hotspot for research of experts in various countries. The frequency measurement method for the oscillation signal mainly includes a phase-locked loop method, a counting method and a differential method. (1) Korean Samsung electronics in 2000 proposed a frequency measurement circuit based on a phase-locked loop, which utilizes the characteristic that a voltage-controlled oscillator control signal is in direct proportion to frequency to realize frequency identification (Buxian, Shenchen, Meta-capacitive light. method for detecting frequency of a digital phase-locked loop. publication No. CN 1171386C). The phase-locked loop frequency measurement method has the advantages of high sensitivity and high precision, and has the disadvantages that the phase-locked loop is a closed loop system, the phase-locked loop can lose lock when a large-bandwidth signal is tested, and the phase-locked loop frequency measurement has no good stability; (2) a method for realizing frequency measurement based on a differential frequency measurement algorithm (Xia Guoming, Linchen, Shi Qin, DuanLian, Su rock, Ding Heng Gao, a differential frequency measurement system based on a digital signal processor platform, publication No. CN204330882U) is provided by Nanjing university of science and engineering in 2014. The differential frequency measurement method has the advantages of no need of an additional reference clock, strong noise immunity, good stability and larger power consumption, and can not be integrated. (3) Zhejiang university in 2012 proposed a frequency measurement circuit based on a counter (Wang Rui. a multifunctional high-precision digital frequency meter. publication: CN 202362380U). The advantages are simple structure, low power consumption, low matching degree with resonant accelerometer, large output nonlinearity and low precision. In summary, the frequency measurement methods have respective advantages and disadvantages, and are difficult to adapt to the frequency reading requirements of the silicon micro-resonant accelerometer on low power consumption, high precision and large bandwidth.

Disclosure of Invention

The invention aims to provide a measurement ASIC chip with multi-rate and adjustable sampling rate frequency, which has the advantages that the silicon micro-resonance type accelerometer digitalized output has the sigma-delta noise modulation effect, the output sampling rate can be adjusted at will, and the average value of acceleration signals represented by the frequency is free from error.

The technical solution for realizing the purpose of the invention is as follows:

a multi-rate adjustable sample rate frequency measurement ASIC chip, comprising:

the period counting module is used for synchronizing an analog oscillation signal F of the silicon micro-resonance accelerometer to be tested to a reference clock clk provided by a crystal oscillator, outputting a synchronized square wave signal F1, counting the synchronized square wave signal F1 by using the reference clock and outputting a count value N;

the nonlinear compensation module is used for converting the count value N into a fixed point number M which is in direct proportion to the square of the frequency, aligning the fixed point number M with the synchronized square wave signal F1 and outputting an aligned fixed point number Dout;

the arbitrary sampling rate adjusting module is used for adjusting the sampling rate of the output Dout and realizing the output final fixed point value Dout3 of the arbitrary sampling rate;

and the digital interface module is used for communicating with the upper computer and comprises a configuration register and outputs data to the upper computer.

Compared with the prior art, the invention has the following remarkable advantages:

(1) the frequency measurement method has a first-order sigma-delta noise modulation principle, greatly inhibits low-frequency quantization noise in output frequency, and realizes the noise level of 0.1mHz/rtHz within the bandwidth of 0.1 Hz-1 Hz;

(2) through the nonlinear compensation module, the output data is in direct proportion to the square of the frequency, and the mean value of the acceleration signal represented by the frequency is ensured to be free from error;

(3) the sampling rate adjustable module realizes multi-sampling rate output and meets different use scenes;

(4) aiming at the silicon micro-resonance type accelerometer, the ASIC chip is specially and optimally designed, a squarer, a divider and a CIC filter in a circuit are redesigned, the area and the power consumption of the ASIC are reduced, and the 10mW power consumption high-precision output in the area of 1.1mm x 2.6mm is realized.

Drawings

FIG. 1 is a schematic diagram of a multi-rate adjustable sample rate frequency measurement ASIC chip according to the present invention.

FIG. 2 is a schematic diagram of the error in cycle counting.

Fig. 3 is a diagram of a quantization noise model.

Fig. 4(a-b) are amplitude-frequency characteristic curves of noise-shaped power spectral density, respectively.

FIG. 5 is a layout schematic of a multi-rate adjustable sample rate frequency measurement ASIC chip of the present invention.

FIG. 6 is an output frequency noise level of the multi-rate adjustable sample rate frequency measurement ASIC chip of the present invention.

Detailed Description

The invention is further described with reference to the following figures and embodiments.

The multi-rate adjustable sampling rate frequency measurement ASIC chip of the present embodiment has an overall structure as shown in fig. 1, and includes a period counting module, a nonlinear compensation module, an arbitrary sampling rate adjustment module, and a digital interface module, which are sequentially arranged from an input end.

The period counting module comprises a synchronizer unit, a counter unit, a rising edge detector unit, a comparator unit and a subtracter unit;

referring to fig. 2, the analog oscillation signal F of the silicon micro resonant accelerometer is input to the period counting module,

firstly, a synchronizer is used for setting a two-stage register to beat for two beats to synchronize an analog oscillation signal F to a reference clock clk, a synchronized square wave signal F1 is output, the reference clock clk continuously counts through a counter, the count value is cnt, the bit width is set to be 12 bits, the rising edge of the synchronized square wave signal F1 is detected through two registers in a rising edge detector, and the output values are fa and fb, namely

fa＜＝F1，fb＜＝fa

When fa equals 1 and fb equals 0, indicating the detection of a rising edge, the value cnt of the counter at the time of the rising edge, i.e. the value of fb, is saved by two 12-bit wide registers in the subtractor

reg1＜＝cnt，reg2＜＝reg1

The output count value N is output through a subtracter

N＝reg2-reg1

When a rising edge is detected, the signal N is indicated_rdWhen not equal to 1, otherwise, N_rd＝0。

When the synchronizer synchronizes the analog oscillation signal F to the reference clock clk for operation, a quantization error is introduced. According to the principle of fig. 2, it is assumed that the true value of the analog oscillation signal F is R, the quantization input is y, the quantization value is N, and the relationship between the true value and the quantization input is y [ N ] ═ R [ N ] -N [ N-1] + y [ N-1]

The quantization error accumulation model for cycle counting is shown in fig. 3. Assume the error of the quantizer to be e, i.e.

e[n]＝N[n]-y[n]

The transfer formula of the quantization error can be expressed as

N[n]＝R[n]+e[n]-e[n-1]

The error between the quantized output N and the true value R is denoted as Q, and the relationship between Q and the error e of the quantizer at time t is Q [ N ] ═ N-R [ N ] ═ e [ N-1]

Can be expressed as by z-transform

Q(z)＝e(z)(1-z^-1)

In the frequency domain, with e^jωInstead of z, the power spectrum of the modulated quantization noise can be represented as

S_e(w) is the single-sided power spectral density of the quantizer, which can be approximated as white noise, assuming that its peak-to-peak value is a, the power spectral density is approximated as

Noise transfer function 1-z^-1The amplitude-frequency characteristic curve is shown in fig. 4, and it is obvious that the frequency measurement mode has the capability of suppressing noise under low bandwidth. Assuming that the input signal frequency is 20kHz, the standard clock is 10MHz, and the output sampling rate isThe noise level at 0.1Hz was 0.1 mHz/rtHz. Therefore, by designing a period counting module with a sigma-delta noise modulation principle, the low-frequency band quantization noise can be effectively inhibited through multiple quantization averages, and the frequency low-noise output is realized.

The nonlinear compensation module comprises a reciprocal unit, a squaring unit and a delay aligner unit;

according to the relation between the input acceleration and the output frequency of the silicon micro-resonance type accelerometer

Where f is the output frequency, w is the output angular frequency, f_nFor the natural frequency of the resonant beam, l is the length of the mass, h is the thickness of the mass, w_thIs the width of the mass, E is the modulus of elasticity of the mass, m is the mass of the mass, and a is the input acceleration.

According to the above formula, the output frequency and the input acceleration are in a nonlinear relationship, and the nonlinearity causes the offset problem of the output acceleration in the impact vibration environment. The input acceleration and the output frequency square are in a linear relation, so that a nonlinear compensation module is carried out after periodic frequency measurement.

The nonlinear compensation module is used for converting the counting difference value N into a frequency square fixed point number q and aligning the square fixed point number q with the input analog oscillation signal F. The module comprises three subunits of reciprocal, square and delay alignment.

The counting difference N is first input into a reciprocal module, i.e.

Wherein M is₁Denotes the reciprocal multiplying factor, M1 being 2 in this example²⁹The method comprises the following specific steps:

1) the comparator of the period counting module outputs an indication signal N_rdFor judging the difference N of counts at high levelThe highest non-zero bit and amplify it to the original bit width, e.g. N10: 8]When the regN is 001, regN is 2, and the counting difference N is shifted to the left by 2 bits;

2) a dividend B of 12bit width defined as 0x7FF (0x represents a 16-ary system), a reciprocal c of 22bit width, and a counter 2 having a reference clock clk as a count cycle, whose count value cont2 is obtained, and the count difference N is extended to 12bit width, and the fixed value B and the count difference N are compared

B-N＞0

If so, the dividend B is equal to the difference between B and N shifted left by one and incremented by one, the quotient c is equal to c shifted left by one and incremented by one, and the count cont2 is itself incremented by one. Otherwise, the dividend B is equal to B shifted left by one and incremented, the reciprocal c is equal to c shifted left by one, and the count cont2 is itself incremented by one.

Then, judge

cont2＝＝regN+20

If not, continuing to cycle the step 2); if equal, the output reciprocal value c is valid. A counter 3 defining a count period of the reference clock clk, the count value of which is cont3, based on the comparator indication signal N_rdWhen cont3 is high, cont3+1 is set, and when cont3 is 23+ regN, the countdown indicator signal crd is set to high level, so that the synchronicity between the countdown indicator signal crd and the countdown value c is ensured.

The reciprocal value c and reciprocal indicator signal crd are then input to the squaring module, i.e.

Wherein M is_qFor scaling factor, M in this embodiment_q＝2²²The method comprises the following specific steps:

1) at the reciprocal indication signal c_rdDefining the power of the squaring module to be 44bit Q3 when the power is high

Q3＝{22‘b0，c}

Defining a multiplier Q2, Q2 ═ c, defining a count value N;

2) then start to judge

Q2[N]＝1

If so, the multiplier Q2 is shifted left by one, the power Q3 equals Q3 plus Q2, and the count N equals N plus one. Otherwise, the multiplier Q2 is shifted to the left by one, the power Q3 is not changed, the count value N is equal to N plus one, and then the judgment is made

N＝＝22

If not, continuing to circulate the step 2), if equal, outputting the fixed point number of the square value

A counter 4 having a count period of a reference clock clk is defined, a count value thereof is cont4, cont4 is cont4+1 when a count-down instruction signal crd is high, and a square instruction signal qrd is set to a high level when the count value cont4 is 22, so that synchronism between a square instruction signal qrd and the number q of square fixed points is ensured.

Finally, the square indicator qrd and the number of square fixed points q are input to the delay alignment module. The module records the high level of the square indicator qrd through one set of register array 1 with data in 0: 3, and simultaneously saves the corresponding number of square nodes q to another set of register 2 with data 21: 0R 0: 3, i.e.

if(q_rd＝1)in[N]＝q_rd，R[N]＝q

Where N is the location of in [ N ], and R [ N ] in its register array.

Then, a counter 5 having a reference clock clk as a COUNT period is defined, the COUNT value is C, when in [ N ] is 1, the counter starts counting, and when the COUNT value reaches a maximum COUNT value (COUNT may take 1k to 2k), the output is C

Dout＝R[N+1]，in[N]＝0

The output signals Dout and the input oscillation signals F can be in one-to-one correspondence by conversion. The four registers are used for storing data, so that the data are matched with the maximum value COUNT of the counting value C, the frequency value of the input oscillating signal F is 10 kHz-25 kHz, namely each input square wave period corresponds to 400-1000 clk period values, and therefore the program can be continuous and errors cannot occur.

The arbitrary sampling rate adjusting module comprises an integrator, a decimator and a comb. Dout is input into an integrator, and the basic principle of the integrator is to simply accumulate input data, namely firstly, beating one beat through a register, then expanding bit width (till no overflow data is added in subsequent addition), and finally, adding the input and the output of the integrator

Dout1＝Dout1+Dout

Dout1 is input into the decimator, integrator output data Dout1 is counted, and then decimated by M data intervals (M is the sampling rate and is input from the upper computer through the SPI interface). First, a counter 6 modulo M and counting period of a reference clock clk is defined, and its value is cnt, and then an indication signal phase is defined, and when cnt is M-1, a high level is output, and otherwise a low level is output. When the instruction signal phase is high, the post-extraction data Dout2 is output.

Dout1 is input into the comb, the comb takes one beat of data Dout2, and then subtraction is carried out, so that low-pass filtering processing can be achieved, and a final fixed-point value Dout3 is output.

The integrator, the decimator and the comb are connected in series, and are the structure of the CIC filter. The high-frequency noise is filtered and suppressed by the comb; the integrator performs sliding average to reduce quantization error; the decimator performs a running average of the count values synchronized to the standard clock to a suitable output rate. By filtering out the high frequency noise, sampling from the reference clock clk to a specified output rate is achieved. By selecting different sampling rates M, data dout3 with different output rates can be obtained.

The digital interface module is used for realizing communication with an upper computer (such as an MCU) through an SPI interface and is provided with a complete SPI interface and a configuration register. Has SPI standard four-wire interface SS, SCK, DIN and DOUT. The upper computer configures a sampling value M through DOUT, and after the configuration is finished, the address is input through DOUT again, so that DOUT3 can be digitally output from DIN. In the module, a two-stage RAM structure is used, when the SS is pulled up, the first-stage RAM writes data into the second-stage RAM, when the SS is pulled down, the first-stage RAM suspends writing, the second-stage RAM starts to transmit the data to the upper computer, the data are protected, and new data are prevented from being written in when data of one frame are not completely transmitted.

The layout of the frequency measurement ASIC design is shown in FIG. 5, the frequency measurement ASIC chip is subjected to experimental test, an analog oscillation signal F output by the silicon micro resonant accelerometer is collected under the normal-temperature static condition, the time duration is 20min, the noise power spectral density of data output by the frequency measurement ASIC is shown in FIG. 6, the noise presents 20dB/dec slope at high frequency, the first-order Sigma-delta noise modulation principle is met, the frequency is reduced by 10 octaves, the noise suppression capability is increased by 20dB, the noise spectral density in the bandwidth of 0.1-1 Hz reaches 0.8mHz/rtHz, and the application requirement of the silicon micro resonant accelerometer is met.

Claims (6)

1. A multi-rate adjustable sample rate frequency measurement ASIC chip, comprising:

the period counting module is used for synchronizing an analog oscillation signal F of the silicon micro-resonance accelerometer to be tested to a reference clock clk provided by a crystal oscillator, outputting a synchronized square wave signal F1, and outputting a count value N after counting the synchronized square wave signal F1 by using the reference clock;

the nonlinear compensation module is used for converting the count value N into a fixed point number q which is in direct proportion to the square of the frequency, aligning the fixed point number q with the synchronized square wave signal F1 and outputting an aligned fixed point number Dout;

the arbitrary sampling rate adjusting module is used for adjusting the sampling rate of the aligned fixed point number Dout, and outputting the fixed point number Dout3 at the final output by the arbitrary sampling rate;

and the digital interface module is used for communicating with the upper computer and comprises a configuration register and outputs data to the upper computer.

2. The multi-rate adjustable sample rate frequency measurement ASIC chip of claim 1, wherein said cycle count module comprises:

a synchronizer unit, configured to synchronize the analog oscillation signal F to a reference clock clk, and output a synchronized square wave signal F1;

a counter unit for constantly counting the synchronous backward wave signal F1 at a cycle of the reference clock clk;

the rising edge detector unit adopts two groups of registers to detect the rising edge of the synchronized square wave signal F1;

a comparator unit for comparing whether one set of register storing data fa is equal to 1 and the other set of register storing data fb is equal to 0; when fa is 1 and fb is 0, the comparator outputs an indication signal N_rdWhen the comparator outputs an indication signal N as 1_rd＝0；

The subtracter is used for calculating the difference value of the count values at two adjacent rising edges of the synchronized square wave signal F1 and outputting the count value N; when the comparator outputs the indication signal N_rdWhen the count value N is equal to 1, the count value N is updated and available, and when the comparator outputs an indication signal N_rd0 indicates that the count N is not updated and continues for a previous difference.

3. The multi-rate adjustable sample rate frequency measurement ASIC chip of claim 1, wherein said non-linearity compensation module comprises:

a reciprocal unit for outputting an indication signal N at the comparator of the cycle counting module_rdWhen 1, the reciprocal is output

And a reciprocal indication signal c_rd(ii) a When the signal c is inverted_rdWhen 1, the indication c is updated and available, and when the inverse indicates the signal c_rdWhen the value is 0, the reciprocal c is not updated and continues to the previous reciprocal;

squaring unit at reciprocal indicator signal c_rdWhen the output is 1, the reciprocal c output by the reciprocal calculating unit is squared and output, namely the output is the number of square fixed points

And a square indication signal q_rd(ii) a When square indicating signal q_rdWhen the square fixed point number q is 1, the square fixed point number q is updated and available, and when the square indication signal q is used_rdWhen the square fixed point number q is equal to 0, the square fixed point number q is not updated and continues to be a fixed point number;

the delay aligner unit is used for aligning the square fixed point number q with the synchronized square wave signal F1 and then outputting an aligned fixed point number signal Dout;

wherein M is₁Denotes the reciprocal magnification factor, M₂A reduction coefficient representing the inverse square of the fixed point number.

4. The multi-rate adjustable sample rate frequency measurement ASIC chip according to claim 3, wherein said delay aligner unit comprises:

a comparator for comparing the square indication signal q_rdWhether it is high level;

multiple registers for recording multiple sets of square indication signals q_rdAnd the square indication signal q_rdThe corresponding fixed point number q is determined according to two adjacent square indication signals q_rdDetermining the time length of the output fixed point number q, namely the time length corresponding to the synchronous backward wave signal F1;

a counter for squaring the indication signal q_rdWhen the voltage level is high, counting is started, and when the set value is reached, the register outputs an aligned fixed point number signal Dout.

5. The multi-rate adjustable sample rate frequency measurement ASIC chip of claim 1, wherein said arbitrary sample rate adjustment module comprises:

the integrator is used for adding the aligned fixed point number signal Dout and the fixed point number output by the integrator, and outputting a sliding average value Dout1 after one beat;

an extractor for extracting the fixed point value Dout2 from the sliding average value Dout1 according to a set extraction rate;

and the comb is used for carrying out low-pass filtering processing on the extracted fixed-point value Dout2 and outputting a final fixed-point value Dout 3.

6. The multi-rate adjustable sample rate frequency measurement ASIC chip according to claim 1, wherein said digital interface module comprises:

a configuration register is arranged for defining configuration words to control the decimation rate of the decimator;

and a two-stage RAM structure is arranged and used for splitting the finally output fixed point value Dout3 and then sequentially outputting the split fixed point value Dout3 to an upper computer.

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