CN114363734A - Clock data recovery method, input/output device and optical line terminal - Google Patents
Clock data recovery method, input/output device and optical line terminal Download PDFInfo
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Abstract
A serial deserializer in the input and output device opens an interface for transmitting a data sample signal and an edge sample signal for an external control module, and the control module realizes phase discrimination to adjust the phase of a clock signal. The clock signal generator in the deserializer only needs to generate a local clock signal, and then the control module adjusts the phase of the local clock signal through the phase difference between the transmission data sample signal and the edge sample signal so as to achieve the alignment of the sampling clock signal and the data sample signal, so that the deserializer does not need to have the capability of quick locking, and the realization difficulty of the deserializer is reduced.
Description
Technical Field
The present application relates to the field of optical communications technologies, and in particular, to a clock data recovery method, an input/output apparatus, and an optical line terminal.
Background
A Passive Optical Network (PON) system includes an Optical Line Terminal (OLT) installed in a central control station and a plurality of Optical Network Units (ONUs). When data is transmitted between the OLT and the ONUs, a Time Division Multiplexing (TDM) manner is adopted, that is, each ONU transmits data to the OLT in a time slice allocated by the OLT. Time slicing may be referred to as time slots or bursts (bursts). For the OLT, because different ONUs transmit data to the OLT through different time slices, the clock phases adopted by different ONUs may be different, and the data transmitted by the ONUs to the OLT does not include a clock signal, a Serializer/Deserializer (SerDes) in the OLT is required to perform clock recovery.
The scheme adopted at present for realizing clock recovery is as follows: one is to perform clock recovery by means of oversampling; another is to provide a Decision Feedback Equalizer (DFE) by a clock data recovery (clock data recovery) circuit included in the SerDes. The clock recovery time is short by adopting the oversampling mode, but when the data rate is high, the oversampling needs a rate which is many times higher than the data rate, so that the oversampling cannot be realized. With the DFE approach, the DFE needs to track data bits over a past symbol interval (UI) to predict the sampling threshold of the current bit, and the clock recovery time is long.
Disclosure of Invention
The application provides a clock data recovery method, an input/output device and an optical line terminal, which are used for reducing recovery time.
In a first aspect, an embodiment of the present application provides an input/output apparatus, which may be applied to an optical line terminal OLT, but is not limited to be applied to the optical line terminal OLT, and includes an edge sampling module, a data sampling module, a clock signal generator, and a control module; the edge sampling module is used for obtaining a first edge sample signal according to a sampling clock signal; the data sampling module is used for acquiring a first data sample signal according to a sampling clock signal; the clock signal generator is used for generating a local clock signal, receiving a phase control signal from the control module and carrying out phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal; and the control module is used for detecting the phase difference between the first edge sample signal and the first data sample signal and generating a phase control signal according to the phase difference.
In the above scheme, the phase of the clock signal is adjusted by realizing phase discrimination through the control module, so that the sampling clock signal is aligned with the data sample signal, the ability of quick locking of the serializer is not required, and the difficulty in realizing the serializer is reduced. In addition, the time length of clock recovery required by the clock recovery circuit is reduced, and whether the CDR works normally is not required to be detected by detecting and releasing the bound lock (bound lock).
In one possible design, the edge sampling module, the data sampling module, and the clock signal generator are located inside the serializer, and the control module is located outside the serializer. In the above design, the clock recovery circuit inside the serializer does not need to have a fast locking capability, and the clock signal generator only generates the local clock signal. The phase of the local clock signal generated by the clock signal generator in the serializer is controlled by the control module outside the serializer, so that the phase control is realized by the control logic in the serializer in the OLT without modifying the hardware of the serializer, and the method is simple and effective.
In one possible design, a clock signal generator includes a phase locked loop and a phase interpolator; a phase locked loop for generating a local clock signal; and the phase interpolator is used for receiving the phase control signal from the control module and carrying out phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal. In the above design, a simple and efficient clock signal generator is provided, which operates in local clock mode via a phase locked loop, and then adjusts the phase via a phase difference unit.
As an example, the phase locked loop may operate in a local clock mode to generate the local clock signal.
In one possible design, the first edge sample signal and the first data sample signal are carried in a time slice of the first optical network unit; the control module is further configured to, when determining that the sampling clock signal currently for the time slice where the first optical network unit is located meets the sampling requirement for the first data sample signal according to the phase difference between the first edge sample signal and the first data sample signal, store the phase value of the sampling clock signal currently for the time slice where the first optical network unit is located.
In one possible design, the control module is further configured to instruct, on a time slice of the first optical network unit, the clock signal generator to generate the sampling clock signal with a phase value that is the saved phase value.
Through the design, when the optimal sampling phase of a certain time slice is determined, the optimal sampling phase is included, and when the time slice is reached subsequently, the stored phase value is sampled, so that the clock recovery rate is improved.
In one possible design, an edge sampling module includes an edge sampler and a first series-to-parallel converter;
the edge sampler is used for carrying out edge sampling on the received service signal according to the sampling clock signal to obtain a second edge sample signal;
and the first serial-to-parallel converter is used for performing serial-to-parallel conversion on the second edge sample signal to obtain a first edge sample signal.
In one possible design, a data sampling module includes a data sampler and a second series-to-parallel converter;
the data sampler is used for carrying out data sampling on the received service signal according to the sampling clock signal to obtain a second data sample signal;
and the second serial-to-parallel converter is used for performing serial-to-parallel conversion on the second data sample signal to obtain a first data sample signal.
In a second aspect, an embodiment of the present application provides a clock data recovery method, including: acquiring a first edge sample signal and a first data sample signal; a phase difference between the first edge sample signal and the first data sample signal is detected, and a phase control signal for controlling a phase of a sampling clock signal for sampling the first edge sample signal and the first data sample signal is generated based on the phase difference.
In one possible design, the first edge sample signal and the first data sample signal are carried in a time slice of the first optical network unit; the method further comprises the following steps: and when the phase difference between the first edge sample signal and the first data sample signal is determined to meet the set phase difference value, storing the phase value of the sampling clock signal aiming at the time slice where the first optical network unit is located.
In one possible design, further comprising: and controlling the phase value of the sampling clock signal to be the saved phase value on the time slice of the first optical network unit.
In one possible design, obtaining a first edge sample signal includes: acquiring a second edge sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first edge sample signal to obtain a first edge sample signal; acquiring a first data sample signal, comprising: and acquiring a second data sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first data sample signal to obtain a second data sample signal.
In a third aspect, an embodiment of the present application provides an optical line terminal OLT, including the input-output apparatus of the first aspect or any design of the first aspect.
Drawings
Fig. 1 is a schematic diagram of an optical communication system according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating allocation of uplink light-emitting timeslots of an optical network device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an input/output device 300 according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an input/output device 300 according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of an input/output device 300 according to an embodiment of the present application;
FIG. 6 is a schematic flow chart illustrating a clock data recovery method according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an apparatus 700 according to an embodiment of the present application.
Detailed Description
The embodiment of the application can be applied to an optical communication system, and the optical communication system can be a Time Division Multiplexing (TDM) Passive Optical Network (PON) system. The TDM PON system may be a gigabit-passive optical network (GPON) system, an ethernet passive optical network (ethernet PON, EPON) system, a 10G ethernet passive optical network (10Gb/s ethernet passive optical network, 10G-EPON) system, a 10G gigabit-passive optical network (10 XG-PON) system, or a 10G gigabit-symmetric passive optical network (10 Gb-capacitive passive optical network, XGs-PON) system, etc.
The optical communication system includes at least an OLT and a plurality of ONUs (or Optical Network Terminals (ONTs)), and the OLT communicates with the plurality of ONUs, respectively. The OLT and the ONU can be connected through optical passive devices such as optical fibers and optical splitters. Referring to fig. 1, the OLT communicates with n ONUs through a Splitter (Splitter). In fig. 1, n ONUs are ONU1, ONU2, … …, and ONUn, respectively. Splitter may also be referred to as an optical Splitter. Splitter may be a fiber optic junction device having multiple inputs and multiple outputs for coupling, branching, and distribution of optical signals.
It should be understood that, in the embodiment of the present application, the transmission direction of the data or the optical signal carrying the data from the OLT to the ONU/ONT is referred to as the downstream direction. The transmission direction of data or data carrying optical signals from the ONU/ONTs to the OLT is called upstream direction. The OLT may transmit data or optical signals to the ONUs (downstream direction), and the ONUs may transmit data or optical signals to the OLT (upstream direction) in a unicast manner.
The data transmission between the OLT and the ONUs uses a Time Division Multiplexing (TDMA) technique, for example.
In the uplink transmission, as shown in fig. 2, each Dynamic Bandwidth Allocation (DBA) period (uplink transmission time) is divided into a plurality of time slots Ti (i is 1,2,3, … … 32, … …), and as shown in fig. 2, only one ONU is arranged in each time slot to transmit an uplink signal to the OLT in a packet manner, and the ONUs sequentially transmit in an order specified by the OLT. It should be noted that one ONU may be allocated one or more time slots. A slot may also be referred to as a Unit Interval (UI), time slice, or the like.
For the OLT, a controller and a receiver are included in the OLT. The controller may be implemented by a Media Access Control (MAC) chip. The MAC chip is used for realizing the control of the OLT to finish the physical layer and the link layer. The receiver is used for receiving the upstream signal from the ONU. Other components or devices, such as a transmitter, may also be included in the OLT, and the devices included in the OLT are not specifically limited in this application.
When the controller controls the receiver to receive the upstream signals from the plurality of ONUs, the upstream signals of different ONUs are received through different time slots, so that the upstream signals are received in a mixed manner. The clock phase of different ONUs may be different, thus requiring the receiver to have the ability to lock (or clock recover) quickly for each time slot. The scheme adopted at present for realizing clock recovery is as follows: one is to perform clock recovery by means of oversampling, for example, by using 4-8 times oversampling. The other is clock recovery capability by the SerDes in the receiver. For example, a Clock Data Recovery (CDR) circuit included in the SerDes is required to be provided with a Decision Feedback Equalizer (DFE). The clock recovery time is short by adopting the oversampling mode, but when the data rate is high, the oversampling needs a rate which is many times higher than the data rate, so that the oversampling cannot be realized. With the DFE approach, the DFE needs to track data bits over past symbol intervals to predict the sampling threshold of the current bit, and if the CDR is not operating properly, the clock phase needs to be increased or decreased 1/4UI, and then the data bits of multiple UIs need to be retraced to predict the sampling threshold of the current bit, resulting in a longer clock recovery time.
Based on this, the embodiment of the present application provides an input/output device 300. The input/output device 300 can be applied to an OLT. The functions of the input/output device may be implemented by a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Central Processing Unit (CPU), or the like. It should be noted that, the FPGA, the ASIC, or the CPU may be used only for implementing the functions of the input/output device, and may also be used for implementing other functions, such as a control function, on the basis of implementing the functions of the input/output device, which is not specifically limited in this embodiment of the present application.
The input/output device in the embodiment of the present application may also be named by other names, such as a clock data recovery device, and the naming manner in the embodiment of the present application is not particularly limited.
Referring to fig. 3, a schematic diagram of an input/output device 300 is shown.
The input/output device 300 includes an edge sampling (edge sampler) module 301, a data sampling (data sampler) module 302, a clock signal generator 303, and a control module 304. The edge sampling module 301 is coupled to a clock signal generator 303 and a control module 304, respectively. The data sampling module 302 is coupled to a clock signal generator 303 and a control module 304, respectively. The control module 304 is coupled to the clock signal generator 303.
An edge sampling module 301, configured to obtain a first edge sample signal according to a sampling clock signal. Wherein the first edge sample signal is a parallel signal.
In one possible embodiment, the edge sampler (edge sampler) module 301, the data sampler (data sampler) module 302, and the clock generator 303 in the input/output device may be located in SerDes, and the control module 304 may be implemented by control logic of an FPGA or an ASIC.
In one example, the edge sampling module 301 may include an edge sampler 3011 and a first serial to parallel (P2S) converter 3012, as shown in fig. 4. The edge sampler 3011 is configured to perform edge sampling on the received traffic signal according to the sampling clock signal to obtain a second edge sample signal. Further, the edge sampler 3011 transmits the second edge sample signal to the first P2S converter 3012, and the first P2S converter 3012 performs serial-to-parallel conversion on the second edge sample signal to obtain the first edge sample signal.
The data sampling module 302 is configured to sample a clock signal to acquire a first data sample signal. Wherein the first edge sample signal is a parallel signal.
In another example, the data sampling module 302 may include a data sampler 3021 and a second P2S converter 3022, as shown in fig. 4. The data sampler 3021 is configured to perform data sampling on the received traffic signal according to a sampling clock signal to obtain a second data sample signal. Further, the data sampler 3021 transmits the second data sample signal to the second P2S converter 3022, and the second P2S converter 3022 performs serial-to-parallel conversion on the second data sample signal to obtain the first data sample signal.
The clock signal generator 303 is configured to generate a local clock signal, receive the phase control signal from the control module 304, and perform phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal.
In one possible example, the clock signal generator 303 may include a Phase Locked Loop (PLL) 3031 and a phase interpolator 3032. The PLL operates in a local clock mode, i.e., does not perform frequency locking, to generate a local clock signal. The PLL used to generate the local clock signal may be replaced by other devices capable of operating in a local clock mode and generating the local clock signal. The phase interpolator 3032 is configured to receive the phase control signal from the control module 304, so as to perform phase adjustment on the local clock signal according to the phase control signal to obtain a sampling clock signal.
The control module 304 is configured to detect a phase difference between the first edge sample signal and the first data sample signal, and generate a phase control signal according to the phase difference.
As a possible implementation, the control module 304 may be implemented by a processing unit or a control unit. For example, the processing unit may include one or more processors, which may be Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), CPUs, or other programmable logic devices, discrete gate or transistor logic devices, and/or the like, and/or other devices that can provide the above-described functions. Illustratively, the control unit may include one or more of a Media Access Control (MAC), a Micro Control Unit (MCU), a Digital Signal Processor (DSP), a Micro Processor Unit (MPU), or the like for implementing a control function.
When the input-output device is applied to a controller, the control module may be implemented by a user logic unit in the controller.
The control module 304 has a phase discrimination function, and determines and adjusts a phase of the local clock signal to obtain a sampling clock signal by using a phase difference between the edge sample signal and the data sample signal, so that the edge sample signal and the data sample signal can be synchronized and maintain a fixed phase relationship, and further the sampling clock signal can be aligned with the data sample signal.
As an example, the transitions between binary symbols received by the control module 304 are used. The data sample signals at time (n-1) and time (n), identified as "D [ n-1 ]" and "D [ n ]", may have a logical value of 0 or 1. D [ n-1] and D [ n ] are data sample signals collected by the data sampling module 302 according to the sampling clock signal. The time delay between D [ n-1] and D [ n ] is a Unit Interval (UI), and the data samples D [ n-1] and D [ n ] are most easily detected at the center of the corresponding UI and are most accurately detected at the center of the UI, and if detection errors occur at the edge of the UI. The logic value of the data sample signal may remain constant, or may change from 0 to 1 or from 1 to 0 between time (n-1) and time (n). Between every two data sample signals, the control module 304 receives an edge sample signal E [ n-1] collected according to a sampling clock signal sent by the edge sampling module 301, and the collection time of the edge sample signal is located between D [ n-1] and D [ n ]. For example, if D [ n-1] and D [ n ] are at the edge of a jump and the edge sample signal is at the center of the UI, the phase of the sampling clock signal needs to be adjusted, i.e., the sampling phase of the edge sample signal is the optimal sampling phase of the data sample signal. If D [ n-1] and D [ n ] are at the center of the UI and the edge sample signal is at the edge of the jump, the receiving end can optimally detect the data samples D [ n-1] and D [ n ], and the sampling phases of D [ n-1] and D [ n ] are the optimal sampling phases of the data sample signal.
Fig. 5 shows a transmission diagram of a signal flow in conjunction with the structure of the input-output device shown in fig. 4.
In the embodiment of the application, the PLL works in a local clock mode, and the phase demodulation is realized through the control module to adjust the phase of the clock signal, so that the alignment of the sampling clock signal and the data sample signal is realized, the serial deserializer is not required to have the capability of quick locking, and the realization difficulty of the serial deserializer is reduced. In addition, the time length of clock recovery required by the clock recovery circuit is reduced, and whether the CDR works normally is not required to be detected by detecting and releasing the bound lock (bound lock).
Because different time slices are distributed to different ONUs and the clock phases adopted by different ONUs may be different, the scheme provided by the embodiment of the application adjusts the clock phases on the time slices adopted by different ONUs, so that the time length of clock recovery is reduced for each time slice. As an example, for ONU1, for example, the traffic signal transmitted by ONU1 is carried in time slice 1 allocated for ONU 1. After detecting the first edge sample signal and the first data sample signal of the service signal of the ONU1, the control module 304 stores a phase value of the sampling clock signal currently aiming at the time slice where the first optical network unit is located, for example, the phase value is AA, when determining that the sampling clock signal currently aiming at the time slice where the first optical network unit is located meets the sampling requirement for the data sample signal according to the phase difference between the first edge sample signal and the first data sample signal. Likewise, for ONU2, the traffic signal sent by ONU2 is carried in time slice 2 allocated for ONU 2. After detecting the first edge sample signal and the first data sample signal of the service signal of the ONU2, the control module 304 stores the phase value of the sampling clock signal currently aiming at the time slice where the first optical network unit is located, for example, the phase value BB, when determining that the sampling clock signal currently aiming at the time slice 2 where the first optical network unit is located meets the sampling requirement for the data sample signal according to the phase difference between the first edge sample signal and the first data sample signal. Based on this, control module 304, upon determining that time slice 1 is reached, sends an indication to phase interpolator 3032 indicating that the phase value of the PLL's local clock signal is AA. For example, control module 304, upon determining that time slice 1 is reached, sends phase control signal 1 to phase interpolator 3032 to control the phase value of the local clock signal of the PLL to be AA. When time slice 2 is reached, phase control signal 2 is sent to phase interpolator 3032, controlling the phase value of the local clock signal of the PLL to be BB. Thereby further reducing the phase detection and lock time.
Based on the same inventive concept as the input/output device, the embodiment of the present application provides a clock data recovery method. As shown in fig. 6.
S601, acquiring a first edge sample signal and a first data sample signal;
s602, detecting a phase difference between the first edge sample signal and the first data sample signal, and generating the phase control signal according to the phase difference, where the phase control signal is used to control a phase of the sampling clock signal, and the sampling clock signal is used to sample the first edge sample signal and the first data sample signal.
In a possible embodiment, the first edge sample signal and the first data sample signal are carried in a time slice of a first optical network unit;
the method further comprises the following steps:
and when the phase difference between the first edge sample signal and the first data sample signal is determined to meet a set phase difference value, storing the phase value of the sampling clock signal of the current time slice corresponding to the first optical network unit.
In a possible embodiment, the phase value of the sampling clock signal is controlled to be the saved phase value on the time slice of the first optical network unit.
In one possible embodiment, obtaining the first edge sample signal includes:
acquiring a second edge sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first edge sample signal to obtain a first edge sample signal;
acquiring a first data sample signal, comprising:
and acquiring a second data sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first data sample signal to obtain a second data sample signal.
In some embodiments, the controller is configured to perform the method flow illustrated in FIG. 6. As an example, fig. 7 is a schematic structural diagram of another apparatus 700 provided in the embodiment of the present application, for implementing the method flow shown in fig. 6. The apparatus 700 includes a communication interface 701, a processor 702, and a memory 703. The communication interface 701 is used to receive traffic data from the ONU. The memory 703 is used for storing data. In one approach, the processor 702 may include an input-output device to implement the above-described embodiments. Alternatively, the memory 703 may store the input-output devices as instructions that are executed by the processor 702.
The processor 702 is any combination of hardware, middleware, firmware, or software. The processor 702 comprises any combination of one or more CPU chips, cores, FPGAs, ASICs, or DSPs. The memory 703 may comprise any combination of disks, tape drives, or solid state drives. Apparatus 700 may use memory 703 as an overflow data storage device to store programs for execution when selected by apparatus 700, and to store instructions and data for apparatus 700 to read during program execution. The memory 703 may be volatile or non-volatile, and may be any combination of read-only memory (read-only memory), random-access memory (random-access memory), ternary content-addressable memory (ternary-addressable memory), or static ram (static ram).
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (12)
1. An input/output device is characterized by comprising an edge sampling module, a data sampling module, a clock signal generator and a control module; wherein the content of the first and second substances,
the edge sampling module is used for obtaining a first edge sample signal according to a sampling clock signal;
the data sampling module is used for acquiring a first data sample signal according to the sampling clock signal;
the clock signal generator is used for generating a local clock signal, receiving a phase control signal from a control module, and performing phase adjustment on the local clock signal according to the phase control signal to obtain the sampling clock signal;
the control module is configured to detect a phase difference between the first edge sample signal and the first data sample signal, and generate the phase control signal according to the phase difference.
2. The apparatus of claim 1, wherein the input-output means comprises a serializer, the edge sampling module, the data sampling module, and the clock signal generator are located inside the serializer, and the control module is located outside the serializer.
3. The apparatus of claim 1 or 2, wherein the clock signal generator comprises a phase locked loop and a phase interpolator;
the phase-locked loop is used for generating the local clock signal;
and the phase interpolator is used for receiving the phase control signal from the control module and carrying out phase adjustment on the local clock signal according to the phase control signal to obtain the sampling clock signal.
4. The apparatus according to any of claims 1-3, wherein the first edge sample signal and the first data sample signal are carried in a time slice of a first optical network unit;
the control module is further configured to, when determining that the sampling clock signal currently for the time slice where the first optical network unit is located meets a sampling requirement for the first data sample signal according to the phase difference between the first edge sample signal and the first data sample signal, store a phase value of the sampling clock signal currently for the time slice where the first optical network unit is located.
5. The apparatus of claim 4, wherein the control module is further configured to indicate, on the time slice of the first optical network unit, a phase value of a sampling clock signal generated by the clock signal generator as the saved phase value.
6. The apparatus of any of claims 1-5, wherein the edge sampling module comprises an edge sampler and a first series-to-parallel converter;
the edge sampler is used for performing edge sampling on the received service signal according to the sampling clock signal to obtain a second edge sample signal;
the first serial-to-parallel converter is used for performing serial-to-parallel conversion on the second edge sample signal to obtain a first edge sample signal.
7. The apparatus of any of claims 1-6, wherein the data sampling module comprises a data sampler and a second series-to-parallel converter;
the data sampler is used for performing data sampling on the received service signal according to the sampling clock signal to obtain a second data sample signal;
and the second serial-to-parallel converter is used for performing serial-to-parallel conversion on the second data sample signal to obtain a first data sample signal.
8. A method of clock data recovery, comprising:
acquiring a first edge sample signal and a first data sample signal;
detecting a phase difference of the first edge sample signal and the first data sample signal, and generating the phase control signal according to the phase difference, wherein the phase control signal is used for controlling the phase of a sampling clock signal, and the sampling clock signal is used for sampling the first edge sample signal and the first data sample signal.
9. The method of claim 8, wherein the first edge sample signal and the first data sample signal are carried in time slices of a first optical network unit;
the method further comprises the following steps:
and when determining that the sampling clock signal aiming at the time slice where the first optical network unit is located meets the sampling requirement of the first data sample signal according to the phase difference between the first edge sample signal and the first data sample signal, saving the phase value of the sampling clock signal aiming at the time slice where the first optical network unit is located.
10. The method of claim 9, further comprising:
and controlling the phase value of the sampling clock signal to be the saved phase value on the time slice of the first optical network unit.
11. The method of any one of claims 8-10, wherein obtaining a first edge sample signal comprises:
acquiring a second edge sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first edge sample signal to obtain a first edge sample signal;
acquiring a first data sample signal, comprising:
and acquiring a second data sample signal according to the sampling clock signal, and performing serial-parallel conversion on the first data sample signal to obtain a second data sample signal.
12. An optical line termination, OLT, comprising an input-output arrangement according to any of claims 1-7.
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| CN116795172A (en) * | 2023-08-29 | 2023-09-22 | 芯耀辉科技有限公司 | Cross-clock domain processing method, medium and device for high-speed digital transmission |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040037383A1 (en) * | 1999-12-31 | 2004-02-26 | Hongjiang Song | Data resynchronization circuit |
| CN101194419A (en) * | 2005-05-24 | 2008-06-04 | 菲尼萨公司 | Pattern-dependent phase detector for clock recovery |
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN105634451A (en) * | 2015-12-29 | 2016-06-01 | 龙迅半导体（合肥）股份有限公司 | Data clock recovery circuit and phase interpolator |
| CN105786746A (en) * | 2015-01-12 | 2016-07-20 | 美国亚德诺半导体公司 | Apparatus And Methods For Clock And Data Recovery |
| CN105794144A (en) * | 2013-12-27 | 2016-07-20 | 英特尔公司 | Phase adjustment circuit for clock and data recovery circuit |
| CN106165298A (en) * | 2014-05-02 | 2016-11-23 | 高通股份有限公司 | There is high shake tolerance and the most phase-locked clock and data recovery |
| US20180152284A1 (en) * | 2015-07-28 | 2018-05-31 | Rambus Inc. | Collaborative clock and data recovery |
| US20190280849A1 (en) * | 2018-03-12 | 2019-09-12 | Qualcomm Incorporated | Clock data recovery broadcast for multi-lane serdes |
-
2020
- 2020-10-12 CN CN202011085602.3A patent/CN114363734B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040037383A1 (en) * | 1999-12-31 | 2004-02-26 | Hongjiang Song | Data resynchronization circuit |
| CN101194419A (en) * | 2005-05-24 | 2008-06-04 | 菲尼萨公司 | Pattern-dependent phase detector for clock recovery |
| CN103219992A (en) * | 2013-01-31 | 2013-07-24 | 南京邮电大学 | Blind sampling clock data recovery circuit with filter shaping circuit |
| CN105794144A (en) * | 2013-12-27 | 2016-07-20 | 英特尔公司 | Phase adjustment circuit for clock and data recovery circuit |
| CN106165298A (en) * | 2014-05-02 | 2016-11-23 | 高通股份有限公司 | There is high shake tolerance and the most phase-locked clock and data recovery |
| CN105786746A (en) * | 2015-01-12 | 2016-07-20 | 美国亚德诺半导体公司 | Apparatus And Methods For Clock And Data Recovery |
| US20180152284A1 (en) * | 2015-07-28 | 2018-05-31 | Rambus Inc. | Collaborative clock and data recovery |
| CN105634451A (en) * | 2015-12-29 | 2016-06-01 | 龙迅半导体（合肥）股份有限公司 | Data clock recovery circuit and phase interpolator |
| US20190280849A1 (en) * | 2018-03-12 | 2019-09-12 | Qualcomm Incorporated | Clock data recovery broadcast for multi-lane serdes |
Non-Patent Citations (1)
| Title |
|---|
| 刘文彦: "时钟恢复在电力电子系统集成中的应用", 《机电工程》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116795172A (en) * | 2023-08-29 | 2023-09-22 | 芯耀辉科技有限公司 | Cross-clock domain processing method, medium and device for high-speed digital transmission |
| CN116795172B (en) * | 2023-08-29 | 2023-12-12 | 芯耀辉科技有限公司 | Cross-clock domain processing method, medium and device for high-speed digital transmission |
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| CN114363734B (en) | 2023-06-20 |
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