CN114362324A - Panel charging circuit and panel charging terminal device - Google Patents
Panel charging circuit and panel charging terminal device Download PDFInfo
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Abstract
The invention discloses a panel charging circuit and a panel charging terminal device, wherein the panel charging circuit comprises: the display device comprises a plurality of driving modules, a display module, a main control module, a level output module and a plurality of switch modules; the main control module is used for outputting a first starting signal to the driving module, the level output module is used for outputting a second starting signal to the driving module and generating a corresponding switch control signal to the switch module according to different display pictures, the driving module is used for generating a driving signal to the switch module according to the first starting signal and the second starting signal, the switch module is used for switching to a corresponding path according to the switch control signal to transmit the driving signal to the display module, and the display module is used for displaying pictures according to the driving signal. The switch module is used for switching to the corresponding path transmission driving signal according to different switch control signals, so that the corresponding transmission path is switched according to different pictures, and the charging time of the panel is saved.
Description
Technical Field
The present invention relates to the field of electronic circuit technologies, and in particular, to a panel charging circuit and a panel charging terminal device.
Background
As display panels develop toward high resolution and high refresh rates, the problem of under-charging becomes more and more severe. The insufficient charging time greatly affects the normal display of the liquid crystal panel, and causes many undesirable phenomena, such as color shift, water ripple, etc. At present, the development of high-end panels (such as 8K 120HZ panels) still has many problems, the most prominent one is the problem of insufficient charging, and therefore, it is important to solve the charging problem in order to further promote the development of high-end panels.
For an 8K 120HZ panel (7680 × 4320, H _ total 4500, as exemplified by the 1G1D architecture in fig. 1), the scan time per line, i.e., 1H, is approximately 16.6ms/2/4500 ≈ 1.8 us. This charging time is very limited with respect to 7.4us for a 4K 60HZ panel. And the charging time CT of the panel is m (1H), where m is a coefficient, for example, usually about 0.6, and H is one row, then the charging time of 8K 120HZ is about 1.08 us. Furthermore, as the signal decays in transmission to both the XR and XL sides, less charging time occurs across the panel. As shown in fig. 2, the panel has the in-plane charging time distribution along with signal transmission, the middle charging time is the most sufficient, the two sides gradually attenuate, and the charging time becomes about 0.1us or even negative when reaching the most side.
If the panel architecture is the Dual Gate (GD) architecture shown in fig. 1, the scan time of the panel is doubled, the charge time is doubled, and the charge time is more limited. Generally, the charging time of the current 8K 120HZ panel is a very big bottleneck, and various display problems caused by insufficient charging time are troubling to the industry.
Thus, the prior art has yet to be improved and enhanced.
Disclosure of Invention
The invention mainly aims to provide a panel charging circuit and a panel charging terminal device, and aims to solve the problem that in the prior art, when power is supplied to a display panel, the display of the panel is abnormal due to insufficient charging time.
In order to achieve the purpose, the invention adopts the following technical scheme:
a panel charging circuit comprising: the display device comprises a plurality of driving modules, a display module, a main control module, a level output module and a plurality of switch modules; the driving modules are respectively connected with the switch modules and the level output module, the driving modules are sequentially connected, the driving modules are also connected with the main control module, and each switch module is also connected with the level output module and the display module; the main control module is used for outputting a first starting signal to the driving module, the level output module is used for outputting a second starting signal to the driving module and generating a corresponding switch control signal to the switch module according to different display pictures, the driving module is used for generating a driving signal to the switch module according to the first starting signal and the second starting signal, the switch module is used for switching to a corresponding path according to the switch control signal to transmit the driving signal to the display module, and the display module is used for displaying pictures according to the driving signal.
In the panel charging circuit, the switch module includes: a first switching unit and a second switching unit; the first switch unit is respectively connected with the driving module, the display module and the second switch unit, and the second switch unit is also connected with the driving module and the display module; the first switch unit is used for changing the opening and closing state of the first switch unit according to the switch control signal, and the second switch unit is used for changing the opening and closing state of the second switch unit according to the switch control signal.
In the panel charging circuit, the driving module includes: a driver; the driver of the drive module and the driver of the drive module 2 are all connected with the switch module 1, the driver of the drive module and the driver of the drive module 4 are all connected with the switch module 2, until the 2(N-1) is the driver of the drive module and the driver of the drive module 2 are all connected with the switch module N, each driver is sequentially connected, each driver is further respectively connected with the main control module and the display module, and the driver of the drive module 1 is further connected with the level output module.
In the panel charging circuit, the number of the switch modules is half of the number of the drive modules, the 1 st drive module and the 2 nd drive module are all connected with the 1 st switch module, the 1 st drive module is also connected with the level output module, the 3 rd drive module and the 4 th drive module are all connected with the 2 nd switch module until the 2(N-1) th drive module and the 2N drive module are all connected with the N switch module.
In the panel charging circuit, the first switching unit includes: the first switching tube, the second switching tube and the third switching tube; the first pin of the first switch tube is connected with the driving module and the second switch unit respectively, the second pin of the first switch tube is connected with the second pin of the second switch tube and the first pin of the third switch tube respectively, the third pin of the first switch tube, the third pin of the second switch tube and the third pin of the third switch tube are all connected with the level output module, and the first pin of the second switch tube and the second pin of the third switch tube are all connected with the display module.
In the panel charging circuit, the second switching unit includes: a fourth switching tube and a fifth switching tube; the first pin of the fourth switch tube and the first pin of the fifth switch tube are both connected with the driving module, the second pin of the fourth switch tube and the second pin of the fifth switch tube are both connected with the display module, and the third pin of the fourth switch tube and the third pin of the fifth switch tube are both connected with the level output module.
In the panel charging circuit, the level output module includes: a level shifter; the level shifter is respectively connected with the driving module, the third pin of the first switch tube, the third pin of the second switch tube, the third pin of the third switch tube, the third pin of the fourth switch tube and the third pin of the fifth switch tube.
In the panel charging circuit, the first switch tube, the second switch tube and the third switch tube are all thin film transistors; the first pin of the first switching tube, the first pin of the second switching tube and the first pin of the third switching tube are source electrodes; the second pin of the first switching tube, the second pin of the second switching tube and the second pin of the third switching tube are drain electrodes; and the third pin of the first switching tube, the third pin of the second switching tube and the third pin of the third switching tube are grids.
In the panel charging circuit, the fourth switching tube and the fifth switching tube are both thin film transistors; the first pin of the fourth switching tube and the first pin of the fifth switching tube are both source electrodes; the second pin of the fourth switching tube and the second pin of the fifth switching tube are both drain electrodes; and the third pin of the fourth switching tube and the third pin of the fifth switching tube are both grids.
A panel charging terminal device comprises a PCB, wherein the PCB is provided with a panel charging circuit.
Compared with the prior art, the panel charging circuit and the panel charging terminal device provided by the invention comprise: the display device comprises a plurality of driving modules, a display module, a main control module, a level output module and a plurality of switch modules; the main control module is used for outputting a first starting signal to the driving module, the level output module is used for outputting a second starting signal to the driving module and generating a corresponding switch control signal to the switch module according to different display pictures, the driving module is used for generating a driving signal to the switch module according to the first starting signal and the second starting signal, the switch module is used for switching to a corresponding path according to the switch control signal to transmit the driving signal to the display module, and the display module is used for displaying pictures according to the driving signal. According to the invention, the switch module is switched to the corresponding path transmission driving signal according to different switch control signals, so that the switching to the corresponding transmission path according to different pictures is realized, and the time for charging the panel is effectively saved.
Drawings
FIG. 1 is a comparison diagram of pixels of the 1G1D architecture and the H21D architecture provided by the present invention;
FIG. 2 is a schematic diagram of charging time versus signal decay provided by the present invention;
FIG. 3 is a block diagram of a panel charging circuit according to the present invention;
FIG. 4 is a circuit diagram of a panel charging circuit according to the present invention;
FIG. 5 is a circuit diagram of another embodiment of the present invention;
FIG. 6 is a diagram of an H _ strip picture and its pixel brightness and darkness provided by the present invention;
fig. 7 is a flowchart of a panel charging circuit according to the present invention.
Reference numerals: 100: a drive module; 200: a display module; 300: a main control module; 400: a level output module; 500: a switch module; 510: a first switch unit; 520: a second switching unit; t1: a first switch tube; t2: a second switching tube; t3: a third switching tube; t4: a fourth switching tube; t5: a fifth switching tube; a driver: GOA block.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
According to the panel charging circuit and the panel charging terminal device, the main control module outputs the corresponding switch control signal to the switch module according to different display pictures, and then the switch module switches to the corresponding path according to the switch control signal to transmit the first starting signal, so that the switching to the corresponding transmission path according to different pictures is realized, the time for scanning the panel is effectively saved, and the time for charging the panel is saved.
The following describes a design scheme of a panel charging circuit by using specific exemplary embodiments, and it should be noted that the following embodiments are only used to explain the technical scheme of the invention, and are not limited specifically:
referring to fig. 3, a panel charging circuit according to the present invention includes: a plurality of driving modules 100, a display module 200, a main control module 300, a level output module 400, and a plurality of switch modules 500; the driving module 100 is respectively connected to the switching module 500 and the level output module 400, a plurality of the driving modules 100 are sequentially connected, the driving modules 100 are also connected to the main control module 300, and each of the switching modules 500 is also connected to the level output module 400 and the display module 200; the main control module 300 is configured to output a first start signal to the driving module 100, the level output module 400 is configured to output a second start signal to the driving module 100, and is configured to generate a corresponding switch control signal to the switch module 500 according to different display pictures, the driving module 100 is configured to generate a driving signal to the switch module 500 according to the first start signal and the second start signal, the switch module 500 is configured to switch to a corresponding path according to the switch control signal to transmit the driving signal to the display module 200, and the display module 200 is configured to perform display according to the driving signal. Wherein N is a positive integer greater than 1.
Specifically, first, the host module 300 outputs the first turn-on signal (generally, a plurality of CK signals, such as CK1-CK6 or CK1-CK8, or even CK1-CK10, etc.), an LC signal (generally, two opposite polarity signals, LC1 and LC2) and a VSS signal (may include two VSS signals, namely VSS1 and VSS2, or may have only one VSS signal)) to the driving module 100, and the level output module 400 also outputs the second turn-on signal (turn-on signal ST) to the driving module 100, and then the driving module 100 generates the driving signal (level logic signal) to the switch module 500 according to the first turn-on signal and the second turn-on signal, and at the same time, the host module 300 displays different images, such as a normal white image or a special image (H _ strip), controlling the level output module 400 to generate different switch control signals to the switch module 500, if the display picture is a normal picture, controlling the level output module 400 to generate a first switch control signal to the switch module 500, switching the switch module 500 to a first transmission path according to the first switch control signal, and then transmitting the driving signal to the display module 200 according to the first transmission path by the switch module 500; if the display frame is a special frame, controlling the level output module 400 to generate a second switch control signal to the switch module 500, switching the switch module 500 to a second transmission path according to the second switch control signal, and then transmitting the driving signal to the display module 200 by the switch module 500 according to the second transmission path; finally, the display module 200 displays the image according to the driving signal.
In the invention, the driving signal is transmitted to the display module 200 by switching the corresponding transmission path according to different display pictures so as to scan the display module 200 in different scanning modes, thereby saving the time for scanning the common picture and saving the time for charging the display module 200.
Furthermore, the number of the switch modules 500 is half of the number of the driving modules 100, the 1 st driving module 100 and the 2 nd driving module 100 are both connected to the 1 st switch module 500, the 1 st driving module 100 is further connected to the level output module 400, the 3 rd driving module 100 and the 4 th driving module 100 are both connected to the 2 nd switch module 500, until the 2(N-1) th driving module 100 and the 2N th driving module 100 are both connected to the N th switch module 500. That is, each of the switch modules 500 is connected to two of the driving modules 100.
Further, referring to fig. 4, the driving module 100 includes: a driver GOA block; wherein, in the embodiment of the invention, the driver of the 1 st driving module 100 is labeled as GOA block1, the driver of the 2 nd driving module 100 is labeled as GOA block2, the driver of the 3 rd driving module 100 is labeled as GOA block3, and the drivers of the 2 nd driving module 100 are labeled as GOA block (2N); the driver GOA block1 of the 1 st driver module 100 and the driver GOA block2 of the 2 nd driver module 100 are both connected to the 1 st switch module 500, the driver GOA block3 of the 3 rd driving module 100 and the driver GOA block4 of the 4 th driving module 100 are all connected with the 2 nd switch module 500, until the 2 nd (N-1) driver GOA block2(N-1) and the 2N nd of the driving module 100 the driver GOA block (2N) of the driving module 100 is all connected with the nth switch module 500, each driver GOA block is sequentially connected, each driver GOA block is further respectively connected with the main control module 300 and the display module 200, the 1 st driver GOA block1 of the driving module 100 is further connected with the level output module 400.
The driver GOA block (GOA) is formed by directly applying a line scan signal to array or glass of the LCD, and is different from a conventional method in which a line scan signal is integrated on a Gate IC. The output end of the previous driver GOA block is used as the input end of the next driver GOA block, that is, the output end of the driver GOA block1 of the drive module 1 is connected with the input end of the driver GOA block 22, the output end of the driver GOA block 22 is connected with the input end of the driver GOA block 33, and the output ends are sequentially connected until the output end of the driver GOA block2(N-1) 2 is connected with the input end of the driver GOA block (2N).
Further, the main control module 300 includes: a system-on-chip; the system-on-chip is connected to each of the driving modules 100. The System-on-a-Chip is an integrated circuit with a special purpose, and comprises a complete System and all contents of embedded software; the main control module 300 may further include: TCON (Timing controller), which is a Timing control master chip, generates GOA Timing, Data and integrates various IPs.
Further, the level output module 400 includes: a level shifter; the level shifter is respectively connected with the driving module 100, the third pin of the first switch transistor T1, the third pin of the second switch transistor T2, the third pin of the third switch transistor T3, the third pin of the fourth switch transistor T4 and the third pin of the fifth switch transistor T5. The Level Shifter (Level Shifter IC, abbreviated as LSI) is connected with the mainboard and the liquid crystal display screen through screen lines or flat cables.
Further, the switch module 500 includes: a first switching unit 510 and a second switching unit 520; wherein, in the embodiment of the invention, the 1 st one of the first switch units is labeled as 511, the 2 nd one of the first switch units is labeled as 512, the 3 rd one of the first switch units is labeled as 513, and up to the nth one of the first switch units is labeled as 51N; the 1 st second switch unit is marked as 521, the 2 nd second switch unit is marked as 522, the 3 rd second switch unit is marked as 523, and the nth second switch unit is marked as 52N; the first switch unit 510 is respectively connected to the driving module 100, the display module 200 and the second switch unit 520, and the second switch unit 520 is further connected to the driving module 100 and the display module 200; the first switch unit 510 is configured to change an on/off state thereof according to the switch control signal, and the second switch unit 520 is configured to change an on/off state thereof according to the switch control signal.
Specifically, the soc or the timing controller may control the level shifter to generate different switch control signals to the first switch unit 510 and the second switch unit 520 according to different display images, if the display images are normal images, the level shifter is controlled to generate a first switch control signal to the first switch unit 510 and the second switch unit 520, the first switch unit 510 and the second switch unit 520 are switched to a first transmission path according to the first switch control signal, and finally, the first switch unit 510 transmits the driving signal to the display module 200 according to the first transmission path, so that the display module 200 performs a next operation; if the display frame is a special frame, the level shifter is controlled to generate a second switch control signal to the first switch unit 510 and the second switch unit 520, the first switch unit 510 and the second switch unit 520 switch to a second transmission path according to the second switch control signal, and finally, the second switch unit 520 transmits the driving signal to the display module 200 according to the second transmission path, so that the display module 200 performs the next operation. In the present invention, the first switch unit 510 and the second switch unit 520 are controlled to switch to different paths according to different display images, so as to transmit the driving signal to the display module 200 according to different paths, thereby saving the time for charging the common image.
Further, the first switching unit 510 includes: a first switching tube T1, a second switching tube T2 and a third switching tube T3; wherein, in the embodiment of the invention, the 1 st first switch tube is labeled as T11, the 2 nd first switch tube is labeled as T12, the 3 rd first switch tube is labeled as T13, and the nth first switch tube is labeled as T1N; the 1 st second switch tube is labeled as T21, the 2 nd second switch tube is labeled as T22, the 3 rd second switch tube is labeled as T23, and the nth second switch tube is labeled as T2N; the 1 st third switching tube is marked as T31, the 2 nd third switching tube is marked as T32, the 3 rd third switching tube is marked as T33, and the nth third switching tube is marked as T3N; a first pin of the first switching tube T1 is connected to the driving module 100 and the second switching unit 520, a second pin of the first switching tube T1 is connected to a second pin of the second switching tube T2 and a first pin of the third switching tube T3, a third pin of the first switching tube T1, a third pin of the second switching tube T2 and a third pin of the third switching tube T3 are all connected to the level shifter, and a first pin of the second switching tube T2 and a second pin of the third switching tube T3 are all connected to the display module 200. In this embodiment, the output terminal of the odd driver GOA block is connected to the first pin of the corresponding first switch transistor T1.
Specifically, if the display frame is a normal frame, first, the soc or the timing controller controls the level shifter to generate a high level signal to the first switch tube T1, the second switch tube T2 and the third switch tube T3 (through the wires EN1 and EN2 in this embodiment), and simultaneously generate a low level signal to the second switch unit 520, that is, the switch control signal is a logic signal of "110", that is, the first switch control signal is a logic signal of "110", at this time, the first switch tube T1, the second switch tube T2 and the third switch tube T3 are all turned on, the second switch unit 520 stops operating, and switches to a first transmission path, that is, the driving signal is transmitted to the display module 200 through the first switch tube T1, the second switch tube T2 and the third switch tube T3, therefore, the display module 200 can perform the next operation, and at this time, the second switching tube T2 and the third switching tube T3 are simultaneously turned on, and the driving signals in the odd drivers GOA block of the 1 st to 2 nd N can simultaneously enter the display module 200 through the corresponding second switching tube T2 and the third switching tube T3 at one time, so that the panel can be scanned in two rows, and the time for scanning and charging the panel can be effectively saved.
If the display frame is a special frame, firstly, the soc or the timing controller controls the level shifter to generate a high level signal to the first switch tube T1, generate a low level signal to the second switch tube T2 and the third switch tube T3, and simultaneously generate a high level signal to the second switch unit 520, that is, a logic signal (arranged in the order of the EN1-EN3 wires) with the switch control signal of "101", that is, a logic signal with the second switch control signal of "101", at this time, the first switch tube T1 is turned on, the second switch tube T2 and the third switch tube T3 are both turned off, the second switch unit 520 starts to operate normally, and is switched to a second transmission path, that is, the driving signal is transmitted to the display module 200 through the second switch unit 520, so that the display module 200 performs the next operation, thereby enabling the special picture to be displayed normally. If the display picture is a special picture, the second switch control signal is controlled to output a logic signal of '001' or '101', and the special picture can be displayed normally.
Further, the second switching unit 520 includes: a fourth switching tube T4 and a fifth switching tube T5; wherein, in the embodiment of the invention, the 1 st of the fourth switch tubes is labeled as T41, the 2 nd of the fourth switch tubes is labeled as T42, the 3 rd of the fourth switch tubes is labeled as T43, and up to the nth of the fourth switch tubes is labeled as T4N; the 1 st fifth switch tube is marked as T51, the 2 nd fifth switch tube is marked as T52, the 3 rd fifth switch tube is marked as T53, and the nth fifth switch tube is marked as T5N; the first pin of the fourth switching tube T4 and the first pin of the fifth switching tube T5 are both connected to the driving module 100, the second pin of the fourth switching tube T4 and the second pin of the fifth switching tube T5 are both connected to the display module 200, and the third pin of the fourth switching tube T4 and the third pin of the fifth switching tube T5 are both connected to the level shifter.
In this embodiment, an output end of each driver GOA block is correspondingly connected to a first pin of the fourth switching tube T4 or a first pin of the fifth switching tube T5, that is, the output end of the driver GOA block of the 1 st driving module is connected to a first pin of the fourth switching tube T4, an output end of the driver GOA block of the 2 nd driver GOA block is connected to a first pin of the fifth switching tube T5, until the output end of the driver GOA block of the N-1 st driver GOA block is connected to a first pin of the fourth switching tube T4 of the 2N-1 st driver GOA block, and an output end of the driver GOA block of the 2N th driver GOA block is connected to a first pin of the fifth switching tube T5 of the N-1 st driver.
Specifically, if the display frame is a normal frame, first, the soc or the timing controller controls the level shifter to generate a high level signal to the first switch transistor T1, the second switch transistor T2 and the third switch transistor T3, and simultaneously generate a low level signal to the fourth switch transistor T4 and the fifth switch transistor T5 (via the EN3 wire in this embodiment), that is, the switch control signal is a logic signal of "110", that is, the first switch control signal is a logic signal of "110", at this time, the first switch transistor T1, the second switch transistor T2 and the third switch transistor T3 are all turned on, the fourth switch transistor T4 and the fifth switch transistor T5 are all turned off, and are switched to a first transmission path, that is, the driving signal is transmitted to the display module 200 via the first switch transistor T1, the second switch transistor T2 and the third switch transistor T3, so that the display module 200 can perform the next operation.
If the display frame is a special frame, firstly, the soc or the timing controller controls the level shifter to generate a high level signal to the first switch transistor T1, the fourth switch transistor T4 and the fifth switch transistor T5, and simultaneously generate a low level signal to the second switch transistor T2 and the third switch transistor T3, that is, the switch control signal is a logic signal of "101", that is, the second switch control signal is a logic signal of "101", at this time, the first switch transistor T1, the fourth switch transistor T4 and the fifth switch transistor T5 are turned on, the second switch transistor T2 and the third switch transistor T3 are turned off, and a second transmission path is switched, that is, the driving signal is transmitted to the display module 200 through the third switch transistor T4 and the fifth switch transistor T5, so that the display module 200 performs a next operation, at this time, each driver GOA block is connected to one corresponding fourth switching tube T4 or fifth switching tube T5, and the driving signal enters the display module 200 through the fourth switching tube T4 and the fifth switching tube T5, so that the special picture is scanned line by line, thereby normally displaying the special picture and ensuring the integrity of displaying the displayed picture.
Further, as shown in fig. 5, another embodiment of the present invention: the output end of the driver GOA block in the even number is connected to the first pin of the corresponding first switching transistor T1, and the output end of each driver GOA block is connected to the corresponding fourth switching transistor T4 or the corresponding fifth switching transistor T5, that is, the connection manner of the driver GOA block in the even number in the alternative is just the connection manner of the driver GOA block in the odd number in this embodiment, and the effect in this embodiment can also be achieved in the same manner, which is the same as this embodiment.
In fig. 4, odd blocks of the GOA blocks are used for scanning, the originally designed GOA block1/GOA block3 … … GOA block (N-1) is used as a new scanning circuit, and gout1/gout2 … … goutN (if 8K 1G1D, N is 2160) is respectively output as a scanning driving signal of each line, the number of lines to be scanned in the prior art is 2N is 4320, and after the scanning method of the present invention is adopted, the number of lines to be scanned can be reduced to half of the original number. Due to the dual-side driving, the right GOA signal in fig. 4 is also scanned synchronously with the left GOA signal, i.e. the ST start signal is input simultaneously to the left and right sides, and the CK/LC/VSS signal is also synchronously obtained, and the 1 ST line and the 2 nd line are scanned simultaneously to the nth line, etc. Similarly, fig. 5 is compared with fig. 4, only even numbered GOA blocks of the original circuit are used to form a new GOA scanning circuit, each row also outputs gout1/gout2 … … goutN (if 8K 1G1D, N is 2160), the present solution is also applicable to Dual gate architecture (see fig. 1 in particular), TCON-less architecture (a TCON functional module is integrated into the SOC, and the SOC directly outputs Mini-LVDS or P-P signals to a driver IC of the screen) and VBO architecture (the TCON functional module is not integrated into the SOC, and there is an independent TCON IC, and at this time, the SOC inputs VBO signals (or LVDS) to the TCON IC, and the TCON IC outputs P-P signals (or Mini-LVDS) to the driver IC of the screen).
If only the two-line on and scan mode is used, some special pictures, such as an H _ strip picture, cannot be displayed, and the picture is a picture with one line bright and one line dark and cannot be realized by using the driving mode of the present invention. Therefore, the panel charging circuit provided by the invention is a control circuit for controlling the switching between progressive scanning and two-line scanning. As shown in fig. 4, T11-T (1N), T21-T (2N), T31-T (3N), T41-T (4N) and T51-T (5N) are provided to control the type of line scan for these TFT tubes, wherein the bases of these tubes are correspondingly connected to EN1-EN3 conductive lines, and the drains of T21-T (2N), T31-T (3N), T41-T (4N) and T51-T (5N) and T11-T (1N) are respectively connected to GoutN (the drain of the corresponding switch tube on the left in this embodiment is labeled GoutN _ L, the drain of the corresponding switch tube on the right is labeled GoutN _ R) and GoutN (the drain of the corresponding switch tube on the left in this embodiment is labeled GoutN _ L, the drain of the corresponding switch tube on the right is labeled GoutN _ R). When the EN1-EN3 lead is at "110" logic level, T11/T21/T31/T12/T22 … … T (2N)/T (3N) is turned on, the GOA scanning circuit is turned on for two rows and two rows, when the EN1-EN3 lead is at "101", "001" or "101" logic level, T41/T51/T42/T52 … T (4N)/T (5N) is turned on, and Gout1/Gout2 … … Gout (2N) are scanned row by row in sequence, and special pictures, such as H _ Strip pictures with one row bright and one row dark, can be displayed. Similarly, the circuit of fig. 5 is also provided with TFT tubes for switching between single-line scanning and double-line scanning, and the operation or scanning principle thereof is similar to that of fig. 4, and the scanning mode can be switched according to different pictures, thereby not only realizing significant improvement of the charging time of the high-order panel, but also considering display of some special pictures.
The embodiment of the invention provides a starting mode capable of selecting rows according to a picture, and can control a panel to scan line by line for a very small number of pictures which need each row of data to change, such as an H _ strip picture (a row is bright and a row is dark, refer to FIG. 6, the picture is rarely used, and the picture can be used only when a panel factory performs a limit power consumption test). For most pictures, the panel can be controlled to be opened in two lines and two lines, so that half of scanning time can be saved theoretically, and the charging time is doubled.
Further, the first switch transistor T1, the second switch transistor T2 and the third switch transistor T3 are all thin film transistors; the first pin T1 of the first switch tube, the first pin of the second switch tube T2 and the first pin of the third switch tube T3 are all source electrodes; the second pin of the first switch tube T1, the second pin of the second switch tube T2 and the second pin T3 of the third switch tube are drain electrodes; the third pin of the first switch transistor T1, the third pin of the second switch transistor T2 and the third pin of the third switch transistor T3 are all gates. The english of the thin Film transistor is abbreviated as tft (thin Film transistor): each liquid crystal pixel on the liquid crystal display is driven by a thin film transistor integrated behind the liquid crystal pixel.
Further, the fourth switching tube T4 and the fifth switching tube T5 are both thin film transistors; a first pin of the fourth switching tube T4 and a first pin of the fifth switching tube T5 are both source electrodes; a second pin of the fourth switching tube T4 and a second pin of the fifth switching tube T5 are both drains; the third pin of the fourth switching tube T4 and the third pin of the fifth switching tube T5 are both gates.
As shown in fig. 7, which is a flowchart for implementing the embodiment, after the LCD is powered on, the SOC or the TCON determines the input data. For a few frames requiring different data of each row, the SOC or TCON controls the Level shifter IC to output corresponding logic Level signals ("101", "001", or "101") to the EN1-EN3 wires, so that all the T41-T (4N) and T51-T (5N) switch tubes are turned on, and the GOA signals are scanned line by line. If the displayed picture is not different in each row, the SOC or the TCON can control the Level shifter IC to output a corresponding logic Level signal ('110') to an EN1-EN3 lead, all the T11-T (1N), T21-T (2N) and T31-T (3N) switching tubes are all turned on, two rows of GOA are turned on, and the charging time is reduced to half.
For a better understanding of the present invention, the operation of the panel charging circuit of the present invention is described in detail below with reference to fig. 4:
first, the System On Chip (SOC) or the Timing Controller (TCON) outputs the first turn-on signal (generally, a plurality of CK, such as CK1-CK6 or CK1-CK8, even CK1-CK10, and so on CK number), LC signal (generally, two opposite polarity signals, LC1 and LC2) and VSS signal (which may include two VSS signals, namely, VSS1 and VSS2, and may have only one VSS signal)) to the odd-numbered driver GOA block, and the level shifter also outputs the second turn-on signal (turn-on signal ST) to the driver GOA block of the 1 ST driver module, and then the driver GOA block generates the driving signals (level logic signals) to the corresponding odd-numbered first switch transistor T1 and the corresponding fourth switch transistor T4 according to the first turn-on signal and the second turn-on signal, meanwhile, the soc or the timing controller may control the level shifter to generate different switch control signals according to different display pictures, such as a normal white picture or a special picture (H _ strip picture), and the different switch control signals are transmitted to the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, the fourth switch transistor T4, and the fifth switch transistor T5 through wires EN1-EN 3:
if the display frame is the normal frame, first, the soc or the timing controller controls the level shifter to generate a high level signal to the first transistor T1, the second transistor T2 and the third transistor T3, simultaneously generate low level signals to the fourth switch transistor T4 and the fifth switch transistor T5 (through the EN3 wire in this embodiment), that is, the switch control signal is a logic signal of "110", that is, the first switch control signal is a logic signal of "110", and at this time, the first switch transistor T1, the second switch transistor T2 and the third switch transistor T3 are all turned on, the fourth switch tube T4 and the fifth switch tube T5 are both turned off, switched to a first transmission path, that is, the driving signal is transmitted to the display module 200 through the first switch transistor T1, the second switch transistor T2 and the third switch transistor T3.
If the display frame is the special frame, firstly, the soc or the timing controller controls the level shifter to generate a high level signal to the first switch transistor T1, the fourth switch transistor T4 and the fifth switch transistor T5, and simultaneously generate a low level signal to the second switch transistor T2 and the third switch transistor T3, that is, the switch control signal is a logic signal of "101", that is, the second switch control signal is a logic signal of "101", at this time, the first switch transistor T1, the fourth switch transistor T4 and the fifth switch transistor T5 are turned on, the second switch transistor T2 and the third switch transistor T3 are all turned off, and the driving signal is switched to a second transmission path, that is, the driving signal is transmitted to the display module 200 through the fourth switch transistor T4 and the fifth switch transistor T5.
Furthermore, the invention also relates to panel charging terminal equipment, which comprises a PCB board, wherein the PCB board is provided with the panel charging circuit; since the above-mentioned detailed description of the panel charging circuit is provided, it is not described herein again.
In summary, the present invention provides a panel charging circuit and a panel charging terminal device, wherein the panel charging circuit includes: the display device comprises a plurality of driving modules, a display module, a main control module, a level output module and a plurality of switch modules; the main control module is used for outputting a first starting signal to the driving module, the level output module is used for outputting a second starting signal to the driving module and generating a corresponding switch control signal to the switch module according to different display pictures, the driving module is used for generating a driving signal to the switch module according to the first starting signal and the second starting signal, the switch module is used for switching to a corresponding path according to the switch control signal to transmit the driving signal to the display module, and the display module is used for displaying pictures according to the driving signal. According to the invention, the switch module is switched to the corresponding path transmission driving signal according to different switch control signals, so that the switching to the corresponding transmission path according to different pictures is realized, and the time for charging the panel is effectively saved.
It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.
Claims (10)
1. A panel charging circuit, comprising: the display device comprises a plurality of driving modules, a display module, a main control module, a level output module and a plurality of switch modules; the driving modules are respectively connected with the switch modules and the level output module, the driving modules are sequentially connected, the driving modules are also connected with the main control module, and each switch module is also connected with the level output module and the display module; the main control module is used for outputting a first starting signal to the driving module, the level output module is used for outputting a second starting signal to the driving module and generating a corresponding switch control signal to the switch module according to different display pictures, the driving module is used for generating a driving signal to the switch module according to the first starting signal and the second starting signal, the switch module is used for switching to a corresponding path according to the switch control signal to transmit the driving signal to the display module, and the display module is used for displaying pictures according to the driving signal.
2. The panel charging circuit of claim 1, wherein the switch module comprises: a first switching unit and a second switching unit; the first switch unit is respectively connected with the driving module, the display module and the second switch unit, and the second switch unit is also connected with the driving module and the display module; the first switch unit is used for changing the opening and closing state of the first switch unit according to the switch control signal, and the second switch unit is used for changing the opening and closing state of the second switch unit according to the switch control signal.
3. The panel charging circuit of claim 1, wherein the driving module comprises: a driver; the driver of the drive module and the driver of the drive module 2 are all connected with the switch module 1, the driver of the drive module and the driver of the drive module 4 are all connected with the switch module 2, until the 2(N-1) is the driver of the drive module and the driver of the drive module 2 are all connected with the switch module N, each driver is sequentially connected, each driver is further respectively connected with the main control module and the display module, and the driver of the drive module 1 is further connected with the level output module.
4. The panel charging circuit according to claim 1, wherein the number of the switch modules is half of the number of the driving modules, the 1 st driving module and the 2 nd driving module are both connected to the 1 st switch module, the 1 st driving module is further connected to the level output module, and the 3 rd driving module and the 4 th driving module are both connected to the 2 nd switch module until the 2(N-1) th driving module and the 2 nth driving module are both connected to the nth switch module.
5. The panel charging circuit according to claim 2, wherein the first switching unit includes: the first switching tube, the second switching tube and the third switching tube; the first pin of the first switch tube is connected with the driving module and the second switch unit respectively, the second pin of the first switch tube is connected with the second pin of the second switch tube and the first pin of the third switch tube respectively, the third pin of the first switch tube, the third pin of the second switch tube and the third pin of the third switch tube are all connected with the level output module, and the first pin of the second switch tube and the second pin of the third switch tube are all connected with the display module.
6. The panel charging circuit according to claim 5, wherein the second switching unit comprises: a fourth switching tube and a fifth switching tube; the first pin of the fourth switch tube and the first pin of the fifth switch tube are both connected with the driving module, the second pin of the fourth switch tube and the second pin of the fifth switch tube are both connected with the display module, and the third pin of the fourth switch tube and the third pin of the fifth switch tube are both connected with the level output module.
7. The panel charging circuit of claim 6, wherein the level output module comprises: a level shifter; the level shifter is respectively connected with the driving module, the third pin of the first switch tube, the third pin of the second switch tube, the third pin of the third switch tube, the third pin of the fourth switch tube and the third pin of the fifth switch tube.
8. The panel charging circuit of claim 7, wherein the first switch tube, the second switch tube and the third switch tube are all thin film transistors; the first pin of the first switching tube, the first pin of the second switching tube and the first pin of the third switching tube are source electrodes; the second pin of the first switching tube, the second pin of the second switching tube and the second pin of the third switching tube are drain electrodes; and the third pin of the first switching tube, the third pin of the second switching tube and the third pin of the third switching tube are grids.
9. The panel charging circuit according to claim 8, wherein the fourth switching transistor and the fifth switching transistor are both thin film transistors; the first pin of the fourth switching tube and the first pin of the fifth switching tube are both source electrodes; the second pin of the fourth switching tube and the second pin of the fifth switching tube are both drain electrodes; and the third pin of the fourth switching tube and the third pin of the fifth switching tube are both grids.
10. A panel charging terminal device comprising a PCB board, wherein the PCB board is provided with the panel charging circuit according to any one of claims 1 to 9.
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| CN202210081371.1A CN114362324A (en) | 2022-01-24 | 2022-01-24 | Panel charging circuit and panel charging terminal device |
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| CN202210081371.1A CN114362324A (en) | 2022-01-24 | 2022-01-24 | Panel charging circuit and panel charging terminal device |
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Cited By (1)
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| CN115188343A (en) * | 2022-07-18 | 2022-10-14 | 深圳创维－Rgb电子有限公司 | Display driving circuit, display driving method, display panel and display device |
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