CN114361218A - Substrate, display substrate, and optical detection substrate - Google Patents
Substrate, display substrate, and optical detection substrate Download PDFInfo
- Publication number
- CN114361218A CN114361218A CN202111619038.3A CN202111619038A CN114361218A CN 114361218 A CN114361218 A CN 114361218A CN 202111619038 A CN202111619038 A CN 202111619038A CN 114361218 A CN114361218 A CN 114361218A
- Authority
- CN
- China
- Prior art keywords
- layer
- transistor
- source
- drain electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The application provides a substrate base plate, a display base plate and a light detection base plate. The substrate base plate includes: a substrate; the photosensitive transistor is arranged on the substrate, and a first source drain electrode layer of the photosensitive transistor is connected to a bias signal end; the active layer of the phototransistor includes a photosensitive material; and the output circuit is arranged on the substrate and comprises one or more transistors, is connected with the second source drain electrode layer of the photosensitive transistor and the reading signal end, and is used for outputting signals to the reading signal end according to the potential of the second source drain electrode layer of the photosensitive transistor. The photoelectric detection can be realized.
Description
Technical Field
The application relates to the technical field of display, in particular to a substrate base plate, a display base plate and a light detection base plate.
Background
With the improvement of living standard, the display panel attracts more and more attention. The display panel includes an OLED display panel, a QLED display panel, and the like. The OLED display panel has a series of advantages of all-solid-state structure, self luminescence, high response speed, high brightness, full viewing angle, flexible display and the like. The QLED display panel has the advantages of narrow light-emitting spectrum, adjustable light-emitting wavelength and the like. However, the current display panel cannot realize photodetection.
Disclosure of Invention
An object of the present application is to provide a substrate base plate, a display base plate and a light detection base plate, which can realize photoelectric detection.
According to an aspect of the present application, there is provided a substrate base plate including:
a substrate;
the photosensitive transistor is arranged on the substrate, and a first source drain electrode layer of the photosensitive transistor is connected to a bias signal end; the active layer of the phototransistor includes a photosensitive material;
and the output circuit is arranged on the substrate and comprises one or more transistors, is connected with the second source drain electrode layer of the photosensitive transistor and the reading signal end, and is used for outputting signals to the reading signal end according to the potential of the second source drain electrode layer of the photosensitive transistor.
Further, the output circuit includes:
and a first source-drain electrode layer of the first reading transistor is connected with a second source-drain electrode layer of the photosensitive transistor, a second source-drain electrode layer of the first reading transistor is connected with the reading signal end, and a grid layer of the first reading transistor is connected with the scanning signal end.
Furthermore, the gate layer of the first reading transistor, the first source drain electrode layer of the phototransistor and the second source drain electrode layer of the phototransistor are arranged in the same layer.
Further, the output circuit includes:
a first source drain electrode layer of the reset transistor is connected to an initial signal end, a second source drain electrode layer of the reset transistor is connected with a second source drain electrode layer of the photosensitive transistor, and a gate electrode layer of the reset transistor is connected to a reset signal end;
a first source drain electrode layer of the source follower transistor is connected to a first power supply end, and a grid layer of the source follower transistor is connected with a second source drain electrode layer of the photosensitive transistor;
and a first source-drain electrode layer of the second reading transistor is connected with a second source-drain electrode layer of the source follower transistor, a second source-drain electrode layer of the second reading transistor is connected with the reading signal terminal, and a gate layer of the second reading transistor is connected with the scanning signal terminal.
Furthermore, the two source-drain electrode layers of the photosensitive transistor, the two source-drain electrode layers of the source follower transistor, the gate layer of the reset transistor and the gate layer of the second read transistor are arranged in the same layer; or
Two source and drain electrode layers of the photosensitive transistor, a grid layer of the source following transistor, a grid layer of the reset transistor and a grid layer of the second reading transistor are arranged in the same layer.
Further, the substrate base plate further includes:
the first pole of the energy storage capacitor is connected to a second power supply end, and the second pole of the energy storage capacitor is connected with the second source drain electrode layer of the phototransistor; the first pole of the energy storage capacitor and the grid layer of the photosensitive transistor are arranged on the same layer, and the second pole of the energy storage capacitor and the second source drain electrode layer of the photosensitive transistor are arranged on the same layer.
Further, the active layer of the phototransistor is located on a side of the gate layer of the phototransistor facing the substrate, and the gate layer of the phototransistor is made of a transparent material.
Furthermore, a light shielding layer is arranged between the active layer of the photosensitive transistor and the substrate.
According to one aspect of the application, a display substrate is provided, which comprises the substrate.
According to one aspect of the present application, there is provided a light detecting substrate comprising the substrate base plate.
According to the substrate, the display substrate and the light detection substrate, due to the fact that the active layer of the phototransistor comprises the photosensitive material, the phototransistor can generate photoproduction current under illumination so as to change the potential of the second source drain electrode layer of the phototransistor, signals are output to the reading signal end through the output circuit according to the potential of the second source drain electrode layer of the phototransistor, and therefore photoelectric detection is achieved; meanwhile, the photosensitive transistor and the transistor in the output circuit both relate to the preparation process of the transistor, the technological processes are approximately the same, and the preparation efficiency of the substrate base plate is improved.
Drawings
Fig. 1 is a schematic structural view of a combination scheme of a switching transistor and a photodiode in the related art.
Fig. 2 is a schematic view of a substrate base plate in the embodiment of the present application.
Fig. 3 is an equivalent circuit diagram of the structure shown in fig. 2.
Fig. 4 is another schematic view of the substrate base plate in the embodiment of the present application.
Fig. 5 is an equivalent circuit diagram of the structure shown in fig. 4.
Fig. 6 is a schematic view of a display substrate according to an embodiment of the present application.
Fig. 7 is a graph of leakage current versus illumination brightness for a phototransistor in accordance with an embodiment of the present application.
Description of reference numerals: 1. a substrate; 2. a light-shielding layer; 3. a buffer layer; 4. an active layer; 5. a first gate insulating layer; 6. a gate layer; 7. a first interlayer insulating layer; 8. a first source drain electrode layer; 9. a second source drain electrode layer; 10. a second gate insulating layer; 11. a second interlayer insulating layer; 12. a first conductive connection line; 13. a planarization layer; 14. an ITO top layer; 15. a third gate insulating layer; 16. a third interlayer insulating layer; 17. a second conductive connection line; 18. a third conductive connection line; 19. a conductive connection layer; 20. an additional layer of metal; 21. a first pole; 22. a second pole; 23. a gate insulating material layer; 24. a first passivation layer; 25. a photoelectric conversion layer; 26. a resin layer; 27. a second passivation layer; 28. a common electrode layer; 29. a third passivation layer; 30. a metal top layer; 31. a top layer of resin; 100. an output circuit; vbias, bias signal terminal; g1, scanning signal terminal; vini, initial signal terminal; read, Read the signal end; rst, a reset signal end; v1, power signal terminal; v2, second power supply terminal; v3, a first power supply terminal; t1, phototransistor; t2, a first read transistor; t3, reset transistor; t4, source follower transistor; t5, a second read transistor; t6, drive transistor; l0, light emitting cell.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In the related art, in the technical field of glass-based photosensitive sensors, the combination scheme of a switching transistor and a photodiode is very mature, related products are also commercially applied, but the problems that the deposition speed of the photodiode is low and the productivity/efficiency of a production line is influenced exist. Specifically, as shown in fig. 1, the combination scheme of the switching transistor and the photodiode includes a substrate 1, a gate electrode layer 6, a gate insulating material layer 23, an active layer 4, a first source drain electrode layer 8, a second source drain electrode layer 9, a first passivation layer 24, a photoelectric conversion layer 25, a resin layer 26, a second passivation layer 27, a common electrode layer 28, a third passivation layer 29, and an ITO top layer 14, and in the preparation process, at least 11 photolithography steps are required, and if a metal top layer 30 and a resin top layer 31 are added, 13 photolithography steps are required.
The embodiment of the application provides a substrate base plate. As shown in fig. 2 to 5, the substrate base board may include a substrate 1, a phototransistor T1, and an output circuit 100, wherein:
the phototransistor T1 is provided on a substrate 1. The first source-drain electrode layer 8 of the phototransistor T1 is connected to the bias signal terminal Vbias. The active layer 4 of the phototransistor T1 includes a photosensitive material. The output circuit 100 is provided on the substrate 1. The output circuit 100 includes one or more transistors. The output circuit 100 is connected to the second source/drain electrode layer 9 of the phototransistor T1 and the Read signal terminal Read, and is configured to output a signal to the Read signal terminal Read according to a potential of the second source/drain electrode layer 9 of the phototransistor T1.
In the substrate of the embodiment of the application, the active layer 4 of the phototransistor T1 includes a photosensitive material, so that the phototransistor T1 can generate a photo-generated current under illumination to change the potential of the second source/drain electrode layer 9 of the phototransistor T1, and the output circuit 100 outputs a signal to the Read signal terminal Read according to the potential of the second source/drain electrode layer 9 of the phototransistor T1, thereby implementing photoelectric detection; meanwhile, the phototransistor T1 and the transistors in the output circuit 100 both relate to the preparation process of the transistor, the process procedures are approximately the same, and the preparation efficiency of the substrate base plate is improved.
The following describes each part of the base substrate according to the embodiment of the present application in detail:
as shown in fig. 2 and 4, the substrate 1 may be a rigid substrate. The rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate) substrate. Of course, the substrate 1 may also be a flexible substrate. The flexible substrate may be a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate) substrate, or a PI (Polyimide) substrate. Furthermore, a buffer layer 3 may be provided on the substrate 1.
As shown in fig. 2 and 4, the phototransistor T1 is provided on the substrate 1. The phototransistor T1 may be a thin film transistor. The phototransistor T1 may include an active layer 4, a first gate insulating layer 5, a gate layer 6, a first interlayer insulating layer 7, a first source-drain electrode layer 8, and a second source-drain electrode layer 9. One of the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the phototransistor T1 is a source layer, and the other is a drain layer. The phototransistor T1 may have a top gate structure, or a bottom gate structure. Taking the phototransistor T1 as a top-gate structure as an example, the active layer 4 of the phototransistor T1 may be disposed on the substrate 1, and specifically, the active layer 4 of the phototransistor T1 is disposed on a side of the buffer layer 3 opposite to the substrate 1; the first gate insulating layer 5 of the phototransistor T1 covers the active layer 4 and the buffer layer 3; the gate layer 6 of the phototransistor T1 may be provided on a side of the first gate insulating layer 5 facing away from the substrate 1; the first interlayer insulating layer 7 of the phototransistor T1 covers the gate layer 6 and the first gate insulating layer 5; the first source drain electrode layer 8 and the second source drain electrode layer 9 of the phototransistor T1 are disposed on the same layer, are located on the side of the first interlayer insulating layer 7 of the phototransistor T1 facing away from the substrate 1, and are connected to the active layer 4 of the phototransistor T1.
The active layer 4 of the phototransistor T1 includes a photosensitive material to perform photoelectric conversion. The photosensitive material may be polysilicon, but is not limited thereto, and may also be germanium, gallium nitride, and the like. Taking the photosensitive material as polysilicon for example, the active layer 4 of the phototransistor T1 is a polysilicon layer. Taking the phototransistor T1 as a top gate structure as an example, the gate layer 6 of the phototransistor T1 is disposed on a side of the active layer 4 opposite to the substrate 1, and the gate layer 6 may be made of a transparent material to prevent the gate layer 6 from shielding light from entering the active layer 4, and meanwhile, a light shielding layer 2 may be disposed between the active layer 4 of the phototransistor T1 and the substrate 1 to shield light entering the active layer 4 from the substrate 1. The transparent material may be ITO or the like. The light shielding layer 2 may be disposed between the substrate 1 and the buffer layer 3, and the material of the light shielding layer 2 may be molybdenum metal or the like.
As shown in fig. 3 and 5, the first source-drain electrode layer 8 of the phototransistor T1 is connected to the bias signal terminal Vbias, and the gate electrode layer 6 of the phototransistor T1 may be connected to a power signal terminal V1. The phototransistor T1 can be turned off or on by controlling the difference between the power supply signal terminal V1 and the bias signal terminal Vbias. When the phototransistor T1 is turned off, the active layer 4 of the phototransistor T1 forms a leakage current under illumination, and the magnitude of the leakage current is positively correlated to the illumination brightness, and the larger the illumination brightness is, the larger the generated leakage current is, and the magnitude of the leakage current is linearly correlated to the illumination brightness (see fig. 7). The leakage current generated by the phototransistor T1 is the photo-generated current of the phototransistor T1. Further, the first source-drain electrode layer 8 of the phototransistor T1 may be connected to the bias signal terminal Vbias through a bias signal line.
The output circuit 100 is configured to output a signal to the Read signal terminal Read according to the potential of the second source-drain electrode layer 9 of the phototransistor T1. In an embodiment of the present application, as shown in fig. 2 and 3, the output circuit 100 may include a first reading transistor T2. The first source-drain electrode layer 8 of the first reading transistor T2 is connected to the second source-drain electrode layer 9 of the phototransistor T1, the second source-drain electrode layer 9 of the first reading transistor T2 is connected to the reading signal terminal Read, and the gate layer 6 of the first reading transistor T2 is connected to the scanning signal terminal G1. The second source-drain electrode layer 9 of the first Read transistor T2 may be connected to the Read signal terminal Read through a Read signal line, and the gate layer 6 of the first Read transistor T2 may be connected to the scan signal terminal G1 through a scan signal line. The first Read transistor T2 can be turned on under the control of the scan signal terminal G1, so that the Read signal terminal Read can Read the leakage current generated by the photo transistor T1 under illumination. It can be seen that the phototransistor T1 and the first read transistor T2 form a passive pixel Sensor.
Specifically, the first read transistor T2 may include an active layer 4, a second gate insulating layer 10, a gate layer 6, a second interlayer insulating layer 11, a first source-drain electrode layer 8, and a second source-drain electrode layer 9. One of the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the first read transistor T2 is a source layer, and the other is a drain layer. The first read transistor T2 may have a top gate structure, or may have a bottom gate structure. Taking the first read transistor T2 as an example of a top-gate structure, the active layer 4 of the first read transistor T2 may be disposed on a side of the first interlayer insulating layer 7 of the phototransistor T1 facing away from the substrate 1; the second gate insulating layer 10 of the first read transistor T2 covers the active layer 4 of the first read transistor T2 and the first interlayer insulating layer 7 of the phototransistor T1; the gate layer 6 of the first read transistor T2 may be disposed on a side of the second gate insulating layer 10 facing away from the substrate 1; the second interlayer insulating layer 11 of the first read transistor T2 covers the gate layer 6 of the first read transistor T2 and the second gate insulating layer 10; the first source drain electrode layer 8 and the second source drain electrode layer 9 of the first read transistor T2 are disposed on the same layer, on a side of the second interlayer insulating layer 11 of the first read transistor T2 facing away from the substrate 1, and connected to the active layer 4 of the first read transistor T2. The first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the phototransistor T1 may be disposed on a side of the second gate insulating layer 10 of the first reading transistor T2, which faces away from the substrate 1, and the gate layer 6 of the first reading transistor T2, the first source-drain electrode layer 8 of the phototransistor T1, and the second source-drain electrode layer 9 of the phototransistor T1 are disposed in the same layer, so that the number of times of photolithography processes may be reduced. The material of the active layer 4 of the first read transistor T2 may be polysilicon, i.e. the first read transistor T2 is a polysilicon thin film transistor, of course, the material of the active layer 4 of the first read transistor T2 may be oxide, i.e. the first read transistor T2 is an oxide thin film transistor. In addition, the second source-drain electrode layer 9 of the phototransistor T1 may be connected to the first source-drain electrode layer 8 of the first read transistor T2 via a first conductive connection line 12. The first conductive connection line 12 may be disposed on a side of the second interlayer insulating layer 11 opposite to the substrate 1, and disposed in the same layer as the read signal line. The substrate base plate may also include a planarization layer 13 and an ITO top layer 14. The planarization layer 13 may cover the first and second source- drain electrode layers 8 and 9 of the first read transistor T2, the first conductive connection line 12, the read signal line, and the second interlayer insulating layer 11 of the first read transistor T2. The ITO top layer 14 may be provided on the side of the planarization layer 13 facing away from the substrate 1.
In another embodiment of the present application, as shown in fig. 4 and 5, the output circuit 100 may include a reset transistor T3, a source follower transistor T4, and a second read transistor T5. The first source/drain electrode layer 8 of the reset transistor T3 is connected to the initial signal terminal Vini, the second source/drain electrode layer 9 of the reset transistor T3 is connected to the second source/drain electrode layer 9 of the phototransistor T1, and the gate layer 6 of the reset transistor T3 is connected to the reset signal terminal Rst. The first source-drain electrode layer 8 of the source follower transistor T4 is connected to the first power supply terminal V3, the gate layer 6 of the source follower transistor T4 is connected to the second source-drain electrode layer 9 of the phototransistor T1, the first source-drain electrode layer 8 of the second Read transistor T5 is connected to the second source-drain electrode layer 9 of the source follower transistor T4, the second source-drain electrode layer 9 of the second Read transistor T5 is connected to the Read signal terminal Read, and the gate layer 6 of the second Read transistor T5 is connected to the scan signal terminal G1. The reset transistor T3 is used for conducting the initial signal end Vini to the second source-drain electrode layer 9 of the phototransistor T1 under the control of the reset signal end Rst, so as to reset the second source-drain electrode layer 9 of the phototransistor T1. The second Read transistor T5 is used to connect the Read signal terminal Read to the second source-drain electrode layer 9 of the source follower transistor T4 under the control of the scan signal terminal G1. The source follower transistor T4 is for outputting a signal to the second read transistor T5 under the influence of the potential of the second source-drain electrode layer 9 of the phototransistor T1. It can be seen that the phototransistor T1, the reset transistor T3, the source follower transistor T4, and the second read transistor T5 form an Active Pixel Sensor (APS).
Specifically, the reset transistor T3 may include an active layer 4, a third gate insulating layer 15, a gate layer 6, a third interlayer insulating layer 16, a first source-drain electrode layer 8, and a second source-drain electrode layer 9. One of the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the reset transistor T3 is a source layer, and the other is a drain layer. The reset transistor T3 may have a top gate structure, or may have a bottom gate structure. Taking the reset transistor T3 as an example of a top gate structure, the active layer 4 of the reset transistor T3 may be disposed on a side of the first interlayer insulating layer 7 of the phototransistor T1 facing away from the substrate 1; the third gate insulating layer 15 of the reset transistor T3 covers the active layer 4 of the reset transistor T3 and the first interlayer insulating layer 7 of the phototransistor T1; the gate layer 6 of the reset transistor T3 may be disposed on a side of the third gate insulating layer 15 facing away from the substrate 1; the third interlayer insulating layer 16 of the reset transistor T3 covers the gate layer 6 of the reset transistor T3 and the third gate insulating layer 15; the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the reset transistor T3 are disposed on the same layer, are located on the side of the third interlayer insulating layer 16 of the reset transistor T3 facing away from the substrate 1, and are connected to the active layer 4 of the reset transistor T3. The first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the phototransistor T1 may be disposed on a side of the third gate insulating layer 15 of the reset transistor T3, which faces away from the substrate 1, and the gate layer 6 of the reset transistor T3, the first source-drain electrode layer 8 of the phototransistor T1, and the second source-drain electrode layer 9 of the phototransistor T1 are disposed in the same layer, so that the number of times of photolithography processes may be reduced.
The source follower transistor T4 may share the first gate insulating layer 5 and the first interlayer insulating layer 7 with the phototransistor T1. The source follower transistor T4 may have a top gate structure, but may have a bottom gate structure. The active layer 4 of the source follower transistor T4 may be disposed at the same layer as the active layer 4 of the phototransistor T1, and the material of the active layer 4 of the source follower transistor T4 may be the same as, of course, different from the material of the active layer 4 of the phototransistor T1. The gate layer 6 of the source follower transistor T4 may be provided in the same layer as the gate layer 6 of the phototransistor T1. The first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the source follower transistor T4 may be disposed at the same layer as the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the phototransistor T1. Taking the source follower transistor T4 as an example of a top gate structure, the light-shielding layer 2 may be provided between the active layer 4 of the source follower transistor T4 and the substrate 1. In order to reduce the trace resistance, the gate layer 6 of the source follower transistor T4 may also be provided with an additional metal layer 20. The source follower transistor T4 may further include a conductive connection layer 19, and the conductive connection layer 19 may be disposed on a side of the third gate insulating layer 15 facing away from the substrate 1, and disposed in the same layer as the two source-drain electrode layers of the source follower transistor T4. The conductive connection layer 19 may be connected to the gate layer 6 of the source follower transistor T4, and in particular, the conductive connection layer 19 may be connected to the additional metal layer 20 of the source follower transistor T4.
The second read transistor T5 may share the third gate insulating layer 15 and the third interlayer insulating layer 16 with the reset transistor T3. The second reading transistor T5 may have a top gate structure, or may have a bottom gate structure. The active layer 4 of the second read transistor T5 may be disposed at the same layer as the active layer 4 of the reset transistor T3. The gate layer 6 of the second read transistor T5 may be disposed at the same layer as the gate layer 6 of the reset transistor T3. The first source/drain electrode layer 8 and the second source/drain electrode layer 9 of the second read transistor T5 may be disposed in the same layer as the first source/drain electrode layer 8 and the second source/drain electrode layer 9 of the reset transistor T3.
Further, the second source-drain electrode layer 9 of the reset transistor T3, the second source-drain electrode layer 9 of the phototransistor T1, and the gate layer 6 of the source follower transistor T4 may be connected through a second conductive connection line 17. Wherein the second conductive connection line 17 may be connected to the conductive connection layer 19 of the source follower transistor T4. The second source-drain electrode layer 9 of the source follower transistor T4 may be connected to the first source-drain electrode layer 8 of the second read transistor T5 through a third conductive connection line 18. The second conductive connection line 17, the third conductive connection line 18 and the read signal line may be disposed in the same layer, and are disposed on a side of the third interlayer insulating layer 16 opposite to the substrate 1. The planarization layer 13 may cover the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the second read transistor T5, the first source-drain electrode layer 8 and the second source-drain electrode layer 9 of the reset transistor T3, the second conductive connection line 17, the third conductive connection line 18, the read signal line, and the third interlayer insulating layer 16. The ITO top layer 14 may be provided on the side of the planarization layer 13 facing away from the substrate 1.
As shown in fig. 2 to 5, the substrate of the present application may further include an energy storage capacitor C. The first electrode 21 of the energy storage capacitor C may be connected to the second power source terminal V2, and the second electrode 22 of the energy storage capacitor C is connected to the second source/drain electrode layer 9 of the phototransistor T1, so as to store the potential of the second source/drain electrode layer 9 of the phototransistor T1. The first electrode 21 of the storage capacitor C is disposed in the same layer as the gate layer 6 of the phototransistor T1. The second electrode 22 of the storage capacitor C is disposed in the same layer as the second source/drain electrode layer 9 of the phototransistor T1.
The embodiment of the application also provides a display substrate. As shown in fig. 6, the display substrate may include the substrate described in any of the above embodiments. The display substrate may be an OLED display substrate. The display substrate may include a driving transistor T6 and a light emitting cell L0. The driving transistor T6 may share the buffer layer 3, the first gate insulating layer 5, and the first interlayer insulating layer 7 with the phototransistor T1. The active layer 4 of the driving transistor T6 may be disposed at the same layer as the active layer 4 of the photo transistor T1. The gate layer 6 of the driving transistor T6 may be disposed at the same layer as the gate layer 6 of the photo transistor T1. The first source/drain electrode layer 8 and the second source/drain electrode layer 9 of the driving transistor T6 may be disposed in the same layer as the first source/drain electrode layer 8 and the second source/drain electrode layer 9 of the phototransistor T1.
Note that each of the transistors may be an N-type thin film transistor, and may be a P-type thin film transistor. The material of the active layer 4 of each transistor may be polysilicon, that is, a polysilicon thin film transistor, and of course, the material of the active layer 4 of each transistor may also be oxide.
The embodiment of the application also provides an optical detection substrate. The light detecting substrate may include the substrate described in any of the above embodiments.
The substrate, the display substrate and the optical detection substrate of the embodiment of the present application belong to the same inventive concept, and the description of the relevant details and the beneficial effects can be referred to each other and are not repeated.
Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (10)
1. A substrate base plate, comprising:
a substrate;
the photosensitive transistor is arranged on the substrate, and a first source drain electrode layer of the photosensitive transistor is connected to a bias signal end; the active layer of the phototransistor includes a photosensitive material;
and the output circuit is arranged on the substrate and comprises one or more transistors, is connected with the second source drain electrode layer of the photosensitive transistor and the reading signal end, and is used for outputting signals to the reading signal end according to the potential of the second source drain electrode layer of the photosensitive transistor.
2. The substrate of claim 1, wherein the output circuit comprises:
and a first source-drain electrode layer of the first reading transistor is connected with a second source-drain electrode layer of the photosensitive transistor, a second source-drain electrode layer of the first reading transistor is connected with the reading signal end, and a grid layer of the first reading transistor is connected with the scanning signal end.
3. The substrate according to claim 2, wherein a gate layer of the first read transistor, a first source drain electrode layer of the phototransistor, and a second source drain electrode layer of the phototransistor are disposed in the same layer.
4. The substrate of claim 1, wherein the output circuit comprises:
a first source drain electrode layer of the reset transistor is connected to an initial signal end, a second source drain electrode layer of the reset transistor is connected with a second source drain electrode layer of the photosensitive transistor, and a gate electrode layer of the reset transistor is connected to a reset signal end;
a first source drain electrode layer of the source follower transistor is connected to a first power supply end, and a grid layer of the source follower transistor is connected with a second source drain electrode layer of the photosensitive transistor;
and a first source-drain electrode layer of the second reading transistor is connected with a second source-drain electrode layer of the source follower transistor, a second source-drain electrode layer of the second reading transistor is connected with the reading signal terminal, and a gate layer of the second reading transistor is connected with the scanning signal terminal.
5. The substrate according to claim 4, wherein the two source-drain electrode layers of the phototransistor, the two source-drain electrode layers of the source follower transistor, the gate layer of the reset transistor, and the gate layer of the second read transistor are disposed in the same layer; or
Two source and drain electrode layers of the photosensitive transistor, a grid layer of the source following transistor, a grid layer of the reset transistor and a grid layer of the second reading transistor are arranged in the same layer.
6. The substrate base of claim 1, further comprising:
the first pole of the energy storage capacitor is connected to a second power supply end, and the second pole of the energy storage capacitor is connected with the second source drain electrode layer of the phototransistor; the first pole of the energy storage capacitor and the grid layer of the photosensitive transistor are arranged on the same layer, and the second pole of the energy storage capacitor and the second source drain electrode layer of the photosensitive transistor are arranged on the same layer.
7. The substrate of claim 1, wherein the active layer of the phototransistor is located on a side of a gate layer of the phototransistor facing the substrate, the gate layer of the phototransistor being a transparent material.
8. The substrate according to claim 7, wherein a light-shielding layer is provided between the active layer of the phototransistor and the substrate.
9. A display substrate comprising the substrate according to any one of claims 1 to 8.
10. A light-detecting substrate comprising the substrate according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111619038.3A CN114361218A (en) | 2021-12-27 | 2021-12-27 | Substrate, display substrate, and optical detection substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111619038.3A CN114361218A (en) | 2021-12-27 | 2021-12-27 | Substrate, display substrate, and optical detection substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114361218A true CN114361218A (en) | 2022-04-15 |
Family
ID=81103723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111619038.3A Pending CN114361218A (en) | 2021-12-27 | 2021-12-27 | Substrate, display substrate, and optical detection substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114361218A (en) |
-
2021
- 2021-12-27 CN CN202111619038.3A patent/CN114361218A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108987455B (en) | Array substrate for display panel and display panel | |
| JP7428845B2 (en) | Imaging devices, display devices, electronic equipment | |
| US11462587B2 (en) | Display panel and fabricating method thereof | |
| WO2019218831A1 (en) | Array substrate, and display device and brightness calibration method therefor | |
| CN108646949B (en) | Photoelectric detection circuit and method, array substrate, display panel and fingerprint identification method | |
| WO2018218936A1 (en) | Pixel circuit, driving method therefor, and display panel | |
| CN112055893B (en) | Display panel and manufacturing method thereof | |
| US11232750B2 (en) | Display substrate, display panel, and manufacturing method and driving method of display substrate | |
| WO2021184907A1 (en) | Display substrate, preparation method therefor, and display device | |
| US11887400B2 (en) | Fingerprint identification display substrate and method of use thereof, and display panel | |
| WO2020062825A1 (en) | Photodetector, display substrate including photodetector, method of fabricating photodetector, and display panel | |
| US11233098B2 (en) | Display array substrate, method for manufacturing the same and display including the same | |
| CN108735782B (en) | Vertical integrated structure of photoelectric sensor based on OLED | |
| US11334195B2 (en) | Optical detection apparatus | |
| CN109378333B (en) | Display panel and display device | |
| US20050179964A1 (en) | Thin film phototransistor, active matrix substrate using the phototransistor, and image scanning device using the substrate | |
| WO2015014077A1 (en) | Organic light-emitting diode pixel circuit, method for driving same and display apparatus | |
| WO2015014146A1 (en) | Pixel circuit, organic electroluminescence display panel, and display apparatus | |
| US11985874B2 (en) | Display substrate and display device | |
| US20200312273A1 (en) | Detection substrate, display panel and display apparatus | |
| US8456460B2 (en) | Sensor element and method of driving sensor element, and input device, display device with input function and communication device | |
| CN114361218A (en) | Substrate, display substrate, and optical detection substrate | |
| JP5848586B2 (en) | I / O device | |
| US20240177665A1 (en) | Display substrate and display device | |
| WO2022227043A1 (en) | Display substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |