CN114337474B - Drive control circuit and motor control circuit - Google Patents
Drive control circuit and motor control circuit Download PDFInfo
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- CN114337474B CN114337474B CN202111561229.9A CN202111561229A CN114337474B CN 114337474 B CN114337474 B CN 114337474B CN 202111561229 A CN202111561229 A CN 202111561229A CN 114337474 B CN114337474 B CN 114337474B
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Abstract
The application provides a drive control circuit and motor control circuit, relates to power technical field. Wherein, the drive control circuit includes: the device comprises a direct current power supply, a driving circuit, a data analysis circuit and a main control circuit. The direct current power supply is used for supplying power to the drive circuit; the drive circuit includes: the MOS tube driving circuit is used for outputting a driving signal to the MOS tube; the MOS tube is used for outputting periodic current signals to a load; the data analysis circuit is used for determining an ideal current value at the current moment according to a predetermined ideal current signal, and the ideal current signal is determined according to a current signal output by the MOS tube; the main control circuit is used for determining a target gate voltage of the MOS tube and adjusting the gate voltage of the MOS tube according to the target gate voltage, wherein the target gate voltage is determined according to an ideal current value. The technical scheme provided by the application can reduce ripples under the condition of not changing the switching frequency.
Description
Technical Field
The application relates to the technical field of power supplies, in particular to a drive control circuit and a motor control circuit.
Background
In the field of modern power supply technology, the application occasions of linear power supplies are gradually reduced, but in some special occasions, the linear power supplies still have application, and the ripple phenomenon exists, so that the low-ripple control technology is still an important direction in the branch field of power supply technology development.
At present, ripple is mainly reduced by an ultra high switching frequency, but the ripple reduction is limited due to the limitation of the maximum frequency of the switching device.
Disclosure of Invention
In view of the above, the present application provides a drive control circuit and a motor control circuit for reducing power supply ripple without changing a switching frequency.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides a drive control circuit, including:
the device comprises a direct current power supply, a driving circuit, a data analysis circuit and a main control circuit;
the direct current power supply is electrically connected with the driving circuit and used for supplying power to the driving circuit;
the drive circuit includes: a Metal-Oxide-Semiconductor (MOS) transistor driving circuit and an MOS transistor, wherein the MOS transistor driving circuit is electrically connected to the dc power supply and the MOS transistor, respectively, and is configured to output a driving signal to the MOS transistor; the MOS tube is used for outputting a periodic current signal to a load;
the data analysis circuit is electrically connected with the driving circuit and used for determining an ideal current value at the current moment according to a predetermined ideal current signal, and the ideal current signal is determined according to a current signal output by the MOS tube;
the main control circuit is respectively electrically connected with the data analysis circuit and the driving circuit and is used for determining a target gate voltage of the MOS tube and adjusting the gate voltage of the MOS tube according to the target gate voltage, wherein the target gate voltage is determined according to the ideal current value.
As an optional implementation manner of the embodiment of the present application, the driving control circuit further includes a sampling circuit, and the sampling circuit is electrically connected to the driving circuit and the data analysis circuit, and is configured to collect a current signal of the driving circuit and output the collected current signal to the data analysis circuit.
As an optional implementation manner of the embodiment of the present application, the current signal is a sine wave signal, and the data analysis circuit is further configured to:
and smoothing the current signal of at least one sine period output by the sampling circuit to obtain the ideal current signal.
As an optional implementation manner of the embodiment of the present application, the data analysis circuit is specifically configured to:
the ideal current value at the current moment is periodically determined according to the predetermined ideal current signal.
As an optional implementation manner of the embodiment of the present application, the main control circuit is specifically configured to:
acquiring drain-source voltage between the source electrode and the drain electrode of the MOS tube;
determining an ideal on-state resistance value of the MOS tube according to the ideal current value and the drain-source voltage;
and determining the target gate voltage of the MOS tube according to the ideal on-state resistance value of the MOS tube.
As an optional implementation manner of the embodiment of the present application, the data analysis circuit is further configured to obtain a current value of the driving circuit at the current time, and determine a current difference value according to the current value and the ideal current value;
the main control circuit is specifically used for determining the target gate voltage of the MOS tube according to the current difference.
As an optional implementation manner of the embodiment of the present application, the main control circuit is specifically configured to:
acquiring drain-source voltage between the source electrode and the drain electrode of the MOS tube;
determining the on-state resistance difference value of the MOS tube according to the current difference value and the drain-source voltage;
acquiring an on-state resistance value of the MOS tube at the current moment, and determining an ideal on-state resistance value according to the on-state resistance value and the on-state resistance difference value;
and determining the target gate voltage of the MOS tube according to the ideal on-state resistance value of the MOS tube.
As an optional implementation manner of the embodiment of the present application, the MOS transistor includes a plurality of MOS transistors, and the main control circuit is specifically configured to: and adjusting the gate voltage of one or two MOS tubes according to the target gate voltage.
As an optional implementation manner of the embodiment of the present application, the MOS transistor in the driving circuit and the load form an H-bridge circuit.
In a second aspect, an embodiment of the present application provides a motor control circuit, which includes the drive control circuit and a motor, where the motor is electrically connected to the drive control circuit.
In the drive control circuit provided by the application, the ideal current value at the current moment can be determined according to the predetermined ideal current signal, the target gate voltage of the MOS tube of the drive circuit can be determined according to the ideal current value, and the gate voltage of the MOS tube can be adjusted according to the target gate voltage, so that the current output by the MOS tube can be closer to the ideal current by adjusting the gate voltage of the MOS tube, and the ripple of a linear power supply can be reduced under the condition of not changing the switching frequency of a switching device; on the other hand, because the technical scheme that this application provided can reduce the ripple of linear power supply under the condition that does not change switching device switching frequency, consequently, the technical scheme that this application provided can reduce switching frequency under the condition that reaches the same ripple reduction effect to can reduce the ripple that switching action itself produced of switching device, and can reduce because switching speed is too high, the switching device generates heat seriously, the switching device damaged condition that leads to, promote electrical power generating system's reliability.
Drawings
Fig. 1 is a schematic structural diagram of a driving control circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an H-bridge circuit provided in an embodiment of the present application;
fig. 3 is a schematic flowchart of a method for determining a target gate voltage of a MOS transistor according to an embodiment of the present application;
fig. 4 is a schematic flowchart of another method for determining a target gate voltage of a MOS transistor according to an embodiment of the present disclosure.
Detailed Description
At present, the existing method for reducing the ripple mainly reduces the ripple through an ultrahigh switching frequency, but is limited by the maximum frequency of a switching device, the ripple is reduced limitedly, the switching action of the switching device also generates the ripple, and in addition, the switching speed is too high, the device generates heat seriously, the switching device is easy to damage, and the reliability of a power supply system is reduced.
In view of the above technical problems, an embodiment of the present application provides a driving control circuit, which mainly determines an ideal current signal, determines a target gate voltage of an MOS transistor in the driving control circuit based on the ideal current signal, and further adjusts the gate voltage of the MOS transistor, so that an actual current value is closer to an ideal current value, thereby achieving an effect of reducing ripples.
The technical solution of the present application will be described in detail below with specific examples. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a schematic diagram of a driving control circuit provided in an embodiment of the present application, and as shown in fig. 1, the driving control circuit provided in the embodiment of the present application may include: the device comprises a direct current power supply 100, a driving circuit 200, a sampling circuit 300, a data analysis circuit 400 and a main control circuit 500.
The dc power supply 100 is electrically connected to the driving circuit 200 for supplying power to the driving circuit 200.
The dc power supply 100 may be obtained by transforming and rectifying ac power, and specifically, may be obtained by stepping down ac power through a transformer, and then rectifying the ac power through a rectifying circuit to obtain pulsed dc power; after the pulse direct current is obtained, a filter circuit and a voltage stabilizing circuit can be adopted for filtering and stabilizing voltage, and the direct current with micro ripple current is obtained.
The driving circuit 200 may include: the MOS transistor driving circuit 210 and the MOS transistor 220 are electrically connected to the dc power supply 100 and the MOS transistor 220, respectively, and the MOS transistor driving circuit 210 can output a driving signal to the MOS transistor 220 to control the on/off state of the MOS transistor 220, which can be specifically controlled by Pulse Width Modulation (PWM) or the like. The MOS transistor 220 is used for outputting a periodic current signal to the load. The MOS transistor 220 may include a plurality of MOS transistors, and the MOS transistor 220 may be an enhancement N-channel MOS transistor 220 or an enhancement P-channel MOS transistor 220.
The MOS transistor 220 in the driving circuit 200 may form an H-bridge circuit with the load to improve the flexibility of load control. The load may be a motor, a relay, or the like, and in the embodiment of the present application, the motor is taken as an example for illustration.
Fig. 2 is a schematic structural diagram of an H-bridge circuit provided in the embodiment of the present application, and as shown in fig. 2, the H-bridge circuit provided in the embodiment of the present application may include: 4 MOS transistors 220 and one motor. The 4 MOS pipes are Q1, Q2, Q3 and Q4 respectively, wherein Q1 is electrically connected with Q3 and a motor respectively, Q2 is electrically connected with Q4 and the motor respectively, Q3 is electrically connected with Q1 and the motor respectively, and Q4 is electrically connected with Q2 and the motor respectively.
When Q1 and Q4 are conducted, current passes through the motor from the positive pole of the power supply to the right through Q1 and then returns to the negative pole of the power supply through Q4, and the current drives the motor to rotate clockwise. When Q2 and Q3 are conducted, current passes through the motor from the positive pole of the power supply from right to left through Q2 and then returns to the negative pole of the power supply through Q3, and the current drives the motor to rotate anticlockwise. In addition, a PWM control mode can be adopted, and the rotating speed of the motor can be adjusted by adjusting the duty ratio.
The sampling circuit 300 is electrically connected To the driving circuit 200 and the data analysis circuit 400, respectively, and is configured To collect a current signal of the driving circuit 200, specifically collect the current signal of the driving circuit 200 through analog-To-Digital (AD) conversion, and then output the collected current signal To the data analysis circuit 400.
The data analysis circuit 400 may perform a smoothing process on the current signal of at least one sinusoidal cycle output by the sampling circuit 300 to obtain an ideal current signal. After determining the ideal current signal, the data analysis circuit 400 may determine the ideal current value at the present time based on the ideal current signal.
As a possible implementation manner, the above process of determining the ideal current signal may be implemented by: the sampling circuit 300 samples the current information of the driving circuit 200, and transmits the acquired current information to the data analysis circuit 400, and the data analysis circuit 400 performs smoothing on a current signal of a sinusoidal period, determines the smoothed current signal as an ideal sinusoidal period current signal, and further obtains an ideal current signal.
As another possible implementation manner, the above-mentioned process of determining the ideal current signal can also be implemented by: the sampling circuit 300 samples the current information of the driving circuit 200, and transmits the acquired current information to the data processing circuit, and the data processing circuit performs smoothing processing on the current signals of a plurality of sinusoidal cycles, calculates an average sinusoidal cycle current signal of the smoothed current signals of the plurality of sinusoidal cycles, and determines the average sinusoidal cycle current signal as an ideal sinusoidal cycle current signal, thereby obtaining an ideal current signal.
The ideal current signal may include an ideal sinusoidal periodic current signal, and correspondingly, when the ideal current value at the current moment is determined, the phase of the current signal at the current moment may be determined according to the current signal historically acquired by the sampling circuit 300, and the current value corresponding to the phase in the ideal current signal is determined as the ideal current value at the current moment.
The ideal current signal may also include a plurality of ideal sinusoidal periodic current signals, and correspondingly, when determining the ideal current value at the current time, the ideal current value at the current time may be determined according to a relationship between the current signal collected by the sampling circuit 300 in the history and the current time, and a corresponding relationship between the current signal collected in the history and the ideal current signal.
The data analysis circuit 400 may periodically determine the ideal current value according to a preset time interval, where the time interval may be set as needed, and the embodiment is not limited thereto.
The main control circuit 500 is electrically connected to the data analysis circuit 400 and the driving circuit 200, respectively, and is configured to determine a target gate voltage of the MOS transistor 220 and adjust the gate voltage of the MOS transistor 220 according to the target gate voltage.
The main control circuit 500 may determine the target gate voltage of the MOS transistor 220 by, but not limited to, the following two ways:
first, referring to fig. 3, fig. 3 is a flowchart illustrating a method for determining a target gate voltage of a MOS transistor according to an embodiment of the present application, as shown in fig. 3, the method may include the following steps:
and S110, acquiring a drain-source voltage between the source and the drain of the MOS tube 220.
Specifically, the source voltage and the drain voltage of the MOS transistor 220 may be obtained by an AD converter, and the difference between the source voltage and the drain voltage may be used as the drain-source voltage.
And S120, determining an ideal on-state resistance value of the MOS tube 220 according to the ideal current value and the drain-source voltage.
After the ideal current value and the drain-source voltage are obtained, the ideal current value is divided by the drain-source voltage, and then the ideal on-state resistance value can be obtained.
And S130, determining the target gate voltage of the MOS tube 220 according to the ideal on-state resistance value of the MOS tube 220.
Specifically, the main control circuit 500 may store a corresponding relationship between the on-resistance and the gate voltage of each MOS transistor 220 in the driving circuit 200 in advance, and the main control circuit 500 may determine a gate voltage corresponding to the ideal on-resistance according to the corresponding relationship, where the gate voltage is a target gate voltage of the MOS transistor 220.
Referring to fig. 4, fig. 4 is another flow chart of a method for determining a target gate voltage of a MOS transistor according to an embodiment of the present disclosure, as shown in fig. 4, the method may include the following steps:
and S210, acquiring a current difference value between the ideal current value and the current value at the current moment.
The current difference may be determined by the data analysis circuit 400 according to the current value and the ideal current value at the current time, or the main control circuit 500 first obtains the current value and the ideal current value at the current time from the data analysis circuit 400, and then determines the current difference according to the obtained current value and the ideal current value at the current time.
Specifically, the current difference may be a difference obtained by subtracting an ideal current value from a current value at the current time, or a difference obtained by subtracting a current value from an ideal current value at the current time, which is exemplified by subtracting a current value from an ideal current value at the current time.
And S220, acquiring a drain-source voltage between the source and the drain of the MOS transistor 220.
This step is similar to step S110 in the embodiment shown in fig. 3, and for specific description, reference may be made to the description in step S110, which is not described herein again.
And S230, determining the on-state resistance difference value of the MOS tube 220 according to the current difference value and the drain-source voltage.
And after the current difference value and the drain-source voltage are obtained, dividing the drain-source voltage by the current difference value to obtain an on-state resistance difference value.
And S240, acquiring the on-state resistance value of the MOS tube 220 at the current moment.
Specifically, the on-state resistance value of the MOS transistor 220 at the present moment may be obtained according to the current value and the drain-source voltage at the present moment.
And S250, determining an ideal on-state resistance value according to the on-state resistance value and the on-state resistance difference value.
Specifically, the on-resistance difference is subtracted from the on-resistance to obtain the ideal on-resistance.
And S260, determining the target gate voltage of the MOS transistor 220 according to the ideal on-state resistance value of the MOS transistor 220.
This step is similar to step S130 in the embodiment shown in fig. 3, and for specific description, reference may be made to the description in step S130, which is not described herein again.
It should be noted that, in this embodiment, there is no strict time sequence execution relationship between the steps, and the execution sequence between the steps is not particularly limited in this embodiment.
Specifically, the main control circuit 500 may directly adjust the gate voltage of the MOS transistor 220, or may adjust the gate voltage of the MOS transistor 220 through the MOS transistor driving circuit 210.
In the adjustment, the gate voltage of one of the MOS transistors 220 may be adjusted, and the gate voltages of two or more of the MOS transistors 220 may also be adjusted.
It is to be understood that the circuit module illustrated in the embodiment of the present application does not constitute a specific limitation to the drive control circuit. In other embodiments of the present application, the drive control circuit may include more or fewer circuit blocks than shown, or combine some circuit blocks, or split some circuit blocks. The illustrated circuit blocks may be implemented in hardware, software, or a combination of software and hardware.
The driving control circuit provided in this embodiment may determine an ideal current value at the current moment according to a predetermined ideal current signal, determine a target gate voltage of the MOS transistor 220 of the driving circuit 200 according to the ideal current value, and adjust the gate voltage of the MOS transistor 220 according to the target gate voltage, so that the current output by the MOS transistor 220 may be closer to the ideal current by adjusting the gate voltage of the MOS transistor 220, and thus the ripple of the linear power supply may be reduced without changing the switching frequency of the switching device; on the other hand, because the technical scheme that this application provided can reduce the ripple of linear power supply under the condition that does not change switching device switching frequency, consequently, the technical scheme that this application provided can reduce switching frequency under the condition that reaches the same ripple reduction effect to can reduce the ripple that switching device's switching action itself produced, and can reduce because switching speed is too high, switching device generates heat seriously, the switching device damage's that leads to the condition, promote electrical power generating system's reliability.
Based on the same inventive concept, the embodiment of the application also provides a motor control circuit, which comprises a drive control circuit and a motor, wherein the motor is electrically connected with the drive control circuit.
In this embodiment, the specific structure, working principle and technical effect of the motor control circuit can be referred to the embodiment shown in fig. 1, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The naming or numbering of the steps appearing in the present application does not mean that the steps in the method flow have to be executed in the chronological/logical order indicated by the naming or numbering, and the named or numbered process steps may be executed in a modified order depending on the technical purpose to be achieved, as long as the same or similar technical effects are achieved.
In the description of the present application, "/" indicates a relationship in which the objects linked before and after are "or", for example, a/B may indicate a or B; in the present application, "and/or" is only an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural.
Also, in the description of the present application, "a plurality" means two or more than two unless otherwise specified. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, described with reference to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (9)
1. A drive control circuit, comprising:
the device comprises a direct current power supply, a driving circuit, a data analysis circuit and a main control circuit;
the direct current power supply is electrically connected with the driving circuit and used for supplying power to the driving circuit;
the drive circuit includes: the MOS tube driving circuit is respectively electrically connected with the direct current power supply and the MOS tube and is used for outputting a driving signal to the MOS tube; the MOS tube is used for outputting a periodic current signal to a load;
the data analysis circuit is electrically connected with the driving circuit and used for determining an ideal current value at the current moment according to a predetermined ideal current signal, and the ideal current signal is determined according to a current signal output by the MOS tube;
the main control circuit is respectively electrically connected with the data analysis circuit and the drive circuit and is used for determining an ideal on-state resistance value of the MOS tube, determining a target gate voltage of the MOS tube according to the ideal on-state resistance value and adjusting the gate voltage of the MOS tube according to the target gate voltage, wherein the ideal on-state resistance value is determined according to the ideal current value and the drain-source voltage between the source electrode and the drain electrode of the MOS tube.
2. The circuit of claim 1, further comprising a sampling circuit electrically connected to the driving circuit and the data analysis circuit, respectively, for collecting a current signal of the driving circuit and outputting the collected current signal to the data analysis circuit.
3. The circuit of claim 2, wherein the current signal is a sine wave signal, the data analysis circuit further configured to:
and smoothing the current signal of at least one sine period output by the sampling circuit to obtain the ideal current signal.
4. The circuit of claim 1, wherein the data analysis circuit is specifically configured to:
the ideal current value at the current moment is periodically determined according to the predetermined ideal current signal.
5. The circuit of claim 1, wherein the data analysis circuit is further configured to obtain a current value of the driving circuit at a current moment, and determine a current difference value according to the current value and the ideal current value;
the main control circuit is specifically used for determining an ideal on-state resistance value of the MOS tube according to the current difference value and the drain-source voltage.
6. The circuit of claim 5, wherein the master circuit is specifically configured to:
determining the on-state resistance difference value of the MOS tube according to the current difference value and the drain-source voltage;
and acquiring the on-state resistance value of the MOS tube at the current moment, and determining an ideal on-state resistance value according to the on-state resistance value and the on-state resistance difference value.
7. The circuit of claim 1, wherein the MOS transistors comprise a plurality of MOS transistors, and wherein the master circuit is specifically configured to: and adjusting the gate voltage of one or two MOS tubes according to the target gate voltage.
8. The circuit according to any one of claims 1-7, wherein the MOS transistor of the driving circuit and the load form an H-bridge circuit.
9. A motor control circuit, comprising: the drive control circuit and the motor according to any one of claims 1 to 8, the motor being electrically connected to the drive control circuit.
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| CN202111561229.9A CN114337474B (en) | 2021-12-16 | 2021-12-16 | Drive control circuit and motor control circuit |
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| CN202111561229.9A CN114337474B (en) | 2021-12-16 | 2021-12-16 | Drive control circuit and motor control circuit |
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