CN114329523A - Spiflash encryption and decryption interface and read-write method thereof - Google Patents
Spiflash encryption and decryption interface and read-write method thereof Download PDFInfo
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Abstract
The invention discloses an spi flash encryption and decryption interface, which comprises: the control unit is used for receiving a bus read/write signal, judging whether a target address of the read/write signal hits a key stream of the current encryption and decryption operation, and determining whether to directly use the current key stream or start the key expansion unit to carry out operation according to a hit result; the key expansion unit is used for generating a key stream corresponding to the target address; the arithmetic unit is used for carrying out XOR operation on the plaintext data and the key stream corresponding to the target address under the condition of data writing to obtain ciphertext data; and in the case of data reading, performing exclusive-or operation based on the ciphertext data and the key stream corresponding to the target address to acquire plaintext data. The encryption and decryption interface designed by the invention can protect the confidentiality of codes and data in the external flash and transparently decrypt the read data in real time, so that a CPU (central processing unit) can read the encrypted data in the off-chip flash in real time and efficiently run the encrypted codes in the off-chip flash.
Description
Technical Field
The invention belongs to the technical field of electronic chip data encryption, and particularly relates to an spi flash encryption and decryption interface and a data writing and reading method.
Background
In a system on chip, the capacity of the on-chip flash is limited, and in some applications, the code needs to be put into an off-chip flash storage or even directly executed from the off-chip flash. Off-chip flash is much weaker in resistance to attacks than on-chip flash. The off-chip flash generally has no protection of hardware level, and as long as the material number of the off-chip flash is known, the read-write time sequence of the off-chip flash can be checked, and the content in the off-chip flash can be easily read. The conventional method is to encrypt the code and then place the encrypted code on an off-chip flash, so that even if someone reads out the ciphertext code inside, the valid information of the code cannot be obtained as long as the key is not available.
In the prior art, when the MCU executes the off-chip encryption code, it needs to invoke the OSPI driver first to read the ciphertext code, for example, put it into the SRAM, then decrypt it using the software or hardware of the MCU to restore the plaintext code to another area of the SRAM, and finally the MCU executes the plaintext code from the SRAM. But this solution is inefficient.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide an spi flash encryption/decryption interface and a data writing and reading method, where the spi flash encryption/decryption interface can significantly improve the efficiency of data writing and reading.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an spi flash encryption and decryption interface comprising:
the control unit is used for receiving a bus read/write signal and judging whether a target address of the bus read/write signal hits a key stream of the current encryption and decryption operation;
the key expansion unit is used for generating a key stream corresponding to the target address;
the arithmetic unit is used for carrying out XOR operation on the plaintext data and the key stream corresponding to the target address under the condition of data writing to obtain ciphertext data; and in the case of data reading, performing exclusive-or operation based on the ciphertext data and the key stream corresponding to the target address to acquire plaintext data.
The control unit automatically judges whether a key stream of the current encryption operation is hit or not for a target address in a read/write signal sent by the bus, and under the condition of hit, the arithmetic unit carries out XOR on ciphertext/plaintext data and the key stream corresponding to the target address to obtain a corresponding plaintext/ciphertext; and under the condition of no hit, the key expansion unit generates a key stream corresponding to the target address for the operation unit to call.
Further, the key expansion unit performs key expansion based on the configured key and the initialization value to obtain the key stream corresponding to the target address. And under the condition of first writing/reading, the target address is filled in an initialization vector to obtain an initialization value, and the key expansion unit performs key expansion on the basis of the configured key and the initialization value to obtain the key stream corresponding to the target address.
Further, the key expansion unit further includes an internal counter, and in the process of reading/writing to the continuous addresses, the key expansion unit performs encryption operation based on the internal counter and the configured key to obtain the key stream corresponding to the target address. Under the condition that the data is not written in/read for the first time, each group corresponds to a counter which is gradually accumulated, the address of the key stream is automatically increased through the counter, and the target address and the initialization value do not need to be written in each time. And the key expansion unit carries out encryption operation based on the counter and the configured key so as to obtain the key stream with continuous addresses.
Based on the same conception, the invention also provides an spi flash data writing method, which comprises the following steps:
the system bus sends a write signal to the control unit and waits for an operation end signal;
the control unit judges whether to hit in the key stream range of the current encryption operation based on the target address in the write signal;
when a target address in the write signal hits a key stream of the current encryption operation, carrying out exclusive OR on the basis of plaintext data in the write signal and the key stream corresponding to the target address in the write signal to obtain ciphertext data, and writing the ciphertext data into the target address of the write signal in spi flash;
and under the condition that the target address in the write signal does not hit the key stream of the current encryption operation, feeding back a waiting signal to a system bus, starting a key expansion unit to generate the key stream corresponding to the target address in the write signal, carrying out XOR on the plaintext data in the write signal and the key stream corresponding to the target address in the write signal to obtain ciphertext data, and writing the ciphertext data into the target address of the write signal in the spi flash.
Further, the method for generating the key stream corresponding to the target address in the write signal by the key expansion unit includes:
filling an spi flash starting address, an spi flash ending address, version information and target address information into an initialization vector;
and carrying out encryption operation on the initialization vector based on the configured key so as to obtain the key stream corresponding to the target address.
And under the condition of first writing, the target address is filled in an initialization vector to obtain an initialization value, and the key expansion unit performs key expansion on the basis of the configured key and the initialization value to obtain the key stream corresponding to the target address.
Further, the method for generating the key stream corresponding to the target address in the write signal by the key expansion unit includes:
and under the condition of writing to the continuous addresses, the key expansion unit performs encryption operation based on the counter and the configured key to acquire the key stream corresponding to the target address.
When the address is not written into for the first time but written into the continuous address, the key expansion unit comprises an internal counter, each group corresponds to a counter which is accumulated successively, the key stream address is automatically increased through the counter, and the target address and the initialization value do not need to be written into each time. And the key expansion unit carries out encryption operation based on the counter and the configured key so as to obtain the key stream with continuous addresses. Based on the same conception, the invention also provides an spi flash data reading method, which comprises the following steps:
the system bus sends a reading signal to the control unit and waits for returning plaintext data of a target address;
reading ciphertext data from the spi flash;
the control unit judges whether to hit in the key stream range of the current decryption operation based on the target address in the read signal;
when the target address in the read signal hits the key stream of the current decryption operation, performing exclusive OR on the basis of the ciphertext data read from the spi flash and the key stream corresponding to the target address in the read signal to obtain plaintext data, and sending the plaintext data to a system bus;
and under the condition that the target address in the read signal does not hit the key stream of the current encryption operation, feeding back a waiting signal to the system bus, starting a key expansion unit to generate the key stream corresponding to the target address in the read signal, carrying out XOR on the ciphertext data read from the spi flash and the key stream corresponding to the target address in the read signal to obtain plaintext data, and sending the plaintext data to the system bus.
Further, the method for generating the key stream corresponding to the target address in the read signal by the key expansion unit includes:
filling an spi flash starting address, an spi flash ending address, version information and target address information into an initialization vector;
and carrying out encryption operation on the initialization vector based on the configured key so as to obtain the key stream corresponding to the target address.
And under the condition of first reading, the target address is filled in an initialization vector to obtain an initialization value, and the key expansion unit performs key expansion on the basis of the configured key and the initialization value to obtain the key stream corresponding to the target address.
Further, the method for generating the key stream corresponding to the target address in the read signal by the key expansion unit includes:
and under the condition of reading the continuous addresses, the key expansion unit performs encryption operation based on the counter and the configured key to acquire the key stream corresponding to the target address.
When the data is not read for the first time but read to continuous addresses, the key expansion unit comprises a counter, each group corresponds to a counter which is accumulated successively, the key stream address is automatically increased through the counter, and the target address and the initialization value do not need to be written each time. And the key expansion unit carries out encryption operation based on the counter and the configured key so as to obtain the key stream with continuous addresses.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
after the configuration of the spi flash encryption and decryption interface is completed, when the spi flash is written, the secure interface generates a key stream according to the configured key and the initialization value, and performs exclusive OR on plaintext data to be written and the corresponding key stream to obtain a ciphertext, and writes the obtained ciphertext into the spi flash. When data in the spi flash is read, the spi flash encryption and decryption interface reads ciphertext data from the spi flash, generates a key stream according to a configured key and an initialization value, and performs exclusive OR on the read ciphertext data and the key stream to obtain a plaintext. Because the time required by reading one word by the spi is 32 cycles, and only 12 cycles are required for carrying out one-time CTR-mode grouping algorithm encryption and decryption operation, the interface can carry out real-time decryption on data read by the spi flash, so that the confidentiality of codes and data in the external flash can be protected, a CPU can read the data in the off-chip flash in real time and transparently, and the encryption codes in the off-chip flash can be efficiently operated.
Drawings
The following detailed description of embodiments of the invention is provided in conjunction with the appended drawings, in which:
FIG. 1 is a schematic structural diagram of an spi flash encryption/decryption interface according to the present invention;
FIG. 2 is a flowchart of a method for writing spi flash data according to the present invention;
FIG. 3 is a schematic diagram of an spi flash data write method according to the present invention;
FIG. 4 is a flowchart of a method for reading spi flash data in accordance with the present invention;
FIG. 5 is a schematic diagram of an spi flash data reading method of the present invention.
Description of reference numerals:
1: a control unit; 2: a key expansion unit; 3: an arithmetic unit.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
First embodiment
As shown in fig. 1, the core of the present invention is to provide an spi flash encryption/decryption interface, which includes:
the control unit 1 is configured to receive a bus read/write signal, determine whether a target address of the bus read/write signal hits a key stream of a current encryption/decryption operation, and determine whether to directly use the current key stream or to automatically start to generate a key stream corresponding to the target address according to a hit result.
And the key expansion unit 2 is used for generating a key stream corresponding to the target address.
An arithmetic unit 3, configured to perform an exclusive or operation based on plaintext data and a key stream corresponding to a target address to obtain ciphertext data when data is written; in the case of data reading, an exclusive or operation is performed based on the ciphertext data and the key stream corresponding to the target address to obtain plaintext data.
The control unit 1 automatically judges whether a key stream of the current encryption operation is hit or not for a target address in a read/write signal sent by a bus, and under the condition of hit, the arithmetic unit 3 carries out XOR on ciphertext/plaintext data and the key stream corresponding to the target address to obtain a corresponding plaintext/ciphertext; and when the target address does not match the cipher key stream, the cipher key expansion unit 2 generates a cipher key stream corresponding to the target address to be called by the operation unit 3, and the operation unit 3 performs exclusive or on the cipher key stream corresponding to the target address and the cipher key stream corresponding to the cipher key/plaintext data to obtain the corresponding plaintext/cipher key.
Further, the key expansion unit 2 performs key expansion based on the configured key and the initialization value to obtain the key stream corresponding to the target address. And under the condition of first writing/reading, filling an spi flash starting address, an spi flash ending address, version information and target address information into an initialization vector to obtain an initialization value, and performing key expansion by the key expansion unit 2 based on the configured key and the initialization value to obtain a key stream corresponding to the target address.
Further, the key expansion unit 2 further includes a counter, and in the process of reading/writing to the consecutive addresses, the key expansion unit 2 performs encryption operation based on the internal counter and the configured key to obtain a consecutive keystream corresponding to the target address. Under the condition that the address is not written in/read for the first time, the key expansion unit 2 comprises a counter, each group corresponds to a counter which is accumulated successively, and the automatic increment of the key stream address is realized through the counter.
Second embodiment
As shown in fig. 2-3, the present invention further provides an spi flash data writing method, comprising the following steps:
s1: the system bus sends a write signal to the control unit 1 and waits for an operation end signal;
s2: the control unit 1 judges whether or not a hit is made within a key stream range of the current encryption operation based on the target address in the write signal;
s301: under the condition that a target address in a write signal hits a key stream of the current encryption operation, carrying out exclusive OR on the basis of plaintext data in the write signal and the key stream corresponding to the target address in the write signal to obtain ciphertext data, and writing the ciphertext data into the target address of the write signal in the spi flash;
s302: under the condition that the target address in the write signal does not hit the key stream of the current encryption operation, a waiting signal is fed back to the system bus, the key expansion unit 2 is started to generate the key stream corresponding to the target address in the write signal, exclusive or is carried out on the basis of plaintext data in the write signal and the key stream corresponding to the target address in the write signal to obtain ciphertext data, and the ciphertext data is written into the target address of the write signal in the spi flash.
Further, the method for generating the key stream corresponding to the target address in the write signal by the key expansion unit 2 includes:
s1: filling the target address into an initialization vector;
s2: and carrying out encryption operation on the initialization vector based on the configured key so as to obtain the key stream corresponding to the target address.
In the case of the first write, the target address is filled in the initialization vector to obtain an initialization value, and the key expansion unit 2 performs key expansion based on the configured key and the initialization value to obtain the key stream corresponding to the target address.
Further, the method for generating the key stream corresponding to the target address in the write signal by the key expansion unit 2 includes:
in the case of writing to consecutive addresses, the key expansion unit 2 performs an encryption operation based on the counter and the configured key to obtain a key stream corresponding to the target address.
When the address is written into the continuous address instead of the first time, the key expansion unit 2 includes a counter, each group corresponds to a counter that is gradually accumulated, and the key stream address is automatically increased through the counter.
The control unit 1 judges the target address of the bus write signal, whether the target address hits the key stream range of the current address, and if the target address hits the key stream range, the key stream does not need to be regenerated; if the key is not hit, the key expansion unit 2 is started to expand the key based on the target address and the configured key to obtain the key stream, and the obtained key stream is called by the arithmetic unit 3; when writing is continuously performed, because the key expansion unit 2 includes a counter, each group corresponds to a counter that is gradually accumulated, and the key stream address is automatically increased through the counter.
Third embodiment
As shown in fig. 4 to 5, based on the same concept, the present invention further provides an spi flash data reading method, comprising the steps of:
s1: the system bus sends a reading signal to the control unit and waits for returning plaintext data of a target address;
s2: reading ciphertext data from the spi flash;
s3: the control unit judges whether to hit in the key stream range of the current decryption operation based on the target address in the read signal;
s401: when the target address in the read signal hits the key stream of the current decryption operation, performing exclusive or based on the ciphertext data in the read signal and the key stream corresponding to the target address in the read signal to obtain plaintext data, and sending the plaintext data to a system bus;
s402: and under the condition that the target address in the read signal does not hit the key stream of the current encryption operation, feeding back a waiting signal to the system bus, starting a key expansion unit to generate the key stream corresponding to the target address in the read signal, carrying out XOR on the target address ciphertext data in the read signal and the key stream corresponding to the target address in the read signal to obtain plaintext data, and sending the plaintext data to the system bus.
Further, the method for generating the key stream corresponding to the target address in the read signal by the key expansion unit includes:
s1: filling the target address into an initialization vector;
s2: and carrying out encryption operation on the initialization vector based on the configured key so as to obtain the key stream corresponding to the target address.
And under the condition of first reading, the target address is filled in an initialization vector to obtain an initialization value, and the key expansion unit performs key expansion on the basis of the configured key and the initialization value to obtain the key stream corresponding to the target address.
Further, the method for generating the key stream corresponding to the target address in the read signal by the key expansion unit includes:
and under the condition of reading the continuous addresses, the key expansion unit performs encryption operation based on the counter and the configured key to acquire the key stream corresponding to the target address.
When reading to continuous addresses instead of first reading, the key expansion unit 2 includes a counter, each group corresponds to a counter that is gradually accumulated, and the key stream address is automatically increased through the counter.
The control unit 1 judges the target address of the bus read signal, whether the target address hits the key stream range of the current address, and if the target address hits the key stream range, the key stream does not need to be regenerated; if the key is not hit, the key expansion unit 2 is started to expand the key based on the target address and the configured key to obtain the key stream, and the obtained key stream is called by the arithmetic unit 3; when writing is continuously performed, because the key expansion unit 2 includes a counter, each group corresponds to a counter that is gradually accumulated, and the key stream address is automatically increased through the counter.
The working process of the present invention is explained in detail below:
when a system bus sends a write-in signal to a control unit 2, the control unit 1 judges whether a target address in a write signal hits a key stream of the current operation, if so, the control unit performs exclusive-or operation based on plaintext data and the key stream in the write signal and stores the key stream into a write signal target address of the spi flash, if not, the control unit starts a key expansion unit 2 to perform key expansion based on the target address of the write signal and a configured key to generate the key stream, and then performs exclusive-or operation based on the generated key stream on the plaintext data in the write signal and stores the key stream into the write signal target address of the spi flash. If the target address of the write signal is written for the first time, filling the target address into an initialization vector, and performing key expansion based on the initialization vector and a configured key to obtain a key stream; if the write signal is to write in continuous address, the key expansion unit 2 has a counter, each group corresponds to a counter which is accumulated successively, and the automatic increment of the key stream address is realized through the counter.
When a system bus sends a reading signal to a control unit 2, the control unit 1 judges whether a target address in the reading signal hits a key stream of the current operation, if so, exclusive-or operation is carried out on the basis of ciphertext data read from the spi flash and the key stream to obtain plaintext data and send the plaintext data to the system bus, if not, the key expansion unit 2 is started to carry out key expansion on the basis of the target address of the reading signal and a configured key to generate a key stream, and then exclusive-or operation is carried out on the ciphertext data read from the spi flash on the basis of the generated key stream to obtain plaintext data and send the plaintext data to the system bus. If the target address of the read signal is written for the first time, filling the target address into an initialization vector, and performing key expansion based on the initialization vector and a configured key to obtain a key stream; if the reading signal is to read continuous addresses, the key expansion unit 2 is provided with a counter, each group corresponds to a counter which is accumulated successively, and the automatic increase of the key stream address is realized through the counter.
Because the time required by reading a word by the SPI is 32 cycles, and only 12 cycles are required for carrying out a simplified encryption and decryption operation of the block cipher, the decryption operation is real-time when the security interface reads the data. The encryption and decryption interface is completely transparent to the external access interface, so that the confidentiality of codes and data in the external false can be protected, the CPU can efficiently run the encryption codes in the off-chip flash in real time, and the safe storage space of the data and the codes is seamlessly expanded.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is still within the scope of the present invention if they fall within the scope of the claims of the present invention and their equivalents.
Claims (9)
1. An spi flash encryption and decryption interface, comprising:
the control unit is used for receiving a bus read/write signal and judging whether a target address of the bus read/write signal hits a key stream of the current encryption and decryption operation;
the key expansion unit is used for generating a key stream corresponding to the target address;
the arithmetic unit is used for carrying out XOR operation on the plaintext data and the key stream corresponding to the target address under the condition of data writing to obtain ciphertext data; and in the case of data reading, performing exclusive-or operation based on the ciphertext data and the key stream corresponding to the target address to acquire plaintext data.
2. The spi flash encryption/decryption interface of claim 1,
and the key expansion unit expands the key based on the configured key and the initialization value to acquire the key stream corresponding to the target address.
3. The spi flash encryption/decryption interface of claim 1,
the key expansion unit also comprises an internal counter, and in the process of reading/writing continuous addresses, the key expansion unit uses the internal counter to realize the automatic increase of encryption and decryption addresses without writing target addresses each time, and carries out encryption operation based on the internal counter and configured keys to obtain the key stream corresponding to the target addresses.
4. An spi flash data writing method is characterized by comprising the following steps:
the system bus sends a write signal to the control unit and waits for an operation end signal;
the control unit judges whether to hit in the key stream range of the current encryption operation based on the target address in the write signal;
when a target address in the write signal hits a key stream of the current encryption operation, carrying out exclusive OR on the basis of plaintext data in the write signal and the key stream corresponding to the target address in the write signal to obtain ciphertext data, and writing the ciphertext data into the target address of the write signal in spi flash;
and under the condition that the target address in the write signal does not hit the key stream of the current encryption operation, feeding back a waiting signal to a system bus, starting a key expansion unit to generate the key stream corresponding to the target address in the write signal, carrying out XOR on the plaintext data in the write signal and the key stream corresponding to the target address in the write signal to obtain ciphertext data, and writing the ciphertext data into the target address of the write signal in the spi flash.
5. The spi flash data writing method according to claim 4, wherein the method for generating the key stream corresponding to the target address in the write signal by the key expansion unit comprises the following steps:
filling the target address into an initialization vector;
and carrying out encryption operation on the initialization vector based on the configured key so as to obtain the key stream corresponding to the target address.
6. The spi flash data writing method according to claim 4, wherein the method for generating the key stream corresponding to the target address in the write signal by the key expansion unit comprises the following steps:
and under the condition of writing to the continuous addresses, the key expansion unit performs encryption operation based on the internal counter and the configured key to acquire the key stream corresponding to the target address.
7. An spi flash data reading method is characterized by comprising the following steps:
the system bus sends a reading signal to the control unit and waits for returning plaintext data of a target address;
reading ciphertext data from the spi flash;
the control unit judges whether to hit in the key stream range of the current decryption operation based on the target address in the read signal;
when the target address in the read signal hits the key stream of the current decryption operation, performing exclusive OR on the basis of the ciphertext data read from the spi flash and the key stream corresponding to the target address in the read signal to obtain plaintext data, and sending the plaintext data to a system bus;
and under the condition that the target address in the read signal does not hit the key stream of the current encryption operation, feeding back a waiting signal to the system bus, starting a key expansion unit to generate the key stream corresponding to the target address in the read signal, performing XOR on target address ciphertext data read from the spi flash and the key stream corresponding to the target address in the read signal to obtain plaintext data, and sending the plaintext data to the system bus.
8. The spi flash data reading method according to claim 7, wherein the method for generating the key stream corresponding to the target address in the read signal by the key expansion unit comprises:
filling the target address into an initialization vector;
and carrying out encryption operation on the initialization vector based on the configured key so as to obtain the key stream corresponding to the target address.
9. The spi flash data reading method according to claim 7, wherein the method for generating the key stream corresponding to the target address in the read signal by the key expansion unit comprises:
and under the condition of reading the continuous addresses, the key expansion unit carries out encryption operation based on the internal counter and the configured key so as to obtain the key stream corresponding to the target address.
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