CN114326289A - Method, apparatus and storage medium for performing optical proximity correction - Google Patents
Method, apparatus and storage medium for performing optical proximity correction Download PDFInfo
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Abstract
According to example embodiments of the present disclosure, methods, apparatuses, devices, and computer-readable storage media for performing Optical Proximity Correction (OPC) are provided. In the method, a second mask layout is determined by modifying a first mask layout, the first mask layout being associated with a target pattern in a first accuracy format. A wafer image in a second precision format is determined by applying the lithography model to the second mask layout using the second precision format, the second precision format having a lower precision than the first precision format. And converting the wafer image in the second precision format into the wafer image in the first precision format. A metrology index indicative of a difference between the wafer image and the target pattern in the first precision format is determined using the first precision format. And outputting the second mask layout based on the measurement index meeting the preset standard. In this way, by using high-precision and low-precision formats in a mixed manner, it is possible to improve the calculation speed and reduce the consumption of calculation resources and storage resources, thereby improving the efficiency of performing OPC.
Description
Technical Field
Embodiments of the present disclosure relate generally to integrated circuits and, more particularly, relate to a method, apparatus, and computer-readable storage medium for performing Optical Proximity Correction (OPC).
Background
With the increasing development of integrated circuits, the design size is smaller and smaller. Due to diffraction and interference phenomena of light, there is a certain difference between a wafer image actually formed on a silicon wafer by exposing a reticle and a circuit layout on the reticle (simply referred to as a mask layout). For example, the wafer image may have narrow line widths, narrow line short-point shrinkage, rounded pattern corners, and the like.
Currently, OPC is widely used to reduce the difference between the wafer image and the designed target pattern. The OPC method compensates for imaging by modifying the mask layout so that the resulting wafer image is closer to the target pattern. However, the OPC method requires simulation of the processes of modifying the mask layout, obtaining the wafer image, and evaluating the wafer image. The simulation of these processes requires a significant amount of time and computational resources. Therefore, a scheme capable of efficiently performing OPC is required.
Disclosure of Invention
According to an example embodiment of the present disclosure, a scheme for performing optical proximity correction is provided.
In a first aspect of the disclosure, a method for performing optical proximity correction is provided. The method includes determining a second mask layout by modifying a first mask layout, the first mask layout being associated with a target pattern in a first accuracy format. The method further includes determining a wafer image in a second precision format by applying the lithography model to a second mask layout using the second precision format, the second precision format having a lower precision than the first precision format. The method also includes converting the wafer image in the second precision format to the wafer image in the first precision format. The method also includes determining, using the first precision format, a metrology index indicative of a difference between the wafer image of the first precision format and the target pattern. The method also includes outputting a second mask layout based on the metric satisfying a predetermined criterion.
In this way, by determining the wafer image using a low precision format and measuring the difference between the wafer image and the target pattern using a high precision format, it is possible to improve the calculation speed and reduce the consumption of calculation resources and storage resources, thereby improving the efficiency of performing OPC.
In a second aspect of the disclosure, an electronic device is provided that includes one or more processors; and a storage device for storing the one or more programs which, when executed by the one or more processors, cause the one or more processors to perform the actions. The actions include determining a second mask layout by modifying a first mask layout, the first mask layout associated with a target pattern in a first accuracy format. The acts also include determining a wafer image in a second precision format by applying the lithography model to a second mask layout using the second precision format, the second precision format having a lower precision than the first precision format. The acts also include converting the wafer image in the second precision format to a wafer image in the first precision format. The actions also include determining, using the first precision format, a metrology index indicative of a difference between the wafer image of the first precision format and the target pattern. The acts also include outputting a second mask layout based on the metric satisfying a predetermined criterion.
In some embodiments, the first precision format includes a 32-bit floating point number format FP 32; and the second precision format includes a 16-bit brain floating point format BF 16.
In some embodiments, the actions further comprise: the value representing the first precision format of the first mask layout is converted to a value representing the second precision format by truncating the mantissa of the first precision format.
In some embodiments, converting the wafer image in the second precision format to the wafer image in the first precision format comprises: converting the numerical value of the second precision format representing the wafer image into the numerical value of the first precision format by complementing the mantissa of the second precision format; determining an estimated value of the corresponding first precision format by interpolating the numerical value of the first precision format; and representing the wafer image using the estimated value.
In some embodiments, applying the lithography model to the second mask layout using the second precision format comprises: at least one of a convolution operation and a Fourier transform operation is performed using a second precision format.
In some embodiments, determining the metric using the first precision format comprises performing with a first processor that supports the first precision format; and determining the wafer image in the second precision format comprises performing with a second processor that supports the second precision format, wherein the first processor and the second processor are the same processor or different processors.
In some embodiments, the first processor and the second processor are selected from the group consisting of: the device comprises a central processing unit CPU, a graphic processing unit GPU, a field programmable gate array FPGA, an acceleration processor AP, a tensor processing unit TPU and a neural network processing unit NPU.
In some embodiments, the metrics include at least one of: edge placement error, and critical dimensions.
In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements a method according to the first aspect of the present disclosure.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
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The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:
FIG. 1 shows a schematic diagram of performing OPC on a mask layout;
FIG. 2 illustrates an example environment in which various embodiments of the present disclosure can be implemented;
FIG. 3 illustrates a flow diagram of an example method for performing OPC in accordance with some embodiments of the present disclosure;
FIG. 4 illustrates an example of a first precision format and a second precision format, in accordance with some embodiments of the present disclosure;
FIG. 5 illustrates an example of a metric according to some embodiments of the present disclosure;
FIG. 6 illustrates a schematic diagram of utilizing multiple processors to perform OPC, according to some embodiments of the present disclosure; and
FIG. 7 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As mentioned previously, OPC requires simulation of the process of modifying the mask layout, obtaining the wafer image, and evaluating the wafer image. The principle of OPC is briefly described below with reference to fig. 1.
Fig. 1 shows a schematic diagram 100 of performing OPC on a mask layout. It should be understood that fig. 1 only schematically shows a part of the patterns in the mask layout. The layout pattern 110 is a portion of the pattern in the input initial mask layout. The target pattern 120 is a pattern desired to be formed on a silicon wafer by exposure. The target pattern 120 is determined based on design goals. The layout pattern 130 is an output pattern for performing optical proximity correction on the layout pattern 110, which may be referred to as a post-OPC pattern.
In general, OPC can compensate for pattern distortions due to optical proximity effects to some extent by modifying the mask layout, such as shifting the position of edges or adding additional polygons (as shown in layout pattern 130), so that the exposed wafer image is closer to the target pattern.
Various OPC schemes have been proposed, such as empirical-based OPC and model-based OPC. Empirical-based OPC modifies the mask layout according to predetermined modification rules. The modification rules specify that the mask layout is to be modified based on various factors, such as width and spacing constraints. The modification rules can be generalized from a large number of experimental data or can be generated by calculation.
However, the modification rules depend on process parameters such as lighting conditions. If the process parameters change, these modification rules need to be adjusted to accommodate the new process parameters. In this case, a large number of wafer images need to be obtained through preparation or calculation for summarizing new modification rules therefrom.
Model-based OPC determines post-OPC patterns by solving an optimization problem. The optimization goal is to minimize the difference between the wafer image calculated using the lithography model and the target pattern. For example, the wafer image W (x, y) may be calculated with reference to equation (1):
W(x，y)＝f(m(x，y)) (I)
where f is a physical model describing various phenomena in the lithographic process, which is a function of the mask layout; m (x, y) is an input mask layout, such as layout pattern 110 shown in FIG. 1; (x, y) represents coordinates.
One way to compute the wafer image is to use a kernel convolution formula as shown in equation (2):
wherein phii(x, y) denotes the ith convolution kernel, i ═ 1, 2, …, K, and K is the number of convolution kernels.
The mask layout may be optimized with reference to equation (3) such that the obtained wafer image W is as close as possible to the target pattern T, such as target pattern 120.
Wherein minmRepresents optimizing m (x, y) so that
At a minimum, N denotes dividing the wafer image W and the target pattern T into N lattices, (x)j，yj) Denotes the coordinates of the jth cell and j ═ 1, 2, …, N, | | … | | survivalLRefers to the mathematical L-norm.
Since there is no inverse function of f in analytic form, a general OPC scheme is to find the appropriate m (x, y) for equation (3) by an optimization or regression process. The resulting m (x, y) is referred to as a post-OPC pattern, such as the layout pattern 130 shown in FIG. 1.
However, the solution of the above optimization problem is quite complex. For example, the process of calculating the wafer image described by equation (2) involves a convolution operation with a high computational complexity. In addition, when the optimization problem is solved numerically, the wafer image and the L norm need to be iteratively calculated until a predetermined condition is satisfied.
In general, current OPC schemes are computationally intensive. Therefore, a scheme capable of efficiently performing OPC is required. According to an embodiment of the present disclosure, a scheme for performing OPC is proposed. In this approach, a second mask layout is determined by modifying a first mask layout, the first mask layout being associated with a target pattern in a first accuracy format. A wafer image in a second precision format is determined by applying the lithography model to a second mask layout using the second precision format, the second precision format having a lower precision than the first precision format. And converting the wafer image in the second precision format into the wafer image in the first precision format. A metrology index indicative of a difference between the wafer image and the target pattern in the first precision format is determined using the first precision format, and a second mask layout is output based on the metrology index satisfying a predetermined criterion.
In this way, by determining the wafer image using a low precision format and measuring the difference between the wafer image and the target pattern using a high precision format, it is possible to improve the calculation speed and reduce the consumption of calculation resources and storage resources, thereby improving the efficiency of performing OPC.
The process and details of performing OPC will be described below with reference to fig. 2 to 6.
FIG. 2 illustrates an example environment 200 in which various embodiments of the present disclosure can be implemented. As shown in FIG. 2, a computing device 210 receives a target pattern 201 and a first mask layout 202. The target pattern 201 is a complete or partial wafer image that is desired to be obtained on a silicon wafer, such as the target pattern 120 shown in fig. 1. The first mask layout 202 may be a complete circuit layout or a portion thereof, such as the layout pattern 110 shown in fig. 1.
The first mask layout 202 is associated with the target pattern 201. The first mask layout 202 may be an initial mask layout determined based on the target pattern 201. In some embodiments, the first mask layout 202 may be the same as the target pattern 201. In some embodiments, the first mask layout 202 may be the preliminarily modified target pattern 201.
Based on the received target pattern 201 and the first mask layout 202, the computing device 210 outputs a second mask layout 203. The second mask layout 203 is a modified version of the first mask layout 202 obtained on the basis of OPC. The wafer image obtained by exposing the second mask layout 203 is closer to the target pattern 201 than the wafer image obtained by exposing the first mask layout 202.
Fig. 3 illustrates a flow diagram of an example method 300 for performing OPC in accordance with some embodiments of the present disclosure. For ease of discussion, the method 300 will be described in conjunction with FIG. 2.
At block 310, the computing device 210 determines the second mask layout 203 by modifying the first mask layout 202. The first mask layout 202 is associated with the target pattern 201 in a first accuracy format.
At block 320, the computing device 210 determines a wafer image in a second precision format by applying a lithography model to the second mask layout 203 using the second precision format, the second precision format having a lower precision than the first precision format.
Fig. 4 illustrates an example of a first precision format and a second precision format, in accordance with some embodiments of the present disclosure. As shown in fig. 4, first precision format 410 may have 8 exponent bits and 23 mantissa bits. For example, the first precision format may be the 32-bit single precision floating point number format (FP32) that is currently in widespread use. Alternatively, the first precision format may be a 64-bit double precision floating point number format (FP 64).
The second precision format has a lower precision than the first precision format. As shown in fig. 4, second precision format 420 may have 8 exponent bits and 7 mantissa bits. For example, the second precision format may be a 16-bit brain floating point format (BF 16). Alternatively, the second precision format may be a 16-bit half precision floating point number format (FP 16).
The BF16 format is a 16-bit numeric encoding format that represents floating point numbers by truncating the FP32 mantissa. The BF16 format may be used for hardware accelerated machine learning algorithms, such as may be used in FPGAs and neuron processors.
It should be understood that the FP32 format and BF16 format described above are exemplary only and not limiting. For example, the first precision format may be the FP64 format and the second precision format may be the FP32 format. The scope of the present disclosure is not limited in terms of the particular type of precision format.
With continued reference to FIG. 3, in some embodiments, received by the computing device 210 is the first mask layout 202 in the first precision format. In this case, the first mask layout 202 in the first precision format may be converted to the first mask layout in the second precision format to reduce the amount of subsequent computations.
In some embodiments, a value representing a first precision format of the first mask layout may be converted to a value representing a second precision format by truncating the mantissa of the first precision format. For example, when the first precision format is the FP32 format and the second precision format is BF16, a numerical value of the first precision format may be converted into a numerical value of the second precision format in such a manner that only the first 7 bits of the 23 mantissa bits are reserved.
Alternatively, the first mask layout 202 in the first precision format may be modified first to obtain the second mask layout 203 in the first precision format. The second mask layout 203 in the first precision format may then be converted to a second mask layout 203 in a second precision format to reduce the amount of subsequent computations.
In some embodiments, the computing device 210 may determine the second mask layout 203 by modifying the first mask layout 202 based on modification rules. Based on the determined second mask layout 203, the computing device 210 applies a lithography model to the second mask layout 203 using a second precision format to determine a wafer image in the second precision format.
The lithography model may include an optical model and a photoresist photochemical reaction model. Applying the lithography model may include applying a convolution operation, an optical model simulation operation, an etch model simulation operation, or a chemical mechanical polishing simulation operation, etc. to the second mask layout 203. For example, a wafer image formed by exposing the second mask layout 203 may be calculated with reference to equations (1) and (2).
Operations with high computational intensity of the above operations may be performed using the second precision format. In some embodiments, applying the lithography model to the second mask layout 203 using the second precision format includes performing a convolution operation using the second precision format. Alternatively or additionally, the fourier transform operation may also be performed using a second precision format.
By using a second precision format with lower precision, such as BF16 format, more data can be stored in the memory, and the time for moving data in the memory is reduced, so that the hardware circuit design of the acceleration processor becomes simple, thereby bringing about a significant increase in the calculation speed.
In some embodiments, the computing device 210 may modify the first mask layout 202, thereby determining the second mask layout 203, based on the guidance for modification determined when solving the optimization problem. For example, when an optimization algorithm such as an evolutionary algorithm is applied to solve the optimization problem as shown in equation (3), the mask layout may be iteratively modified and evaluated until it is determined that the modified mask layout satisfies the predetermined condition. The mask layout satisfying the predetermined condition may be determined as the second mask layout 203.
In this case, for each mask layout in the iterative process, a corresponding wafer image needs to be calculated, so that guidance for next modification of the mask layout is given by comparison of the wafer image and the target pattern 201. By calculating each corresponding wafer image using the second precision format instead of the first precision format, the amount of calculations can be greatly reduced and the calculation speed can be increased. It is to be understood that in this case, the wafer image may be compared to the target pattern 201 using either the first or second precision format.
At block 330, the computing device 210 converts the wafer image in the second precision format to the wafer image in the first precision format, i.e., converts the numerical values representing the wafer image in the second precision format to the numerical values representing the wafer image in the first precision format. Depending on the particular type of first precision format and second precision format, various suitable methods may be employed to convert the wafer image in the second precision format to the wafer image in the first precision format.
In some embodiments, when the second precision format is only missing mantissa bits from the first precision format, the value of the second precision format representing the wafer image may be converted to the value of the first precision format by completing the mantissa bits of the second precision format (the value of the additional mantissa bits being zero).
Additionally, the values of the first precision format may be interpolated using an interpolation algorithm to determine corresponding estimated values of the first precision format. Interpolation means that new and more reliable data are calculated by a mathematical method to make up for the vacant part in the data space. The interpolation may be performed using various suitable algorithms, such as Hermite interpolation, cubic spline interpolation, differential Newton interpolation, and the like.
The estimate of the first accuracy format from the interpolation may represent the wafer image with higher resolution and higher accuracy. Therefore, representing the wafer image with the estimated value may more accurately compare the difference between the wafer image and the target pattern 201.
At block 340, the computing device 210 determines a metrology index indicative of a difference between the wafer image in the first precision format and the target pattern 201 using the first precision format. The metrology index may be used to evaluate the similarity between the wafer image and the target pattern 201, so that the quality of the determined second mask layout 203 may be evaluated.
In some embodiments, the metric may include Edge Placement Error (EPE). Edge placement error is an index used to measure OPC quality, and smaller edge placement error means closer wafer image to target pattern after exposure.
Alternatively or additionally, the metric may include a Critical Dimension (CD). The critical dimension may be defined as the width of a line obtained at a particular exposure intensity threshold. The closer the determined critical dimension of the wafer image and the critical dimension of the target pattern, the less the difference between the wafer image and the target pattern.
By determining the metrology index using the first precision format, the difference between the wafer image and the target pattern 201, and thus the second mask layout 203, may be more accurately evaluated.
Fig. 5 illustrates an example of a metric according to some embodiments of the present disclosure. Fig. 5 shows errors 510 and 511 between the target pattern 201 and the wafer image 501. Errors 510 and 511 are examples of edge placement errors. Edge placement errors, which indicate differences between the target pattern 201 and the wafer image 501, may be synthetically determined based on the errors 510 and 511, as well as other unannotated errors. Fig. 5 also shows a critical dimension 520 of the target pattern 201 and a critical dimension 521 of the wafer image 501.
It should be understood that edge placement errors and critical dimensions are merely examples of metrics and are not limiting. Various suitable metrology indicators may be determined using the first precision format to indicate the difference between the target pattern 201 and the wafer image 501. The scope of the present disclosure is not limited thereto.
With continued reference to FIG. 3, at block 350, the computing device 210 outputs the second mask layout 203 based on the metrics meeting predetermined criteria. In some embodiments, the second mask layout 203 may be output as a post-OPC pattern when the difference between the wafer image determined based on the second mask layout 203 and the target pattern 201 satisfies a predetermined criterion.
In some embodiments, when the metrology index does not meet a predetermined criterion, i.e., the difference between the wafer image determined based on the second mask layout 203 and the target pattern 201 is large, the steps of blocks 310-340 may be repeated to determine additional mask layouts based on the second mask layout 203.
For example, the second mask layout 203 may continue to be modified to obtain additional mask layouts. If the difference between the wafer image determined based on the additional mask layout and the target pattern 201 satisfies a predetermined criterion, the additional mask layout may be output as the post-OPC pattern.
The process and details of performing OPC are described above with reference to fig. 1-5. A process of performing OPC using hardware resources will be described below with reference to fig. 6. FIG. 6 illustrates a schematic diagram of performing OPC using multiple processors according to some embodiments of the present disclosure.
Fig. 6 shows a controller 610 and a plurality of processors 620. Controller 610 and plurality of processors 620 may be components in computing device 210. Plurality of processors 620 may include processor 621 and processor 622. It should be understood that the number of processors shown in fig. 6 is merely illustrative, and one, two, or more processors may be utilized to perform OPC.
Plurality of processors 620 may be various suitable types of processors. In some embodiments, the processor may be selected from the following: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Acceleration Processor (AP), a Tensor Processing Unit (TPU), a neural Network Processing Unit (NPU), and the like.
The controller 610 and the plurality of processors 620 may communicate and transfer data with each other. Data transfers between the controller 610 and the plurality of processors 620 may be based on any suitable form of communication connection, including but not limited to a wide area network (e.g., the internet), a local area network, a private network, a public network, a packet network, a wired network, or a wireless network, such as connections established through bluetooth, Near Field Communication (NFC), wireless fidelity (Wi-Fi), Worldwide Interoperability for Microwave Access (WiMAX), infrared, 2G/3G/4G/5G, and other future developed technologies, among others.
The plurality of processors 620 may be a hybrid architecture. In other words, the plurality of processors 620 may include various types of processors, and may also include processors that support various precision formats. For example, processor 621 and processor 622 may be a CPU supporting FP32 and a TPU supporting BF16, respectively. In another example, processor 621 and processor 622 may be a CPU supporting FP32 and a CPU supporting BF16, respectively. In another example, processors 621 and 622 may be GPUs supporting FP32 and BF16 and APs supporting BF16, respectively.
The controller 610 may send instructions to the respective processors to perform different operations based on the configuration information of the plurality of processors 620. The configuration information may indicate the type of processor, e.g., CPU, GPU, TPU, or the like. The configuration information may also indicate the precision formats supported by the processor, such as FP32 and BF 16. A single processor may support one or more precision formats.
In some embodiments, the operation of determining a metric may be performed using a first processor that supports a first precision format. An operation may be performed to determine the wafer image in the second precision format using a second processor that supports the second precision format, where the first processor and the second processor are the same processor or different processors.
For example, the operations of determining metrology metrics and determining wafer images may be performed using a GPU that supports both FP32 and BF 16. In another example, the operations of determining the metrology metrics may be performed using a GPU supporting FP32 and the operations of determining the wafer image may be performed using an APL supporting BF 16.
In such a hybrid architecture, the respective operations of OPC may be performed using a suitable processor. In this way, a balance of efficiency and cost may be achieved.
Fig. 7 illustrates a schematic block diagram of an example device 700 that may be used to implement embodiments of the present disclosure. Device 700 may be used to implement computing device 210 of fig. 2. As shown, device 700 includes a Central Processing Unit (CPU)701 that may perform various appropriate actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM)702 or computer program instructions loaded from a storage unit 708 into a Random Access Memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the device 700 can also be stored. The CPU 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.
Various components in the device 700 are connected to the I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, or the like; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processing unit 701 performs the various methods and processes described above, such as the method 300. For example, in some embodiments, the method 300 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of a computer program may be loaded onto and/or installed onto device 700 via ROM 702 and/or communications unit 709. When the computer program is loaded into the RAM 703 and executed by the CPU 701, one or more steps of the method 300 described above may be performed. Alternatively, in other embodiments, the CPU 701 may be configured to perform the method 300 in any other suitable manner (e.g., by way of firmware).
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), System On Chip (SOCs), load programmable logic devices (CPLDs), and the like.
Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (10)
1. A method of performing optical proximity correction, comprising:
determining a second mask layout by modifying a first mask layout, the first mask layout being associated with a target pattern of a first accuracy format;
determining a wafer image in a second precision format by applying a lithography model to the second mask layout using the second precision format, the second precision format having a lower precision than the first precision format;
converting the wafer image with the second precision format into the wafer image with the first precision format;
determining, using the first precision format, a metrology index indicative of a difference between the wafer image of the first precision format and the target pattern; and
and outputting the second mask layout based on the measurement index meeting a preset standard.
2. The method of claim 1, wherein:
the first precision format comprises a 32-bit floating point number format FP 32; and is
The second precision format includes a 16-bit brain floating point format BF 16.
3. The method of claim 2, further comprising:
converting the value representing the first precision format of the first mask layout into a value representing the second precision format by truncating the mantissa of the first precision format.
4. The method of claim 2, wherein converting the wafer image of the second precision format to the wafer image of the first precision format comprises:
converting the numerical value of the second precision format representing the wafer image into the numerical value of the first precision format by complementing the mantissa of the second precision format;
determining a corresponding estimated value of the first precision format by interpolating the numerical value of the first precision format; and
representing the wafer image using the estimate.
5. The method of claim 1, wherein applying a lithography model to the second mask layout using the second precision format comprises:
performing at least one of a convolution operation and a Fourier transform operation using the second precision format.
6. The method of any of claims 1-5, wherein:
determining the metric using the first precision format comprises performing with a first processor that supports the first precision format; and is
Determining the wafer image in the second precision format comprises performing with a second processor supporting the second precision format,
wherein the first processor and the second processor are the same processor or different processors.
7. The method of claim 6, wherein the first processor and the second processor are selected from the group consisting of: the device comprises a central processing unit CPU, a graphic processing unit GPU, a field programmable gate array FPGA, an acceleration processor AP, a tensor processing unit TPU and a neural network processing unit NPU.
8. The method of claim 1, wherein the metric comprises at least one of:
edge placement error, and
critical dimensions.
9. An electronic device, comprising:
a processor; and
a memory coupled with the processor, the memory having instructions stored therein that, when executed by the processor, cause the apparatus to perform acts comprising:
determining a second mask layout by modifying a first mask layout, the first mask layout being associated with a target pattern of a first accuracy format;
determining a wafer image in a second precision format by applying a lithography model to the second mask layout using the second precision format, the second precision format having a lower precision than the first precision format;
converting the wafer image with the second precision format into the wafer image with the first precision format;
determining, using the first precision format, a metric indicative of a difference between a wafer image of the first precision format and the target pattern; and
and outputting the second mask layout based on the measurement index meeting a preset standard.
10. A computer program product tangibly stored on a computer-readable medium and comprising machine executable instructions that, when executed, cause a machine to perform the method of any of claims 1 to 8.
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