CN114301452A - Phase-locked loop circuit, control method, charge pump and chip - Google Patents
Phase-locked loop circuit, control method, charge pump and chip Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention provides a phase-locked loop circuit, a control method, a charge pump and a chip, wherein the circuit comprises a phase frequency detector, a phase-locked loop control circuit and a phase-locked loop control circuit, wherein the phase frequency detector is used for receiving a reference clock signal and an output signal of a frequency divider and generating a charge and discharge control signal; the charge pump module is used for determining charging or discharging according to the charging and discharging control signal, determining a charging or discharging current gear, and generating corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear; a loop filter for filtering the charging current or the discharging current; the voltage-controlled oscillator is used for generating a phase-locked loop output signal with a preset frequency; and the frequency divider is used for dividing the frequency of the output signal of the phase-locked loop, and inputting the frequency-divided signal into the phase frequency detector as an output signal. The circuit provided by the invention realizes the function of the phase-locked loop, reduces the stray in the phase-locked loop and improves the bandwidth characteristic.
Description
Technical Field
The invention relates to the technical field of phase-locked loop circuits, in particular to a phase-locked loop circuit, a control method, a charge pump and a chip.
Background
A phase locked loop is a circuit that synchronizes the output frequency divided signal generated by a Voltage Controlled Oscillator (VCO) with an input reference signal in phase and frequency. In the synchronous state (commonly referred to as lock), the phase difference between the output signal of the oscillator and the input reference signal is 0 or a fixed constant. If the phase difference between the two changes, a feedback control mechanism exists in the phase-locked loop to adjust the output of the oscillator, so that the phase difference is reduced, and finally the phase-locked state is achieved. In this control system, the phase of the output signal is actually locked to the phase of the input reference signal, which is why the circuit is called a phase-locked loop.
The frequency multiplication function of the phase-locked loop circuit is the most common means for obtaining a high-frequency clock, and the phase-locked loop circuit is widely used for generating clocks required under various applications, and plays an important role in clock data recovery circuits, wireless transceiver circuits, microprocessors and MCU chips, while the prior phase-locked loop circuit has high stray and poor bandwidth characteristics.
Disclosure of Invention
Based on this, the invention provides a phase-locked loop circuit, which comprises a phase frequency detector, a charge pump module, a loop filter, a voltage-controlled oscillator and a frequency divider,
the phase frequency detector is used for receiving a reference clock signal and an output signal of the frequency divider and generating a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider;
the charge pump module is used for receiving the charge and discharge control signal, determining charging or discharging according to the charge and discharge control signal, determining a charging or discharging current gear, and generating corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear;
the loop filter is used for filtering the charging current or the discharging current to obtain a control voltage signal;
the voltage-controlled oscillator is used for generating a phase-locked loop output signal with a preset frequency according to the control voltage signal;
and the frequency divider is used for dividing the frequency of the output signal of the phase-locked loop, and inputting the frequency-divided signal into the phase frequency detector as an output signal.
Optionally, the charge pump module includes a charging circuit, a discharging circuit, and a dynamic cell matching module; the dynamic unit matching module is used for determining a charging current gear or a discharging current gear according to a preset frequency division coefficient; the charging circuit is used for generating a charging current of the charging current gear; the discharging circuit is used for generating the charging current of the discharging current gear.
Optionally, the charging circuit and the discharging circuit both include a plurality of current mirror units, and the dynamic unit matching module is further configured to determine the number of current mirror units in the charging circuit or the discharging circuit that are turned on according to the charging current gear or the discharging current gear, and turn on the current mirror units in the charging circuit or the discharging circuit according to the number of current mirror units that are turned on.
Optionally, the current mirror unit in the charging circuit includes a first P-type field effect transistor and a first switch, one end of the first switch is connected to a bias voltage, the other end of the first switch is connected to a gate of the first P-type field effect transistor, a source of the first P-type field effect transistor is connected to a power supply, and a drain of the first P-type field effect transistor is connected to the dynamic unit matching module.
Optionally, the current mirror unit in the discharge circuit includes a first N-type field effect transistor and a second switch, one end of the second switch is connected to the bias voltage, the other end of the second switch is connected to the gate of the first N-type field effect transistor, the source of the first N-type field effect transistor is grounded, and the drain of the first N-type field effect transistor is connected to the dynamic unit matching module.
Optionally, the dynamic unit matching module includes a first dynamic unit matcher and/or a second dynamic unit matcher;
the first dynamic unit matcher is used for determining a charging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit according to the conduction number;
the second dynamic unit matcher is used for determining a discharging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the discharge circuit according to the discharging current gear, and conducting the current mirror units in the discharge circuit according to the conduction number.
Optionally, the dynamic unit matching module includes a first dynamic unit matcher and/or a second dynamic unit matcher;
the first dynamic unit matcher is used for determining a charging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit randomly according to the conduction number;
the second dynamic unit matcher is used for determining a discharging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the discharge circuit according to the discharging current gear, and conducting the current mirror units in the discharge circuit randomly according to the conduction number.
Optionally, the charge pump module further includes a third switch and a fourth switch, one end of the third switch is connected to the charging circuit, and the other end of the third switch is connected to the loop filter; one end of the fourth switch is connected with the discharge circuit, and the other end of the fourth switch is connected with the loop filter.
Optionally, the phase-locked loop circuit further includes a bias voltage generating circuit, where the bias voltage generating circuit includes a second P-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor, and a reference current source;
one end of the reference current source is connected with the source electrode of the second P-type field effect transistor, the drain electrode of the second P-type field effect transistor is connected with the grid electrode, and the grid electrode of the second P-type field effect transistor is also connected with one end of the first switch in the charging circuit and the grid electrode of the first P-type field effect transistor;
the drain electrode of the second N-type field effect transistor is connected with the other end of the reference current source, the grid electrode of the second N-type field effect transistor is connected with the grid electrode of the third N-type field effect transistor, the source electrode of the second N-type field effect transistor is grounded with the source electrode of the third N-type field effect transistor, and the grid electrode of the second N-type field effect transistor and the grid electrode of the third N-type field effect transistor are connected with one end, connected with the bias voltage, of the second switch in the discharge circuit.
The invention also provides a phase-locked loop control method, which comprises the following steps:
acquiring a reference clock signal and a frequency division signal, and generating a charge and discharge control signal according to the phase difference of the reference clock signal and the frequency division signal;
determining charging or discharging according to the charging and discharging control signal, determining a charging or discharging current gear according to a preset frequency division coefficient, and generating corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear;
filtering the charging current or the discharging current to obtain a control voltage signal;
generating a phase-locked loop output signal with a preset frequency according to the control voltage signal;
and carrying out frequency division on the output signal of the phase-locked loop to obtain the frequency division signal.
The invention also provides a charge pump, which is used for receiving the charge and discharge control signal, determining charging or discharging according to the charge and discharge control signal, determining a charging or discharging current gear, and generating corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear.
The invention also provides a chip which comprises the phase-locked loop circuit or the charge pump in any technical scheme.
The invention has the beneficial effects that: receiving a reference clock signal and an output signal of a frequency divider through a phase frequency detector, and generating a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider; receiving a charge and discharge control signal through a charge pump module, determining charging or discharging according to the charge and discharge control signal, determining a charging or discharging current gear, and generating a corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear; filtering the charging current or the discharging current through a loop filter to obtain a control voltage signal; generating a phase-locked loop output signal with a preset frequency according to the control voltage signal through a voltage-controlled oscillator; the phase-locked loop has the advantages that the phase-locked loop function is realized, meanwhile, the stray in the phase-locked loop is reduced, and the bandwidth characteristic is improved.
Drawings
FIG. 1 is a circuit block diagram of a phase-locked loop circuit according to a first embodiment of the present invention;
fig. 2 is a schematic circuit diagram of the phase-locked loop circuit according to the first embodiment of the present invention;
FIG. 3 is a schematic block diagram of a charge pump module according to a first embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a charge pump module according to a first embodiment of the present invention;
fig. 5 is a flowchart illustrating a phase-locked loop control method according to a second embodiment of the invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Fig. 1 is a circuit block diagram of a phase-locked loop circuit according to a first embodiment of the present invention. It should be noted that the circuit of the present invention is not limited to the schematic circuit shown in fig. 1 if the same results are obtained. As shown in fig. 1, the phase-locked loop circuit includes a phase frequency detector PFD, a charge pump module CP, a loop filter LPF, a voltage controlled oscillator VCO, and a frequency divider DIV,
the phase frequency detector PFD is used for receiving a reference clock signal and an output signal of the frequency divider and generating a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider;
the charge pump module CP is configured to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, determine a current gear for charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current gear for charging or discharging;
the loop filter LPF is used for filtering the charging current or the discharging current to obtain a control voltage signal;
the voltage controlled oscillator VCO is used for generating a phase-locked loop output signal with preset frequency according to the control voltage signal;
and the frequency divider DIV is used for dividing the frequency of the output signal of the phase-locked loop, and inputting the frequency-divided signal into the phase frequency detector as an output signal.
The charge/discharge control signal is generated according to the reference clock signal and the output signal of the frequency divider, and specifically, the charge/discharge control signal is generated according to a phase difference between the reference clock signal and the output signal of the frequency divider.
As an embodiment, the phase-locked loop circuit includes a phase frequency detector PFD, a charge pump module CP, a loop filter LPF, a voltage controlled oscillator VCO, and a frequency divider DIV; the phase frequency detector is used for detecting the phase difference between an input reference clock clkin and a feedback clock clkdiv after frequency division, outputting a control signal UP or DN, the signal UP controls the charge pump module to charge, the signal DN controls the charge pump module to discharge, the output current of the charge pump obtains the control voltage Vc of the voltage-controlled oscillator after passing through the loop filter, the Vc can adjust the output clock frequency of the voltage-controlled oscillator, and the adjusted output clock frequency clkout returns to the phase frequency detector after passing through the frequency division of the frequency divider, so that a feedback loop is formed.
In some embodiments, the loop filter LPF includes a capacitor C1, a capacitor C2, and a resistor R1, one end of the resistor R1 is connected to the output terminal of the charge pump module, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the input terminal of the voltage controlled oscillator.
As an embodiment, the circuit schematic diagram of the phase-locked loop circuit is shown in fig. 2, where clkin is an input reference clock, clkdiv is a feedback clock after frequency division in fig. 2, and the loop filter LPF includes capacitors C1, C2 and a resistor R1, where the transfer function of the loop filter LPF is
The gain of the phase-locked loop circuit can be obtained to be approximately
Zero of gain of phase-locked loop circuit is
The gain of the phase-locked loop circuit has a sub-pole of
The phase margin PM of the PLL circuit is
The unit gain bandwidth of the phase-locked loop circuit is
Natural frequency
Damping factor
Wherein, IcpIs the output current of the charge pump module, KvcoAnd N is the frequency division coefficient of the gain of the voltage-controlled oscillator.
For a phase-locked loop circuit for frequency multiplication, considering that the input reference is from a high-precision crystal oscillator, the phase noise performance is good, and the loop bandwidth should be designed to be as close as possible to 1/20 of the input reference, because the phase noise suppression effect on the ring oscillator VCO is the best.
The loop bandwidth and the damping factor of the phase-locked loop circuit are in negative correlation with the frequency division coefficient N, and when the frequency division coefficient N is increased, the bandwidth omega is ensuredcWithout change, I should be increased appropriatelycpCurrent, based on charge pump current segmentation techniques, can be divided over a wide frequencyUnder the coefficient range, the loop characteristic of the phase-locked loop circuit is ensured to be in a better value, in other words, the phase-locked loop circuit can realize a wide output frequency range on the premise of ensuring the performance.
In some embodiments, the charge pump module comprises a charging circuit, a discharging circuit, and a dynamic cell matching module; the dynamic unit matching module is used for determining a charging current gear or a discharging current gear according to a preset frequency division coefficient; the charging circuit is used for generating a charging current of the charging current gear; the discharging circuit is used for generating the charging current of the discharging current gear.
As an embodiment, a functional block diagram of the charge pump module is shown in fig. 3. The charge pump module in fig. 3 includes a charging circuit 301, a discharging circuit 302, and a dynamic cell matching module 303.
In some embodiments, the charging circuit and the discharging circuit each include a plurality of current mirror units, and the dynamic unit matching module is further configured to determine the number of current mirror units in the charging circuit or the discharging circuit that are turned on according to the charging current gear or the discharging current gear, and turn on the current mirror units in the charging circuit or the discharging circuit according to the number of current mirror units that are turned on.
As an example, the current mirror units in the charging circuit or the discharging circuit are turned on randomly according to the corresponding turn-on number, and by turning on the current mirror units randomly, the mismatch between the current mirror units, that is, the mismatch between the charging current and the discharging current, can be eliminated.
As an implementation manner, as shown in fig. 4, a schematic circuit diagram of the charge pump module is that clkin in fig. 4 is an input reference clock, and the dynamic cell matching module includes a first dynamic cell matcher DEM1 and a second dynamic cell matcher DEM 2.
In some embodiments, the current mirror unit in the charging circuit includes a P-type field effect transistor and a switch, one end of the switch is connected to a bias voltage, the other end of the switch is connected to a gate of the P-type field effect transistor, a source of the P-type field effect transistor is connected to a power supply, and a drain of the P-type field effect transistor is connected to the dynamic unit matching module.
As an example, the charging circuit includes P-type fets PM 1-PMK and switches SWP 0-SWPK, where K is the number of current mirror units, gates of the P-type fets PM 1-PMK are respectively connected to one ends of the switches SWP 1-SWPK, the other ends of the switches SWP 1-SWPK are connected to the bias voltage Vbiasp, sources of the P-type fets PM 1-PMK are all connected to the power supply voltage VDD, and drains of the P-type fets PM 1-PMK are connected to corresponding interfaces of the dynamic unit matching module.
In some embodiments, the current mirror unit in the discharge circuit includes an N-type field effect transistor and a switch, one end of the switch is connected to a bias voltage, the other end of the switch is connected to a gate of the N-type field effect transistor, a source of the N-type field effect transistor is grounded, and a drain of the N-type field effect transistor is connected to the dynamic unit matching module.
As an example, the discharge circuit comprises N-type field effect transistors NM 1-NMK, grid ends of the N-type field effect transistors NM 1-NMK are respectively connected with one ends of switches SWN 1-SWNK, the other ends of the switches SWN 1-SWNK are connected with a bias voltage Vbiasn, sources of the NMOS transistors NM 1-NMK are all grounded, and drains of the NMOS transistors NM 1-NMK are connected with corresponding interfaces of the dynamic unit matching module.
In some embodiments, the dynamic element matching module includes a first dynamic element matcher and a second dynamic element matcher;
the first dynamic unit matcher is used for determining a charging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit according to the conduction number;
the second dynamic unit matcher is used for determining a discharging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the discharge circuit according to the discharging current gear, and conducting the current mirror units in the discharge circuit according to the conduction number.
It should be noted that the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher, that is, the dynamic unit matching module includes two DEM (dynamic element matching) logics and frequency multiplication coefficient logic control.
In some embodiments, the dynamic element matching module comprises a first dynamic element matcher and/or a second dynamic element matcher;
the first dynamic unit matcher is used for determining a charging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit randomly according to the conduction number;
the second dynamic unit matcher is used for determining a discharging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the discharge circuit according to the discharging current gear, and conducting the current mirror units in the discharge circuit randomly according to the conduction number.
It should be noted that the dynamic unit matching module includes a first dynamic unit matcher and/or a second dynamic unit matcher, that is, the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher, or the dynamic unit matching module includes any one of the first dynamic unit matcher and the second dynamic unit matcher.
In some embodiments, the charge pump module further comprises a third switch and a fourth switch, one end of the third switch is connected with the charging circuit, and the other end of the third switch is connected with the loop filter; one end of the fourth switch is connected with the discharge circuit, and the other end of the fourth switch is connected with the loop filter.
It should be noted that, when the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher, one end of the third switch is indirectly connected to the charging circuit through the first dynamic unit matcher, and one end of the fourth switch is indirectly connected to the discharging circuit through the second dynamic unit matcher; when the dynamic unit matching module only comprises a first dynamic unit matcher, one end of the fourth switch is directly connected with the discharge circuit through a second dynamic unit matcher; when the dynamic unit matching module only comprises the second dynamic unit matcher, one end of the third switch is directly connected with the charging circuit through the first dynamic unit matcher.
In some embodiments, the charge pump module further comprises a switch SWP0 and a switch SWN0, one end of the switch SWP0 is connected to the first dynamic cell matcher, and the other end of the switch SWP0 is connected to the loop filter; one end of the switch SWN0 is connected to the second dynamic cell matcher, and the other end of the switch SWN0 is connected to the loop filter.
It should be noted that, the dynamic unit matching module inputs the logic part through the frequency multiplication coefficient DIV <1: N >, and obtains the control signal SEL <1: K > through the logic operation, which is used to control the switch on and off of the P-type field effect tube and the N-type field effect tube.
As one embodiment, the first dynamic unit matcher DEM1 receives the currents from the P-type field effect transistors PM 1-PMK, the currents are controlled by a clock clkin, and the random current mirror unit is conducted to enable the currents to flow in to obtain a current IcppCurrent I ofcppFlows into the switch SWP0 from one end, and the SWP0 switch is controlled by the output signal UP of the phase frequency detector; the second dynamic unit matcher DEM2 receives the current from the N-type field effect transistors NM 1-NMK, the current is controlled by the clock clkin, the random current mirror unit is conducted to enable the current to flow in, the current Icpn is obtained, and the current I is obtainedcpnFlows out of one end of a switch SWN0, and a SWN0 switch is controlled by an output signal DN of the phase frequency detector; the other end of the switch SWP0 is connected with the other end of the SWN0 to finally obtain an output current IcpTo a loop filter.
As an example, the PFETs are all the same size and the corresponding output currents are all the same, i.e., IP1＝IP2＝…＝IPKThe same N-type field effect transistors have the same size and the corresponding output currents are the same, namely IN1＝IN2＝…＝INKAnd are both equal to the current I of the reference current sourceuThe same is true.
In some embodiments, the phase-locked loop circuit further includes a bias voltage generation circuit, where the bias voltage generation circuit includes a P-type fet PB0, an N-type fet NB0, an N-type fet NB1, and a reference current source;
one end of the reference current source is connected with the source electrode of the P-type field effect transistor PB0, the drain electrode of the P-type field effect transistor PB0 is connected with the grid electrode, and the grid electrode of the P-type field effect transistor PB0 is also connected with the other end of the switch in the charging circuit;
the drain of the N-type field effect transistor NB0 is connected to the other end of the reference current source, the gate of the N-type field effect transistor NB0 is connected to the gate of the N-type field effect transistor NB1, the source of the N-type field effect transistor NB0 is connected to the ground to the source of the N-type field effect transistor NB1, and the gate of the N-type field effect transistor NB0 and the gate of the N-type field effect transistor NB1 are connected to one end of a switch in the discharge circuit.
As an example, a plurality of current mirror units in the charging circuit and the P-type field effect transistor PB0 in the bias voltage generating circuit together form a current mirror, and each current mirror unit is an output branch of the current mirror; a plurality of current mirror units in the discharge circuit and N-type field effect transistors NB0 and NB1 in the bias voltage generation circuit jointly form a current mirror, and each current mirror unit is an output branch of the current mirror.
The bias voltage generating circuit supplies bias voltages to the P-type field effect transistors PM1 to PMK and the N-type field effect transistors NM1 to NMK, respectively. BIAS voltage generating circuit is shown as BIAS in fig. 4.
As an implementation mode, according to a given frequency division coefficient DIV <1: N > range, determining the required current Icp, and determining the current gear of the charge pump module; then, a corresponding number of current mirror units are randomly selected from PM 1-PMK and NM 1-NMK by utilizing a dynamic unit matching module, and as mismatch can be regarded as independent and identically distributed events, more samples can be randomly selected, the mismatch inhibition effect is better, and based on the mismatch inhibition effect, the mismatch between the CP charging current and the CP discharging current can be effectively reduced on the basis of multiple gears, and stray is effectively inhibited.
As an example, assuming that the frequency division factor ranges from 8 to 128, the charge pump module can be configured to pump charges according to 8 to 15, 16 to 31, 32 to 63, and 64 to 128The output current of the block is divided into 4 stages, and the output current corresponding to the charge pump module is Icp、2Icp、4IcpAnd 8IcpWherein, IP＝IN＝Iu＝IcpThe current mirror units in the P-type field effect transistor and the N-type field effect transistor in the charge pump module are 8 groups in total; when the frequency division coefficient is 20, 2 current mirror units are needed corresponding to the charge pump current of 2Icp, and 2 current mirror units are randomly selected from PM 1-PM 8 and NM 1-NM 8 by using a first dynamic unit matcher and a second dynamic unit matcher of the dynamic unit matching module, so that two paths of currents with high matching degree are obtained.
According to the phase-locked loop circuit provided by the embodiment of the invention, the phase frequency detector receives the reference clock signal and the output signal of the frequency divider, and generates the charge and discharge control signal according to the phase difference between the reference clock signal and the output signal of the frequency divider; receiving a charge and discharge control signal through a charge pump module, determining charging or discharging according to the charge and discharge control signal, determining a charging or discharging current gear according to a preset frequency division coefficient, and generating a corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear; filtering the charging current or the discharging current through a loop filter to obtain a control voltage signal; generating a phase-locked loop output signal with a preset frequency according to the control voltage signal through a voltage-controlled oscillator; the charge pump charging and discharging current with multiple gears is set, the loop characteristic of the phase-locked loop is guaranteed to be optimal according to different frequency division coefficients, meanwhile, the noise of the charge pump is reduced, based on the current with multiple gears, the technical scheme of dynamic unit matching is adopted, mismatch between the charging current and the discharging current in the charge pump module can be eliminated, stray is effectively suppressed, and the bandwidth characteristic is improved.
As shown in fig. 5, the flowchart of the phase-locked loop control method according to the second embodiment of the present invention includes the following steps:
s501, acquiring a reference clock signal and a frequency division signal, and generating a charge and discharge control signal according to the phase difference of the reference clock signal and the frequency division signal;
s502, determining charging or discharging according to the charging and discharging control signal, determining a charging or discharging current gear according to a preset frequency division coefficient, and generating corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear;
s503, filtering the charging current or the discharging current to obtain a control voltage signal;
s504, generating a phase-locked loop output signal with a preset frequency according to the control voltage signal;
and S505, frequency division is carried out on the output signal of the phase-locked loop to obtain the frequency division signal.
A third embodiment of the present invention provides a charge pump, where the charge pump is configured to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, determine a current gear for charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current gear for charging or discharging.
As an embodiment, the charge pump includes a charging circuit, a discharging circuit and a dynamic cell matching module; the dynamic unit matching module is used for determining a charging current gear or a discharging current gear according to preset parameters; the charging circuit is used for generating charging current of a charging current gear; the discharging circuit is used for generating charging current of the discharging current gear. When the charge pump is applied to the phase-locked loop circuit, the preset parameter may be a frequency division coefficient of the phase-locked loop.
As an implementation manner, the charging circuit and the discharging circuit both include a plurality of current mirror units, and the dynamic unit matching module is further configured to determine the number of current mirror units in the charging circuit or the discharging circuit that are turned on according to the charging current gear or the discharging current gear, and turn on the current mirror units in the charging circuit or the discharging circuit according to the number of current mirror units that are turned on.
As an implementation manner, the current mirror unit in the charging circuit includes a first P-type field effect transistor and a first switch, one end of the first switch is connected to the bias voltage, the other end of the first switch is connected to the gate of the first P-type field effect transistor, the source of the first P-type field effect transistor is connected to the power supply, and the drain of the first P-type field effect transistor is connected to the dynamic unit matching module.
As an implementation manner, the current mirror unit in the discharge circuit includes a first N-type field effect transistor and a second switch, one end of the second switch is connected to the bias voltage, the other end of the second switch is connected to the gate of the first N-type field effect transistor, the source of the first N-type field effect transistor is grounded, and the drain of the first N-type field effect transistor is connected to the dynamic unit matching module.
As an embodiment, the dynamic unit matching module includes a first dynamic unit matcher and/or a second dynamic unit matcher; the first dynamic unit matcher is used for determining a charging current gear according to the preset parameters, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit according to the conduction number; and the second dynamic unit matcher is used for determining a discharging current gear according to the preset parameters, determining the conduction number of the current mirror units in the discharging circuit according to the discharging current gear, and conducting the current mirror units in the discharging circuit according to the conduction number.
As an embodiment, the dynamic unit matching module includes a first dynamic unit matcher and/or a second dynamic unit matcher; the first dynamic unit matcher is used for determining a charging current gear according to the preset parameters, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit randomly according to the conduction number; the second dynamic unit matcher is used for determining a discharging current gear according to the preset parameters, determining the conduction number of current mirror units in the discharging circuit according to the discharging current gear, and conducting the current mirror units in the discharging circuit randomly according to the conduction number.
According to the charge pump provided by the embodiment of the invention, the charging or discharging is determined according to the charging or discharging control signal, the charging or discharging current gear is determined, and the corresponding charging current or discharging current is generated according to the determined charging or discharging and the charging or discharging current gear, so that the mismatch between the charging current and the discharging current in the charge pump can be eliminated, and the stray can be effectively inhibited.
A fourth embodiment of the present invention provides a chip, including the phase-locked loop circuit or the charge pump according to any one of the above embodiments.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (12)
1. A phase-locked loop circuit is characterized by comprising a phase frequency detector, a charge pump module, a loop filter, a voltage-controlled oscillator and a frequency divider,
the phase frequency detector is used for receiving a reference clock signal and an output signal of the frequency divider and generating a charge and discharge control signal according to the reference clock signal and the output signal of the frequency divider;
the charge pump module is used for receiving the charge and discharge control signal, determining charging or discharging according to the charge and discharge control signal, determining a charging or discharging current gear, and generating corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear;
the loop filter is used for filtering the charging current or the discharging current to obtain a control voltage signal;
the voltage-controlled oscillator is used for generating a phase-locked loop output signal with a preset frequency according to the control voltage signal;
and the frequency divider is used for dividing the frequency of the output signal of the phase-locked loop, and inputting the frequency-divided signal into the phase frequency detector as an output signal.
2. The phase-locked loop circuit of claim 1, wherein the charge pump module comprises a charging circuit, a discharging circuit, and a dynamic cell matching module; the dynamic unit matching module is used for determining a charging current gear or a discharging current gear according to a preset frequency division coefficient; the charging circuit is used for generating a charging current of the charging current gear; the discharging circuit is used for generating the charging current of the discharging current gear.
3. The phase-locked loop circuit of claim 1, wherein the charging circuit and the discharging circuit each comprise a plurality of current mirror cells,
the dynamic unit matching module is further configured to determine the number of current mirror units in the charging circuit or the discharging circuit to be turned on according to the charging current gear or the discharging current gear, and turn on the current mirror units in the charging circuit or the discharging circuit according to the number of current mirror units to be turned on.
4. The phase-locked loop circuit of claim 3, wherein the current mirror unit of the charging circuit comprises a first P-type field effect transistor and a first switch, one end of the first switch is connected to a bias voltage, the other end of the first switch is connected to the gate of the first P-type field effect transistor, the source of the first P-type field effect transistor is connected to a power supply, and the drain of the first P-type field effect transistor is connected to the dynamic unit matching module.
5. The phase-locked loop circuit of claim 3, wherein the current mirror unit of the discharging circuit comprises a first N-type field effect transistor and a second switch, one end of the second switch is connected to a bias voltage, the other end of the second switch is connected to the gate of the first N-type field effect transistor, the source of the first N-type field effect transistor is grounded, and the drain of the first N-type field effect transistor is connected to the dynamic unit matching module.
6. The phase-locked loop circuit of claim 2, wherein the dynamic cell matching module comprises a first dynamic cell matcher and/or a second dynamic cell matcher;
the first dynamic unit matcher is used for determining a charging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit according to the conduction number;
the second dynamic unit matcher is used for determining a discharging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the discharge circuit according to the discharging current gear, and conducting the current mirror units in the discharge circuit according to the conduction number.
7. The phase-locked loop circuit of claim 2, wherein the dynamic cell matching module comprises a first dynamic cell matcher and/or a second dynamic cell matcher;
the first dynamic unit matcher is used for determining a charging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the charging circuit according to the charging current gear, and conducting the current mirror units in the charging circuit randomly according to the conduction number;
the second dynamic unit matcher is used for determining a discharging current gear according to a preset frequency division coefficient, determining the conduction number of current mirror units in the discharge circuit according to the discharging current gear, and conducting the current mirror units in the discharge circuit randomly according to the conduction number.
8. The phase-locked loop circuit of any of claims 2-7, wherein the charge pump module further comprises a third switch and a fourth switch, one end of the third switch is connected to the charging circuit, and the other end of the third switch is connected to the loop filter; one end of the fourth switch is connected with the discharge circuit, and the other end of the fourth switch is connected with the loop filter.
9. The phase-locked loop circuit of claim 4, further comprising a bias voltage generation circuit, the bias voltage generation circuit comprising a second P-type field effect transistor, a second N-type field effect transistor, a third N-type field effect transistor, and a reference current source;
one end of the reference current source is connected with the source electrode of the second P-type field effect transistor, the drain electrode of the second P-type field effect transistor is connected with the grid electrode, and the grid electrode of the second P-type field effect transistor is also connected with one end of the first switch in the charging circuit and the grid electrode of the first P-type field effect transistor;
the drain electrode of the second N-type field effect transistor is connected with the other end of the reference current source, the grid electrode of the second N-type field effect transistor is connected with the grid electrode of the third N-type field effect transistor, the source electrode of the second N-type field effect transistor is grounded with the source electrode of the third N-type field effect transistor, and the grid electrode of the second N-type field effect transistor and the grid electrode of the third N-type field effect transistor are connected with one end, connected with the bias voltage, of the second switch in the discharge circuit.
10. A phase-locked loop control method, comprising the steps of:
acquiring a reference clock signal and a frequency division signal, and generating a charge and discharge control signal according to the reference clock signal and an output signal of the frequency divider;
determining charging or discharging according to the charging and discharging control signal, determining a charging or discharging current gear, and generating a corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current gear;
filtering the charging current or the discharging current to obtain a control voltage signal;
generating a phase-locked loop output signal with a preset frequency according to the control voltage signal;
and carrying out frequency division on the output signal of the phase-locked loop to obtain the frequency division signal.
11. The charge pump is characterized in that the charge pump is used for receiving the charge and discharge control signal, determining charging or discharging according to the charge and discharge control signal, determining a current gear for charging or discharging, and generating corresponding charging current or discharging current according to the determined charging or discharging and the current gear for charging or discharging.
12. A chip comprising a phase locked loop circuit as claimed in any one of claims 1 to 9 or a charge pump as claimed in claim 11.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111677744.3A CN114301452A (en) | 2021-12-31 | 2021-12-31 | Phase-locked loop circuit, control method, charge pump and chip |
| PCT/CN2022/130896 WO2023124557A1 (en) | 2021-12-31 | 2022-11-09 | Phase-locked loop circuit, control method, charge pump, and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111677744.3A CN114301452A (en) | 2021-12-31 | 2021-12-31 | Phase-locked loop circuit, control method, charge pump and chip |
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| CN114301452A true CN114301452A (en) | 2022-04-08 |
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| CN202111677744.3A Pending CN114301452A (en) | 2021-12-31 | 2021-12-31 | Phase-locked loop circuit, control method, charge pump and chip |
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| WO (1) | WO2023124557A1 (en) |
Cited By (1)
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|---|---|---|---|---|
| WO2023124557A1 (en) * | 2021-12-31 | 2023-07-06 | 合肥市芯海电子科技有限公司 | Phase-locked loop circuit, control method, charge pump, and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7701270B2 (en) * | 2007-08-03 | 2010-04-20 | International Business Machines Corporation | Structure for a high output resistance, wide swing charge pump |
| CN106685415B (en) * | 2017-02-07 | 2024-05-07 | 江西华讯方舟智能技术有限公司 | Charge pump circuit and phase-locked loop |
| CN107634759B (en) * | 2017-09-15 | 2020-07-28 | 北京华大九天软件有限公司 | Phase-locked loop circuit capable of adapting to loop bandwidth |
| CN114301452A (en) * | 2021-12-31 | 2022-04-08 | 合肥市芯海电子科技有限公司 | Phase-locked loop circuit, control method, charge pump and chip |
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2021
- 2021-12-31 CN CN202111677744.3A patent/CN114301452A/en active Pending
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| WO2023124557A1 (en) * | 2021-12-31 | 2023-07-06 | 合肥市芯海电子科技有限公司 | Phase-locked loop circuit, control method, charge pump, and chip |
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