CN114296707A - Programmable hardware logic architecture realized based on P4 language and logic realization method - Google Patents
Programmable hardware logic architecture realized based on P4 language and logic realization method Download PDFInfo
- Publication number
- CN114296707A CN114296707A CN202210059260.0A CN202210059260A CN114296707A CN 114296707 A CN114296707 A CN 114296707A CN 202210059260 A CN202210059260 A CN 202210059260A CN 114296707 A CN114296707 A CN 114296707A
- Authority
- CN
- China
- Prior art keywords
- module
- message
- data
- descriptor
- action
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/31—Programming languages or programming paradigms
- G06F8/313—Logic programming, e.g. PROLOG programming language
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
The invention discloses a programmable hardware logic architecture and a logic implementation method based on P4 language. The programmable hardware logic architecture comprises: the device comprises a message receiving module, a data caching module, a message sending module and a programmable logic unit; the programmable logic unit further comprises: the device comprises an extraction instruction storage module, an extraction data module, a matching module, an action instruction storage module and an action module. The programmable hardware logic architecture allows a user to use a P4 language to carry out secondary development on a chip adopting the architecture, identifies any network message, carries out assignment, shift and common ALU operation on any bit field, and increases the use scene of the chip. By adopting the programmable hardware logic architecture, codes do not need to be rewritten for each new project, and hardware code development efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of programmable hardware technology, and in particular, to a programmable hardware logic architecture and a logic implementation method implemented based on the P4 language.
Background
With the development of modern communication technology, the requirement for realizing high-speed real-time communication between different networks is more and more complicated. Sometimes, control plane processing needs to be performed on a network protocol message according to an actual internet, and a customized processing of a network protocol control plane by a user cannot be supported after a traditional switching chip is subjected to tape-out, that is, a secondary development operation cannot be performed.
In order to fully liberate the programming capability of the data plane, the teaching of Nick McKeown of stanford university first designed and proposed a data plane domain-specific programming language P4 in 2014, which was proposed to be widely noticed and accepted by the academia and the industry. Industry has followed and developed a series of high performance programmable hardware. On one hand, on the basis of the customizable characteristic of programmable hardware, novel network architectures, functions and protocols can be quickly realized and verified, and network evolution and innovation are greatly accelerated; on the other hand, based on the high performance characteristics of programmable hardware, some simple network functions such as firewall and load balancing, which are conventionally implemented by flexible but low-performance middleware, can be offloaded onto a programmable data plane to achieve considerable performance improvement.
Disclosure of Invention
The invention mainly solves the technical problem of providing a programmable hardware logic architecture realized based on a P4 language, allowing a user to use the P4 language to carry out secondary development on a chip adopting the architecture, and increasing the use scene of the chip. The invention also provides a logic implementation method of the programmable hardware.
In a first aspect, the present disclosure provides a programmable hardware logic architecture implemented based on P4 language, including: the device comprises a message receiving module, a data caching module, a message sending module and a programmable logic unit; the programmable logic unit comprises: the device comprises an extraction instruction storage module, an extraction data module, a matching module, an action instruction storage module and an action module; the message receiving module is used for receiving a message, identifying whether the message is valid or not, storing the valid message into the data cache module, generating a descriptor according to the received message and outputting the descriptor to the programmable logic unit, wherein the descriptor comprises appointed part of message information and a storage address of an extraction instruction; the data caching module is used for caching the message stored by the message receiving module and providing the cached message to the message sending module; the data extracting module is used for acquiring an extracting instruction from the extracting instruction storage module according to the storage address carried by the descriptor, extracting data at a specified position from the descriptor according to the acquired extracting instruction, and outputting the obtained extracted data to the matching module; the matching module is used for comparing the extracted data with stored matching data and outputting a storage address of an action instruction to the action module according to a comparison result; the action module is used for acquiring an action instruction from the action instruction storage module according to the received storage address, correspondingly modifying the descriptor according to the acquired action instruction, and outputting the modified descriptor to the message sending module; and the message sending module is used for acquiring the message from the data caching module, acquiring the modified descriptor from the action module, and outputting the modified descriptor and the message after the modified descriptor and the message are subjected to packet splicing processing.
In some optional implementation manners, the message receiving module is specifically configured to: and when the inlet data message and the loopback data message are received simultaneously, the loopback data message is processed preferentially.
In some optional implementations, the agreed partial message information refers to message header information.
In some optional implementation manners, the message sending module is specifically configured to output the packet-spliced message to a subordinate module, or output the packet-spliced message as a loopback data message to the message receiving module again.
In some optional implementations, the data extracting module specifically adopts a register extraction manner and/or an immediate extraction manner to extract data at a specified position from the descriptor.
In some optional implementations, the matching module uses a register of a two-dimensional array structure to store the matching data.
In some alternative implementations, the action module is specifically configured to modify the descriptor by assignment, shifting, or arithmetic logic unit, ALU, operation.
In some optional implementation manners, bit widths of the message receiving module, the data caching module, and the message sending module are consistent.
In a second aspect, the present disclosure provides a logic implementation method of programmable hardware, which is used for the programmable hardware logic architecture implemented based on the P4 language as described above, and includes the following steps:
s1, the message receiving module stores the received effective message into the data cache module;
s2, the message receiving module generates a descriptor according to the received message and outputs the descriptor to the programmable logic unit, wherein the descriptor comprises appointed partial message information and a storage address of an extraction instruction;
s3, the data extraction module acquires an extraction instruction from the extraction instruction storage module according to the storage address carried by the descriptor, extracts data at a specified position from the descriptor according to the acquired extraction instruction, and outputs the acquired extraction data to the matching module;
s4, the matching module compares the extracted data with the stored matching data, and outputs the storage address of the action instruction to the action module according to the comparison result;
s5, the action module acquires an action instruction from the action instruction storage module according to the received storage address, correspondingly modifies the descriptor according to the acquired action instruction, and outputs the modified descriptor to the message sending module;
and S6, the message sending module acquires the message from the data cache module, acquires the modified descriptor from the action module, and outputs the modified descriptor and the message after the modified descriptor and the message are subjected to packet splicing processing.
In some optional implementations, the method further comprises: and if the bit field length of the message to be modified is larger than the portable length of the descriptor, the message modified by packet splicing processing is used as a loopback data message and is output to the message receiving module again.
According to the technical scheme, the invention has the following advantages:
the programmable hardware logic architecture provided by the invention allows a user to use the P4 language to carry out secondary development on a chip adopting the architecture, identifies any network message, carries out assignment, shift and common ALU operation on any bit field, and increases the use scene of the chip.
By adopting the programmable hardware logic architecture, codes do not need to be rewritten for each new project, and hardware code development efficiency is improved. Software can generate an extraction instruction, a matching instruction and an action instruction based on a P4 language, and controls hardware logic to perform corresponding processing on messages, so that the applicable scene of the chip is increased.
The invention supports the programmable function, can instantiate more RAM (Random Access Memory) in the hardware to store the programmable instruction, and provides richer application at the cost of occupying some resources. The user can conveniently and quickly perform secondary development only by being familiar with the programmable hardware logic architecture and the using steps of a compiler based on the P4 language.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a programmable hardware logic architecture implemented based on the P4 language according to an embodiment of the present invention;
FIG. 2 is a block diagram of a programmable hardware logic architecture based on the P4 language implementation in an example application scenario of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following will explain details by way of specific examples.
The embodiment of the invention provides a programmable hardware logic architecture (or a programmable hardware device) implemented based on the P4 language. The P4 language has language characteristics of reconfigurability, protocol independence and platform independence, and the basic processing flow is as follows: extracting, matching and acting. The programmable hardware logic architecture provided by the invention also adopts the processing flow of extraction, matching and action to support P4 language to re-develop the hardware logic, and the application range of a chip (such as a switching chip) adopting the programmable hardware logic architecture is increased.
Referring to the structural block diagram shown in fig. 1, in an embodiment of the present invention, the programmable hardware logic architecture includes: a message receiving module (Rx _ Pkt)10, a data Buffer module (Buffer)20, a message sending module (Tx _ Pkt)30, and a programmable logic unit (SLICE) 40.
Wherein the programmable logic unit (SLICE)40 as a core component further includes: an Extract instruction storage module (Extract _ Ram)41, an Extract data module (Extract _ Key)42, a matching module (Cmp)43, an Action instruction storage module (Action _ Ram)44, an Action module (Action)45, and the like.
The units and modules will be described in detail below.
The message receiving module (Rx _ Pkt)10 is configured to receive a message and implement a message error detection function: and identifying effective messages, discarding invalid messages, and completely storing the effective messages into the data cache module 20. When the module 10 schedules received messages, such as an ingress data message (Pkt _ in) and a loopback data message (Pkt _ lp), a loopback data message priority scheduling mode is adopted. The loopback data message is a message re-input into the message receiving module by the message sending module. The module 10 is further configured to generate a corresponding descriptor (MF) according to the received packet, and fill the appointed partial packet information into the descriptor and output the descriptor to the programmable logic unit 40. The appointed partial message information may specifically refer to message header information of a message, may be complete message header information, or may be a part of the message header information.
The data Buffer module (Buffer)20 is configured to Buffer the messages stored by the message receiving module 10, including the ingress data message and/or the loopback data message, and provide the buffered messages to the message sending module (Tx _ Pkt) 30.
The fetch instruction cache module (Extract _ Ram)41 is responsible for storing fetch instructions. The descriptor output by the message receiving module 10 may also carry a storage address of a required extraction instruction, and the address may be used to extract a corresponding storage location of the instruction cache module to obtain different extraction instructions, where the address is issued by software.
The Extract data module (Extract _ Key)42 is configured to first obtain a corresponding Extract instruction according to a storage address carried by the descriptor, then Extract data (field) at a specified location from the descriptor according to the Extract instruction, and finally output the obtained Extract data to the matching module 43. It will be readily appreciated that data (fields) anywhere in the descriptor may be fetched by different fetch instructions. The extract data module 42 may support both register extraction and immediate extraction to extract fields in descriptors, or a mixture of both. The register extraction mode is to use register addressing, namely extracting by means of relative offset positions of fields in descriptors. The immediate extraction mode does not depend on the descriptor field, and the immediate in the extraction instruction is directly taken as an extraction value.
The matching module (Cmp)43 stores matching data, and is configured to compare the extracted data output by the extracted data module 42 as data to be matched with the matching data one by one, and output a storage address of an action instruction to the action module 45 according to a result of the matching comparison, where the address is used to query the action instruction. In order to ensure the full-pipeline processing, different data extraction needs to ensure that the data matching result is counted in the same beat, and if the Ram structure is adopted, the Ram reading times are not fixed, so the invention preferably adopts a register with a two-dimensional array structure to store the matching data so as to ensure that the matching result is obtained in the same beat.
The Action command storage module (Action _ Ram)44 is used for caching an Action command set, and the matching module outputs an Action table look-up address (i.e. a storage address of an Action command), so that different Action commands can be obtained from different storage positions by using the address.
The Action module (Action)45 is configured to first obtain an Action instruction from the Action instruction storage module according to a storage address of the received Action instruction, then modify the descriptor correspondingly according to the obtained Action instruction, and finally output the modified descriptor to the message sending module 30. The modification may be assigning (i.e., setting), shifting (i.e., shifting) and ALU (arithmetic and logic unit) operation.
The message sending module (Tx _ Pkt)30 is configured to perform packet splicing processing on the modified descriptor and the message in the data caching module 20 and then output the modified descriptor and the message, where the modified descriptor and the message may be output to a lower module, or may be output to the message receiving module 10 again as a loopback data message. The packet splicing process may be understood as modifying and replacing a corresponding bit field (field) in the message, for example, masking process, according to the modified descriptor.
Further, the bit widths of the message receiving module (Rx _ Pkt)10, the data Buffer module (Buffer)20, and the message sending module (Tx _ Pkt)30 are kept consistent, so as to avoid a backpressure scene and increase the system working efficiency.
The programmable hardware logic architecture provided by the present invention is described in detail above.
An embodiment of the present invention further provides a logic implementation method of programmable hardware, which is applied to the programmable hardware logic architecture implemented based on the P4 language as described above, and a chip adopting the architecture, such as a programmable switching chip, etc. The method comprises the following steps:
s0: and the message receiving module receives the message and carries out message scheduling processing. In order to ensure order-preserving processing among messages, the priority of the looped messages is highest. When the message receiving module (Rx _ Pkt) receives the inlet data message and the loopback data message at the same time, the loopback data message is processed preferentially.
S1: the message receiving module analyzes and detects the received message, identifies the effective message, discards the invalid message and stores the effective message into the data caching module.
S2: the message receiving module generates a descriptor MF, for example, 1024-bit descriptor information, which contains the appointed partial message information and the table lookup address of the extraction instruction storage module (Extract _ Ram), which is the storage address of the required extraction instruction. Optionally, if the message only needs to perform transparent transmission operation, the Extract _ Ram lookup table address is configured as an invalid address, and step S6 is executed.
S3: the data extraction module (Extract _ Key) acquires an extraction instruction from a corresponding storage position of the extraction instruction storage module according to a storage address carried by the descriptor, and then extracts data at a specified position from the descriptor according to the acquired extraction instruction, specifically, 40 bits of 5 groups of 8-bit data can be extracted for outputting to the matching module for matching calculation. The module supports two modes of register extraction and immediate extraction.
Register fetch instruction: the 1024-bit descriptor MF is divided into 128 groups of 8 bits, and the adjacent two groups are spliced to form 16-bit data. The register extraction instruction is 10 bits, the high 7 bits are used for selecting the group number of 128 groups, and the low 3 bits are used for selecting the initial bit extracted by 16 bits, so that continuous 8-bit data at any position can be extracted.
Immediate fetch instruction: and sending the upper 8 bits of the 10-bit extraction instruction to the matching module as an immediate number.
S4: the matching module (Cmp) is responsible for storing matching data, each matching data corresponds to a storage address, and if the extracted data is consistent with the matching data, the storage address is used as a table look-up address (namely the storage address of the Action instruction) of the Action instruction storage module (Action _ Ram) and is output to the Action module; if the match is inconsistent, outputting the default unprocessed table lookup address to the action module.
S5: the Action module (Action) acquires an Action instruction from a corresponding storage position of the Action instruction storage module according to the received storage address, modifies the descriptor according to the acquired Action instruction, wherein the modification mode comprises Setting (SET), shifting (MOV) and common ALU operation, and finally outputs the modified descriptor to the message sending module (Tx _ Pkt).
The SET instruction: the instruction divides the 1024-bit descriptor into 32 groups of 32-bit data, can set any 4 bits in the 32-bit data, and can set 1 or 0.
The MOV instruction: the instruction divides the 1024-bit descriptor into 128 groups of 8-bit data, and can move any group of data to another group of data for overwriting.
ALU instructions: addition, subtraction, exclusive or, and, or, not calculation can be supported, and the operand is 1 to 32 bits in effective length.
S6: the message sending module (Tx _ Pkt) acquires the modified descriptor from the action module, and replaces the message cached in the data caching module (Buffer) with the processed message information in the modified descriptor, so as to realize the modification function of the entry data message, namely the so-called packet splicing processing. Optionally, if the bit field length of the entry packet that needs to be modified is greater than the descriptor carrying length and cannot be processed at one time, the modified entry data packet needs to be re-input to the packet sending module (Rx _ Pkt) as a loopback data packet and processed again until the packet information processing is completed.
The logic implementation method of the programmable hardware provided by the present invention is described in detail above.
In order to further understand the present invention, the following further describes a practical implementation method and practical application of the present invention by taking an actual product or system of a specific application scenario as an example.
In this embodiment, the programmable hardware logic architecture of the present invention is used in an ethernet security chip to implement classification, identification and processing of ethernet packets.
As shown in fig. 2, the structure block diagram of the programmable hardware logic architecture of this example includes a message receiving module (Rx _ Pkt), a data caching module (Buffer), a message sending module (Tx _ Pkt), a first-level programmable logic unit (SLICE0), and a second-level programmable logic unit (SLICE 1).
The programmable hardware logic architecture is used for implementing a function of classifying and masking input ethernet TCP (Transmission Control Protocol), UDP (User Datagram Protocol), and other two-layer and three-layer ethernet messages.
Next, taking an RIP (Routing Information Protocol) packet in the UDP Protocol as an example, a step of identifying the RIP packet by the programmable hardware logic architecture is described.
The programmable architecture is adopted in the embodiment mainly for increasing the application range, and after stream slicing, the UDP protocol to be supported needs to be expanded in application, and software can support the application expansion only by adding the instruction of the corresponding protocol.
First, the IPV4 RIP message format is introduced, as shown in Table 1.
TABLE 1 IPV4 RIP message Format
The following steps are introduced to implement the RIP packet classification mask, including:
1. after the message receiving module (Rx _ Pkt) fills the header information of the RIP message in the descriptor MF, the descriptor MF is sent to the first-level programmable logic unit (SLICE0), and the message is sent to the data Buffer module (Buffer).
2, SLICE0, software extracts TYPE [15:0], Version [3:0], IHL [3:0], and Protocol [7:0] fields in the message by issuing configuration extraction instruction (Extract _ Key), and sends the fields to the first-level matching module (CMP) in SLICE 0.
3. The first-stage matching module compares an input extraction field (i.e., a field to be compared) with a comparison field issued by software, and if TYPE [15:0] ═ 0x0800, Version [3:0] ═ 0x4, IHL [3:0] ═ 0x5, and Protocol [7:0] ═ 0x11, sends a matching address to an Action instruction storage module (Action _ Ram) in the SLICE0 to extract an Action instruction.
The first stage ACTION module (ACTION) in SLICE0 modifies the descriptor to look up the second stage fetch instruction lookup address and then sends the modified descriptor to the second stage programmable logic unit (SLICE 1).
The SLICE1 provides the Source Port [15:0] field in the instruction fetch message to the second level matching module (CMP) in the SLICE1 by fetching it.
6. And the second-stage matching module compares the input field to be compared with the comparison field issued by the software, and if the Source Port [15:0] is 16' h0208, the matching address is sent to an Action instruction storage module (Action _ Ram) in the SLICE1 to extract an Action instruction.
And 7, modifying the descriptor by a second-stage ACTION module (ACTION) in the SLICE1 according to the ACTION instruction, setting all values of check [15:0] fields to be 0, and then sending the modified descriptor to a message sending module (Tx _ Pkt).
8. The message sending module reads the message in the data caching module (Buffer), and covers the original message by using the message header after the descriptor mask, so that the function of classifying and masking the Ethernet (EThnet, ETH) message is realized.
Further, if the extension needs to support other UDP messages, software only needs to add a matching instruction to a matching module of the second-level programmable logic unit (SLICE1) to make the source Port [15:0] be the corresponding protocol number, thereby implementing the extension of the applicable type of the message.
In the above, an application scenario example provided by the present invention is described in detail.
In summary, the invention discloses a programmable hardware logic architecture implemented based on the P4 language, and a logic implementation method applied to the programmable hardware logic architecture.
The technical scheme of the invention has the beneficial effects that:
the programmable hardware logic architecture realized based on the P4 language allows a user to use the P4 language to carry out secondary development on a chip adopting the architecture, identifies any network message, carries out assignment, shift and common ALU operation on any bit field, and increases the use scene of the chip.
By adopting the programmable hardware logic architecture, codes do not need to be rewritten for each new project, and hardware code development efficiency is improved. Software can generate an extraction instruction, a matching instruction and an action instruction based on a P4 language, and controls hardware logic to perform corresponding processing on messages, so that the applicable scene of the chip is increased.
The invention provides richer application for supporting the programmable function, instantiating more RAMs in the hardware to store the programmable instructions and occupying more resources. The user can conveniently and quickly perform secondary development only by being familiar with the programmable hardware logic architecture and the using steps of a compiler based on the P4 language.
The technical solution of the present invention is explained in detail by the specific embodiments above. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
It should be understood that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same. The technical solutions described in the above embodiments can be modified or part of the technical features can be equivalently replaced by those skilled in the art; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the spirit and the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A programmable hardware logic architecture realized based on P4 language is characterized in that,
the method comprises the following steps: the device comprises a message receiving module, a data caching module, a message sending module and a programmable logic unit;
the programmable logic unit comprises: the device comprises an extraction instruction storage module, an extraction data module, a matching module, an action instruction storage module and an action module;
the message receiving module is used for receiving a message, identifying whether the message is valid or not, storing the valid message into the data cache module, generating a descriptor according to the received message and outputting the descriptor to the programmable logic unit, wherein the descriptor comprises appointed part of message information and a storage address of an extraction instruction;
the data caching module is used for caching the message stored by the message receiving module and providing the cached message to the message sending module;
the data extracting module is used for acquiring an extracting instruction from the extracting instruction storage module according to the storage address carried by the descriptor, extracting data at a specified position from the descriptor according to the acquired extracting instruction, and outputting the obtained extracted data to the matching module;
the matching module is used for comparing the extracted data with stored matching data and outputting a storage address of an action instruction to the action module according to a comparison result;
the action module is used for acquiring an action instruction from the action instruction storage module according to the received storage address, correspondingly modifying the descriptor according to the acquired action instruction, and outputting the modified descriptor to the message sending module;
and the message sending module is used for acquiring the message from the data caching module, acquiring the modified descriptor from the action module, and outputting the modified descriptor and the message after the modified descriptor and the message are subjected to packet splicing processing.
2. The programmable hardware logic architecture implemented based on the P4 language according to claim 1, wherein the message receiving module is specifically configured to: and when the inlet data message and the loopback data message are received simultaneously, the loopback data message is processed preferentially.
3. The P4-based programmable hardware logic architecture according to claim 1, wherein the agreed partial message information is message header information.
4. The P4-based programmable hardware logic architecture according to claim 1, wherein the message sending module is specifically configured to output a packet-processed message to a lower module, or output a packet-processed message as a loopback data message to the message receiving module again.
5. The programmable hardware logic architecture implemented based on the P4 language according to claim 1, wherein the data extracting module extracts data at a specific location from the descriptor, specifically using a register extraction method and/or an immediate extraction method.
6. The programmable hardware logic architecture implemented based on the P4 language according to claim 1, wherein the matching module employs registers of a two-dimensional array structure to store matching data.
7. The programmable hardware logic architecture implemented according to the P4 language, wherein the action module is specifically configured to modify the descriptor by assignment, shift, or Arithmetic Logic Unit (ALU) operation.
8. The programmable hardware logic architecture implemented based on the P4 language according to claim 1, wherein the bit width of the message receiving module, the data caching module and the message sending module is consistent.
9. A logic implementation method of programmable hardware, which is used for the programmable hardware logic architecture implemented based on P4 language as claimed in claim 1, and includes the following steps:
s1, the message receiving module stores the received effective message into the data cache module;
s2, the message receiving module generates a descriptor according to the received message and outputs the descriptor to the programmable logic unit, wherein the descriptor comprises appointed partial message information and a storage address of an extraction instruction;
s3, the data extraction module acquires an extraction instruction from the extraction instruction storage module according to the storage address carried by the descriptor, extracts data at a specified position from the descriptor according to the acquired extraction instruction, and outputs the acquired extraction data to the matching module;
s4, the matching module compares the extracted data with the stored matching data, and outputs the storage address of the action instruction to the action module according to the comparison result;
s5, the action module acquires an action instruction from the action instruction storage module according to the received storage address, correspondingly modifies the descriptor according to the acquired action instruction, and outputs the modified descriptor to the message sending module;
and S6, the message sending module acquires the message from the data cache module, acquires the modified descriptor from the action module, and outputs the modified descriptor and the message after the modified descriptor and the message are subjected to packet splicing processing.
10. The method of claim 9, further comprising:
and if the bit field length of the message to be modified is larger than the portable length of the descriptor, the message modified by packet splicing processing is used as a loopback data message and is output to the message receiving module again.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2021101940620 | 2021-02-20 | ||
| CN202110194062.0A CN113157254A (en) | 2021-02-20 | 2021-02-20 | Programmable hardware logic architecture realized based on P4 language and logic realization method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114296707A true CN114296707A (en) | 2022-04-08 |
Family
ID=76883414
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110194062.0A Pending CN113157254A (en) | 2021-02-20 | 2021-02-20 | Programmable hardware logic architecture realized based on P4 language and logic realization method |
| CN202210059260.0A Pending CN114296707A (en) | 2021-02-20 | 2022-01-19 | Programmable hardware logic architecture realized based on P4 language and logic realization method |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110194062.0A Pending CN113157254A (en) | 2021-02-20 | 2021-02-20 | Programmable hardware logic architecture realized based on P4 language and logic realization method |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN113157254A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113709064B (en) * | 2021-07-26 | 2022-11-01 | 中国科学院计算技术研究所 | P4 switch and data processing method thereof |
| CN113590136B (en) * | 2021-08-09 | 2024-02-27 | 郑朗 | Method for automatically generating bit domain object in JavaScript language |
| CN115086392B (en) * | 2022-06-01 | 2023-07-07 | 珠海高凌信息科技股份有限公司 | Data plane and switch based on heterogeneous chip |
-
2021
- 2021-02-20 CN CN202110194062.0A patent/CN113157254A/en active Pending
-
2022
- 2022-01-19 CN CN202210059260.0A patent/CN114296707A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN113157254A (en) | 2021-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114296707A (en) | Programmable hardware logic architecture realized based on P4 language and logic realization method | |
| US11677664B2 (en) | Apparatus and method of generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine | |
| US7586851B2 (en) | Programmable packet parsing processor | |
| US8819217B2 (en) | Intelligent graph walking | |
| US9652505B2 (en) | Content search pattern matching using deterministic finite automata (DFA) graphs | |
| US8908693B2 (en) | Flow key lookup involving multiple simultaneous cam operations to identify hash values in a hash bucket | |
| US20190149472A1 (en) | Pipelined evaluations for algorithmic forwarding route lookup | |
| CN102104541B (en) | Header processing engine | |
| US8867395B2 (en) | Accelerating data packet parsing | |
| US11729300B2 (en) | Generating programmatically defined fields of metadata for network packets | |
| JP2001094596A (en) | Device and method for packet processing | |
| US20190052553A1 (en) | Architectures and methods for deep packet inspection using alphabet and bitmap-based compression | |
| US10944696B2 (en) | Variable-length packet header vectors | |
| CN113076137B (en) | Programmable stream processing device and method based on instruction set | |
| WO2005109788A2 (en) | Programmable packet parsing processor | |
| CN116471344B (en) | Keyword extraction method, device and medium for data message | |
| Zolfaghari et al. | Run-to-Completion versus Pipelined: The Case of 100 Gbps Packet Parsing | |
| US20040258057A1 (en) | Method and hardware apparatus for implementing frame alteration commands | |
| Nordqvist et al. | Packet classification and termination in a protocol processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |