CN114283048A - Cache memory applied to three-dimensional graph depth test - Google Patents
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Abstract
The application provides a high-speed buffer memory applied to three-dimensional graph depth test, comprising: the system comprises a Cache control unit, a secondary Cache RAM memory bank, a primary high-speed Cache, a data positioning unit and a dynamic distribution unit; wherein, the Cache control unit allocates a storage address and controls a Cache Line; the second-level Cache RAM memory bank stores a second-level Cache Line; the first-level Cache caches the first-level Cache Line; the data positioning unit determines the position of the depth data in the Cache Line; the dynamic allocation unit dynamically allocates the test tasks. The response speed of the Cache is improved through the combination of two stages of caches with different speeds, the read-write delay is reduced, and the throughput is increased. When the Cache hits, only one depth data read request is sent, and a plurality of associated depth data can be returned simultaneously in one clock period.
Description
Technical Field
The present application relates to the field of three-dimensional graphics processing, and more particularly, to a cache memory for use in depth testing of three-dimensional graphics.
Background
In the segment-by-segment operation of the 3D (three-dimensional) graphics processing flow, a depth cache test is generally required to confirm the mutual occlusion relationship between pixels. In the application process, the depth buffer test algorithm needs to read the depth values of 4 fragments of a 2 × 2 block from the depth buffer area of the external memory, then test the depth values of the fragments output by the rendering, and finally write the depth values passing the test back to the external memory.
The segments output by the superordinate shading unit are organized in the abscissa (x, y) of the segment. In a depth cache, fragment data is stored and accessed in some organized manner (linear storage or block storage).
In the process of depth testing, when the testing unit receives the depth value of one fragment, the depth value under the corresponding (x, y) coordinate needs to be fetched from the depth cache for shielding testing. If a common Cache (Cache memory) is adopted, an address needs to be sent to the Cache once for each segment, and the reading and writing of depth data are requested once.
In the actual process of delivering the fragments to the depth test unit for the superior shading unit, the fragments are grouped in the form of 2 × 2 blocks in the (x, y) coordinate space. In this case, a block needs to send 4 consecutive read and write requests at maximum, if the requests are still sent for each fragment separately. Therefore, the interface waiting period of the upper layer unit is too long due to the fact that the format regularity of the data is not utilized, and a bottleneck of Cache access efficiency is generated.
Disclosure of Invention
In order to solve one of the technical defects, the application provides a cache memory applied to a three-dimensional graphics depth test.
In a first aspect of the present application, there is provided a cache memory for three-dimensional graphics depth test, the cache memory comprising: the system comprises a Cache control unit, a secondary Cache RAM memory bank, a primary high-speed Cache, a data positioning unit and a dynamic distribution unit;
wherein the content of the first and second substances,
the Cache control unit is used for allocating storage addresses and controlling Cache Line;
the secondary Cache RAM memory bank is used for storing a secondary Cache Line;
the first-level Cache is used for caching the first-level Cache Line;
the data positioning unit is used for determining the position of the depth data in the Cache Line;
and the dynamic distribution unit is used for dynamically distributing the test tasks for the lower-level test unit.
Optionally, the Cache control unit is configured to allocate a storage address to a depth value of the depth data according to a linear or block format according to a coordinate (x, y) of the depth data input by the upper coloring unit and a base address configured by the register.
Optionally, the requested data block in the Cache control unit includes 4 segments, and each segment corresponds to depth data of (x, y), (x +1, y), (x, y +1), and (x +1, y +1) coordinates.
Optionally, the requested data block is represented by (x, y) as a first address for assigning a depth value of said depth data to a storage address of the data block in a linear or block format.
Optionally, in the Cache control unit, the storage address includes a base address and an offset relative to the base address;
the offset of any segment in the data block is determined by the following equation:
OFFSET＝(X[max]～X[2]，Y[1]，Y[0]，X[1]，X[0])
wherein max is the total number of bits of the X-axis coordinate value in the binary system in any segment, X [ max ] is the value of the max-th bit of the X-axis coordinate value in the binary system in any segment, X [2] is the value of the 2 nd bit of the X-axis coordinate value in the binary system in any segment, X [1] is the value of the 1 st bit of the X-axis coordinate value in the binary system in any segment, X [0] is the value of the 0 th bit of the X-axis coordinate value in the binary system in any segment, Y [1] is the value of the 1 st bit of the Y-axis coordinate value in the binary system in any segment, and Y [0] is the value of the 0 th bit of the Y-axis coordinate value in the binary system in any segment.
Optionally, the first segment of the data block corresponds to depth data of (x, y) coordinates;
taking the hit state of the first segment as the hit state of the data block;
the high order in the address of the first segment is the identifier of the depth data of the (x, y) coordinate in the Cache RAM memory bank, and the low order is the offset address of the depth data of the (x, y) coordinate in the Cache RAM memory bank.
Optionally, the Cache control unit sends a first-level hit index to the first-level high-speed Cache according to a hit state of the generated address in the Cache Line; and meanwhile, sending the read-write cache address to the external memory.
Optionally, the first-level Cache Line and the second-level Cache Line form a two-level Cache Line;
wherein the first-level Cache Line is a high-speed Cache Line; the secondary Cache Line is a secondary speed Cache Line;
when the Cache control unit obtains a data request, the Cache control unit controls the first-level Cache Line to perform low-delay high-speed search, when the data request is not searched, the Cache control unit generates a second-level index, and the first-level Cache Line is controlled to perform search based on the second-level index.
Optionally, the data positioning unit is configured to determine a position of the requested data in the Cache Line according to an address of the data block, a sub-pixel direction, an address blocking mode, and bits per pixel.
Optionally, the dynamic allocation unit is configured to dynamically allocate a test task to a lower level test unit according to the read and write requests, the fragment mask and the data repeatability, and the cache data position.
The application provides a high-speed buffer memory applied to three-dimensional graph depth test, which comprises the following components: the system comprises a Cache control unit, a secondary Cache RAM memory bank, a primary high-speed Cache, a data positioning unit and a dynamic distribution unit; the Cache control unit is used for allocating storage addresses and controlling Cache Line; the second-level Cache RAM memory bank is used for storing a second-level Cache Line; the first-level high-speed Cache is used for caching the first-level Cache Line; the data positioning unit is used for determining the position of the depth data in the Cache Line; the dynamic distribution unit is used for dynamically distributing the test tasks for the lower-level test unit. According to the Cache processing method and device, the response speed of the Cache is improved as much as possible, the read-write delay is reduced, and the throughput is increased through the combination of two stages of caches with different rates and two algorithm units. Meanwhile, when the Cache hits, only one depth data read request is sent, and a plurality of associated depth data can be returned simultaneously in one clock period.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a cache memory for three-dimensional graphics depth test according to an embodiment of the present disclosure;
FIG. 2 is a detailed flow chart of a cache memory for three-dimensional graphics depth test according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of data organization and coordinate operation of a Cache RAM bank provided in an embodiment of the present application;
fig. 4 is a schematic diagram of coordinates, data positioning, and dynamic allocation of a Cache RAM memory bank provided in an embodiment of the present application.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In carrying out the present application, the inventors discovered that, in the actual process of delivering a fragment to a depth test unit for a superior shading unit, the fragment is organized in the form of 2 × 2 blocks in (x, y) coordinate space. In this case, a block needs to send 4 consecutive read and write requests at maximum, if the requests are still sent for each fragment separately. Therefore, the interface waiting period of the upper layer unit is too long due to the fact that the format regularity of the data is not utilized, and a bottleneck of Cache access efficiency is generated.
In view of the above problem, the embodiment of the present application provides a cache memory for three-dimensional graphics depth test, comprising: the system comprises a Cache control unit, a secondary Cache RAM memory bank, a primary high-speed Cache, a data positioning unit and a dynamic distribution unit; the Cache control unit is used for allocating storage addresses and controlling Cache Line; the second-level Cache RAM memory bank is used for storing a second-level Cache Line; the first-level high-speed Cache is used for caching the first-level Cache Line; the data positioning unit is used for determining the position of the depth data in the Cache Line; the dynamic distribution unit is used for dynamically distributing the test tasks for the lower-level test unit. According to the Cache processing method and device, the response speed of the Cache is improved as much as possible, the read-write delay is reduced, and the throughput is increased through the combination of two stages of caches with different rates and two algorithm units. Meanwhile, when the Cache hits, only one depth data read request is sent, and a plurality of associated depth data can be returned simultaneously in one clock period.
Referring to fig. 1, the present embodiment provides a cache memory applied to a three-dimensional graphics depth test, including: the system comprises a Cache control unit, a secondary Cache RAM (Random Access Memory) Memory bank, a primary Cache, a data positioning unit and a dynamic allocation unit.
1. Cache control unit
And the Cache control unit is used for distributing storage addresses and controlling the Cache Line.
In particular, the method comprises the following steps of,
and the Cache control unit is used for allocating storage addresses for the depth values of the depth data according to the coordinates (x, y) of the depth data input by the upper coloring unit and the base address configured by the register in a linear or block format.
For example, the Cache control unit is configured to allocate a storage address of a data block to a depth value of the depth data in a linear or block format according to the coordinate (x, y) of the depth data input by the upper coloring unit and a base address of the register configuration.
The data block includes 4 segments, and each segment corresponds to depth data of (x, y), (x +1, y), (x, y +1), and (x +1, y +1) coordinates.
Wherein the memory address includes a base address and an offset from the base address.
The offset of any segment in the data block is determined by the following equation:
OFFSET＝(X[max]～X[2]，Y[1]，Y[0]，X[1]，X[0])
wherein max is the total number of bits of X-axis coordinate value in binary system in any segment, X [ max ] is the value of max bit of X-axis coordinate value in binary system in any segment, X [2] is the value of 2 bit of X-axis coordinate value in binary system in any segment, X [1] is the value of 1 bit of X-axis coordinate value in binary system in any segment, X [0] is the value of 0 bit of X-axis coordinate value in binary system in any segment, Y [1] is the value of 1 bit of Y-axis coordinate value in binary system in any segment, Y [0] is the value of 0 bit of Y-axis coordinate value in binary system in any segment.
In addition, the first segment of the data block corresponds to the depth data in (x, y) coordinates.
The address of the first segment is taken as the address of the data block.
And taking the hit state of the first fragment as the hit state of the data block.
And the high order in the address of the first segment is the identification of the depth data of the (x, y) coordinate in the Cache RAM memory bank, and the low order is the offset address of the depth data of the (x, y) coordinate in the Cache RAM memory bank.
That is, the requested data block includes 4 pieces, and each piece corresponds to the depth data of (x, y), (x +1, y), (x, y +1), and (x +1, y +1) coordinates, respectively. The whole block is represented by (x, y) as a head address, and the depth value of the depth data is allocated to the storage address of the data block in a linear or block format.
In addition, the Cache control unit is also used for sending the internal index to the Cache RAM memory bank according to the hit state of the data block, and simultaneously sending the read-write address to the external memory.
That is, the Cache control unit sends a first-level hit index to a first-level high-speed Cache according to the hit state of the generated address in the Cache Line; and meanwhile, sending the read-write cache address to the external memory.
In addition, before the Cache control unit sends the internal index to the Cache RAM memory bank, the Cache control unit also sends the internal index to the register high-speed Cache memory bank, and the register high-speed Cache memory bank does not index data.
That is to say, the Cache control unit sends the internal index to the Cache bank of the register, and if the Cache bank of the register does not index data, the Cache control unit sends the internal index to the Cache RAM bank according to the hit state of the data block, and simultaneously sends the read-write address to the external memory.
2. Two-level Cache RAM memory bank
And the Cache RAM memory bank is used for storing the secondary Cache Line.
The Cache RAM memory bank is composed of a plurality of Cache lines, data are stored in one Cache Line, and a plurality of data are stored in one Cache Line.
3. One-level high-speed Cache
And the register Cache is used for caching the first-level Cache Line.
The structure of the high-speed Cache of the register is the same as that of a Cache RAM storage body, and the high-speed Cache of the register is also composed of a plurality of Cache lines, wherein the data is stored in one Cache Line, and a plurality of data are stored in one Cache Line.
A Cache RAM memory bank and a register high-speed Cache can form a secondary data Cache, and the secondary data Cache can ensure that only one depth data read request is sent when the Cache hits, so that the depth data of 4 segments in a block can be returned simultaneously in one clock period.
Wherein, the first-level Cache Line and the second-level Cache Line form a two-level Cache Line.
The first-level Cache Line is a high-speed Cache Line, and the second-level Cache Line is a secondary-speed Cache Line;
when a data request is obtained, the Cache control unit controls the first-level Cache Line to perform low-delay high-speed search, when the data request is not searched, a second-level index is generated, and the first-level Cache Line is controlled to perform search based on the second-level index.
That is, the Cache memory of the present embodiment is constituted by two levels of Cache lines. Comprises a group of high-speed first-level Cache lines and a group of secondary-speed second-level Cache lines
In the two-stage structure, when data is requested, low-delay high-speed searching is preferentially carried out in the first-stage Cache Line. When the first level misses, a second level index is generated, the request is transmitted to the second level, and so on.
4. Data positioning unit
And the data positioning unit is used for determining the position of the depth data in the Cache Line.
For example, Cache data locations are determined in Cache RAM banks or register Cache according to read and write requests.
In particular, the method comprises the following steps of,
and the data positioning unit is used for determining whether the target Cache Line exists in the high-speed Cache of the register according to the read and write requests. And if so, determining the Cache data position from the target Cache Line. And if the Cache Line does not exist, determining a target Cache Line in a Cache RAM memory bank, and determining the position of the Cache data from the target Cache Line.
For example, the position of the requested Cache data in the Cache Line is determined according to the address of the data block, the sub-pixel direction, the address blocking mode and the bits per pixel.
5. Dynamic allocation unit
And the dynamic distribution unit is used for dynamically distributing the test tasks for the lower-level test unit.
For example, test cells are allocated according to read and write requests and cache data locations.
Specifically, the dynamic allocation unit is configured to dynamically allocate a test task to the lower-level test unit according to the read and write requests, the fragment mask, the data repeatability, and the cache data position.
The Cache memory applied to the three-dimensional graphics depth test provided by the embodiment is a secondary data Cache special for the depth test, and can ensure that only one depth data read request is sent when the Cache hits, and the depth data of 4 segments in a block can be returned simultaneously in one clock cycle. Meanwhile, the architecture of the first-level register high-speed Cache and the second-level Cache RAM memory bank enables most of reading and writing operations to be concentrated at the first-level register end, the response speed of the Cache is increased, the access waiting bottleneck of the deep Cache is greatly eliminated, and the power consumption is reduced. Meanwhile, the dynamic allocation unit in the cache memory applied to the three-dimensional graphics depth test provided by the embodiment can dynamically allocate the read depth data to the plurality of processing units, so that the idle cycle of parallel processing is reduced to the maximum extent, and the processing effect is improved.
The following explains the cache memory applied to the three-dimensional graphics depth test provided in the present embodiment again. Referring to fig. 2, the Cache memory applied to the depth test of the three-dimensional graphics provided by this embodiment includes a Cache control unit, a Cache Ram bank, a register Cache, a data positioning unit, and a dynamic allocation unit. The depth data input by the upper level shading unit is organized in (x, y) coordinate space. And an address blocking operation unit in the Cache control unit allocates storage addresses for the depth values of the fragments according to (x, y) coordinates of the address blocking operation unit and the base address configured by the register according to a linear or blocking format.
Next, address assignment will be described in a 4 × 4 block format. As shown in fig. 3, the 32 segments are arranged in an organized manner in (x, y) coordinates. And storing the fragments in a Cache Line according to a configured 4 x 4 block format, and allocating addresses.
The operation formula of the address offset is as follows:
OFFSET＝(X[max]～X[2]，Y[1]，Y[0]，X[1]，X[0])
wherein max is the total number of bits of X-axis coordinate value in binary system in any segment, X [ max ] is the value of max bit of X-axis coordinate value in binary system in any segment, X [2] is the value of 2 bit of X-axis coordinate value in binary system in any segment, X [1] is the value of 1 bit of X-axis coordinate value in binary system in any segment, X [0] is the value of 0 bit of X-axis coordinate value in binary system in any segment, Y [1] is the value of 1 bit of Y-axis coordinate value in binary system in any segment, Y [0] is the value of 0 bit of Y-axis coordinate value in binary system in any segment. That is, X [ a ] represents the a-th bit of the X-axis coordinate value in binary.
When the Cache control unit judges that the Cache hits, data is organized in the Cache in the form of a plurality of Cache lines. The data of the upper level shading unit is 1 group of 4 segments. The spatial arrangement relation of the 4 segments is 2 × 2 blocks, namely (x, y), (x +1, y), (x, y +1), (x +1, y +1), wherein (x, y) is used as the first segment of a data block, and the coordinates of the first segment are used as an identifier, so that the positions and addresses of all 4 segments are automatically identified. Meanwhile, the hit state of the first segment address represents the hit state of the whole data block, the high order of the address is used as the identification tag of the Cache Line to judge the hit, and the low order of the address is used as the offset positioning in the Cache Line. And the Cache control unit sends the internal index to the internal memory of the Cache according to the hit result and simultaneously sends the read-write address to the external memory.
In addition, the Cache memory applied to the three-dimensional graphics depth test provided by the embodiment is designed by two levels of caches. In order to reduce the number of accesses to the memory bank of the second-level Cache RAM and further reduce the access latency, the embodiment designs the first-level register Cache. The register Cache takes a register as a memory bank, and further caches a large Cache Line (marked as a 2-level Line in fig. 2) in the memory bank of the Cache RAM to form a plurality of Cache lines (marked as a 1-level Line in fig. 2). When the first-stage register high-speed Cache hits, data directly flows in the first-stage high-speed storage, and the Cache Line in the first-stage register high-speed Cache is written in and read; and when the first level is not hit, the second level is applied for access.
In addition, the Cache memory applied to the three-dimensional graphics depth test provided by the embodiment can also perform Cache level pruning. The Cache control unit is independent of the primary register high-speed Cache and the secondary Cache RAM storage body, the primary register high-speed Cache can be directly bypassed between the L2 control and the L2 storage, the L2 index is directly provided for the L2 storage, and the custom level configuration of the Cache is simply realized.
In addition, when the Cache memory applied to the three-dimensional graphics depth test provided by this embodiment is used for data positioning and dynamic allocation, since one block only sends a request once, the Cache of the first-level register reads the entire Cache Line once. As shown in fig. 4, the data positioning unit restores the positions of 4 pieces of depth data in the block in the first-level register Cache or the second-level Cache RAM memory bank, and reads and writes corresponding data according to the positioning.
When data is positioned, the input is 2 x 2 block initial pixel address, sub-pixel direction, address block mode and bits per pixel. The output is the position of 4 segments in the Cache Line of the first-level register high-speed Cache or the second-level Cache RAM memory bank.
After positioning is finished, the dynamic distribution unit dynamically distributes effective data to the plurality of test units according to the fragment masks and the data repeatability, and the idle rate of the test units is reduced.
The Cache memory applied to the three-dimensional graph depth test provided by the embodiment has good performance, and utilizes a 2-level Cache structure to perform low-delay data access and write-back in a pipelined manner, so that the efficiency is improved and the power consumption is reduced; the three-dimensional graphics processing is specially optimized, and the access times to the storage are reduced.
The Cache memory applied to the three-dimensional graph depth test provided by the embodiment is convenient to use, low in module coupling, capable of directly shielding or starting the first-level Cache through changing the wiring, easy to delete or add in a user-defined mode, and good in reusability and expansibility.
The embodiment provides a cache memory applied to three-dimensional graphics depth test, which comprises the following components: the system comprises a Cache control unit, a secondary Cache RAM memory bank, a primary high-speed Cache, a data positioning unit and a dynamic distribution unit; the Cache control unit is used for allocating storage addresses and controlling Cache Line; the second-level Cache RAM memory bank is used for storing a second-level Cache Line; the first-level high-speed Cache is used for caching the first-level Cache Line; the data positioning unit is used for determining the position of the depth data in the Cache Line; the dynamic distribution unit is used for dynamically distributing the test tasks for the lower-level test unit. According to the Cache processing method and device, the response speed of the Cache is improved as much as possible, the read-write delay is reduced, and the throughput is increased through the combination of two stages of caches with different rates and two algorithm units. Meanwhile, when the Cache hits, only one depth data read request is sent, and a plurality of associated depth data can be returned simultaneously in one clock period.
It will be apparent to those skilled in the art that while the preferred embodiments of the present application have been described, additional variations and modifications in these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A cache memory for three-dimensional graphics depth testing, the cache memory comprising: the system comprises a Cache control unit, a secondary Cache RAM memory bank, a primary high-speed Cache, a data positioning unit and a dynamic distribution unit;
wherein the content of the first and second substances,
the Cache control unit is used for allocating storage addresses and controlling Cache Line;
the secondary Cache RAM memory bank is used for storing a secondary Cache Line;
the first-level Cache is used for caching the first-level Cache Line;
the data positioning unit is used for determining the position of the depth data in the Cache Line;
and the dynamic distribution unit is used for dynamically distributing the test tasks for the lower-level test unit.
2. The Cache memory according to claim 1, wherein the Cache control unit is configured to allocate a storage address for a depth value of the depth data in a linear or block format according to a coordinate (x, y) of the depth data input by the upper shading unit and a base address of a register configuration.
3. The Cache memory according to claim 2, wherein the requested data block in the Cache control unit comprises 4 segments, each segment corresponding to depth data of (x, y), (x +1, y), (x, y +1), and (x +1, y +1) coordinates.
4. A cache memory according to claim 3, wherein the requested data block is represented by (x, y) as a first address for allocating a depth value of said depth data to a storage address of the data block in a linear or block format.
5. The Cache memory according to claim 4, wherein in the Cache control unit, the memory address comprises a base address and an offset relative to the base address;
the offset of any segment in the data block is determined by the following equation:
OFFSET＝(X[max]～X[2],Y[1],Y[0],X[1],X[0])
wherein max is the total number of bits of the X-axis coordinate value in the binary system in any segment, X [ max ] is the value of the max-th bit of the X-axis coordinate value in the binary system in any segment, X [2] is the value of the 2 nd bit of the X-axis coordinate value in the binary system in any segment, X [1] is the value of the 1 st bit of the X-axis coordinate value in the binary system in any segment, X [0] is the value of the 0 th bit of the X-axis coordinate value in the binary system in any segment, Y [1] is the value of the 1 st bit of the Y-axis coordinate value in the binary system in any segment, and Y [0] is the value of the 0 th bit of the Y-axis coordinate value in the binary system in any segment.
6. The cache memory of claim 4, wherein the first segment of the data block corresponds to depth data in (x, y) coordinates;
taking the hit state of the first segment as the hit state of the data block;
the high order in the address of the first segment is the identifier of the depth data of the (x, y) coordinate in the Cache RAM memory bank, and the low order is the offset address of the depth data of the (x, y) coordinate in the Cache RAM memory bank.
7. The Cache memory according to claim 2, wherein the Cache control unit sends a first-level hit index to the first-level Cache according to a hit state of the generated address in the Cache Line; and meanwhile, sending the read-write cache address to the external memory.
8. The Cache memory according to claim 1, wherein the first-level Cache Line and the second-level Cache Line form a two-level Cache Line;
wherein the first-level Cache Line is a high-speed Cache Line; the secondary Cache Line is a secondary speed Cache Line;
when the Cache control unit obtains a data request, the Cache control unit controls the first-level Cache Line to perform low-delay high-speed search, when the data request is not searched, the Cache control unit generates a second-level index, and the first-level Cache Line is controlled to perform search based on the second-level index.
9. The Cache memory according to claim 1, wherein the data positioning unit is configured to determine a location of the requested data in the Cache Line according to an address of the data block, a sub-pixel direction, an address blocking mode, and bits per pixel.
10. The cache memory of claim 1, wherein the dynamic allocation unit is configured to dynamically allocate test tasks for subordinate test units according to read and write requests, segment masks and data redundancy, and cache data locations.
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