CN114267628A - Ultra-thin silicon-on-insulator (SOI) substrate and preparation method thereof - Google Patents
Ultra-thin silicon-on-insulator (SOI) substrate and preparation method thereof Download PDFInfo
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Abstract
The application discloses an ultrathin silicon-on-insulator (SOI) substrate and a preparation method thereof, wherein the preparation method comprises the following steps: providing a monocrystalline silicon back substrate, and forming a buried oxide layer with a first thickness on the upper surface of the monocrystalline silicon back substrate; etching the buried oxide layer and forming a window penetrating through the buried oxide layer, wherein the window exposes part of the upper surface of the monocrystalline silicon back substrate; taking the monocrystalline silicon back substrate as seed crystal, and growing a monocrystalline silicon layer with a second thickness along the window; the monocrystalline silicon layer covers the upper surface of the buried oxide layer and the window, and the crystal orientation of the monocrystalline silicon layer is the same as that of the monocrystalline silicon back substrate. The SOI substrate of the present application has a thin buried oxide layer and a single crystal silicon layer, which can reduce threshold voltage variability by improving short channel effect to enhance the stability of the substrate. In addition, the buried oxide layer and the single crystal silicon layer each have good thickness uniformity, which can reduce threshold voltage variability caused by thickness unevenness.
Description
Technical Field
The present application relates to the field of semiconductor related technologies, and in particular, to an ultra-thin silicon-on-insulator (SOI) substrate and a method for manufacturing the same.
Background
SOI refers to a silicon substrate technology on an insulating substrate, and an integrated circuit fabricated using the SOI substrate technology is widely used in the fields of high speed, low power consumption, high integration, and high reliability due to advantages of low parasitic capacitance, low short channel effect, low power consumption, and good latch-up resistance. The SOI substrate comprises substrate bulk silicon, a buried oxide layer and top layer silicon, wherein the thickness and the thickness uniformity of the buried oxide layer and the top layer silicon are important parameters influencing the quality of the SOI substrate. If the SOI substrate has an ultra-thin top silicon layer and a buried oxide layer, an integrated circuit prepared by using the SOI substrate has better performance. However, the conventional preparation method of the SOI substrate cannot obtain an ultrathin buried oxide layer and top silicon, and the thickness uniformity of the buried oxide layer and the top silicon is not easy to control, so that the quality of the SOI substrate is influenced, and the application range of the SOI substrate in the fields of high speed, low voltage and low power consumption is limited.
Disclosure of Invention
An object of the present application is to provide a method of manufacturing an ultra-thin silicon-on-insulator (SOI) substrate by which a buried oxide layer and a single crystal silicon layer, which are thin and have good thickness uniformity, can be manufactured, which can reduce a threshold voltage (V)T) The variability enhances the stability of the SOI substrate and increases the application range of the SOI substrate in the fields of low voltage and low power consumption.
It is another object to provide an ultra-thin silicon-on-insulator (SOI) substrate.
In a first aspect, embodiments of the present application provide a method for preparing an ultra-thin silicon-on-insulator (SOI) substrate, which includes the following steps:
providing a monocrystalline silicon back substrate, and forming a buried oxide layer with a first thickness on the upper surface of the monocrystalline silicon back substrate;
etching the buried oxide layer and forming a window penetrating through the buried oxide layer, wherein the window exposes part of the upper surface of the monocrystalline silicon back substrate;
taking the monocrystalline silicon back substrate as seed crystal, and growing a monocrystalline silicon layer with a second thickness along the window; the monocrystalline silicon layer covers the upper surface of the buried oxide layer and the window, and the crystal orientation of the monocrystalline silicon layer is the same as that of the monocrystalline silicon back substrate.
In one possible embodiment, the step of seeding a monocrystalline silicon back substrate and growing a monocrystalline silicon layer having a second thickness along the window comprises:
depositing an amorphous silicon layer or a polycrystalline silicon layer on the upper surface of the buried oxide layer and the window;
annealing the amorphous silicon layer or the polycrystalline silicon layer; the amorphous silicon layer or the polycrystalline silicon layer takes the monocrystalline silicon back substrate as seed crystal and is crystallized from the window to form the monocrystalline silicon layer with the same crystal orientation as the monocrystalline silicon back substrate.
In one possible embodiment, the thickness of the single crystal silicon layer depends on the thickness of the amorphous silicon layer or the polycrystalline silicon layer.
In one possible embodiment, in the step of seeding a single-crystal silicon back substrate and growing a single-crystal silicon layer having a second thickness along the window, the number of the single-crystal silicon layers is one;
or, the number of the monocrystalline silicon layers is multiple, and the multiple monocrystalline silicon layers are arranged along the height direction of the monocrystalline silicon back substrate (vertical to the upper surface of the monocrystalline silicon back substrate); the monocrystalline silicon layer is defined as a 1 st monocrystalline silicon layer, an n-1 st monocrystalline silicon layer and an n-th monocrystalline silicon layer in the order from bottom to top, wherein n is greater than or equal to 2; and depositing an amorphous silicon layer or a polycrystalline silicon layer on the upper surface of the n-1 th monocrystalline silicon layer, wherein the amorphous silicon layer or the polycrystalline silicon layer takes the n-1 th monocrystalline silicon layer as a seed crystal and is crystallized into the n-th monocrystalline silicon layer.
In a second aspect, embodiments of the present application provide an ultra-thin silicon-on-insulator (SOI) substrate, comprising:
a monocrystalline silicon back substrate;
the buried oxide layer with the first thickness is arranged on the upper surface of the monocrystalline silicon back substrate; the buried oxide layer is provided with a window, and the window penetrates through the buried oxide layer and exposes out of part of the upper surface of the monocrystalline silicon back substrate;
a monocrystalline silicon layer with a second thickness covering the upper surface of the buried oxide layer and the window; the monocrystalline silicon layer is formed by crystallizing an amorphous silicon layer or a polycrystalline silicon layer by taking a monocrystalline silicon back substrate as a seed crystal and taking a window as a growth window; the crystal orientation of the monocrystalline silicon layer is the same as the crystal orientation of the monocrystalline silicon back substrate.
In one possible embodiment, the total area of the windows is equal to or greater than 1% of the total area of the upper surface of the monocrystalline silicon back substrate.
In one possible embodiment, the window has a circular, polygonal, arcuate or circular cross-section.
In one possible embodiment, the thickness of the single crystal silicon layer is equal to or less than 20 nm; the thickness of the buried oxide layer is equal to or less than 50 nm.
In one possible embodiment, the thickness of the monocrystalline silicon layer is between 10 and 15nm or between 5 and 10 nm; the thickness of the buried oxide layer is 20-30 nm or 10-20 nm.
In one possible embodiment, the thickness uniformity of both the buried oxide layer and the single crystal silicon layer is equal to or less than 5 angstroms.
In one possible embodiment, the single crystal silicon layer has a crystal orientation of [100], [110] or [111 ]; the crystal orientation of the monocrystalline silicon back substrate is the same as the crystal orientation of the monocrystalline silicon layer.
In one possible embodiment, the number of single crystal silicon layers is one; alternatively, the number of the single crystal silicon layers is plural, and the plural single crystal silicon layers are arranged in the height direction of the single crystal silicon back substrate (perpendicular to the upper surface of the single crystal silicon back substrate).
Compared with the prior art, the beneficial effects of this application are as follows at least:
1) the SOI substrate with the thin buried oxide layer and the single crystal silicon layer and with good thickness uniformity can be obtained by the preparation method provided by the application, and the SOI substrate has the thin buried oxide layer and the single crystal silicon layer, has small vertical field, improves short channel effect and reduces threshold voltage (V)T) The variability enhances the stability of the SOI substrate and increases the application range of the SOI substrate in the fields of low voltage and low power consumption. In addition, the buried oxide layer and the single crystal silicon layer each have good thickness uniformity, which can reduce the threshold voltage (V) caused by thickness non-uniformityT) Variability.
2) The preparation method provided by the application takes the monocrystalline silicon backing substrate as the seed crystal and takes the window as the growth window to grow the monocrystalline silicon layer with the same crystal orientation as the monocrystalline silicon backing substrate, namely the SOI substrate with the monocrystalline silicon layer with the specific crystal orientation can be prepared by the method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a schematic diagram illustrating a method of fabricating an ultra-thin silicon-on-insulator (SOI) substrate wafer according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a single crystal silicon backing substrate with a buried oxide layer formed thereon according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a buried oxide layer with a window provided thereon according to an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of an amorphous silicon layer or a polysilicon layer formed on the upper surface and at the window of the buried oxide layer according to an embodiment of the present disclosure;
fig. 5 is a schematic cross-sectional view of an ultra-thin silicon-on-insulator (SOI) substrate according to an embodiment of the present application.
Illustration of the drawings:
100 monocrystalline silicon back substrate; 200 burying an oxide layer; 210 windows; 300 a layer of amorphous silicon or polysilicon; 400 single crystal silicon layer.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and variations in various respects, all without departing from the spirit of the present application.
In the description of the present application, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," etc. are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Conventional methods for fabricating existing silicon-on-insulator (SOI) substrate substrates include Epitaxial Layer Transfer (ELTRAN) or Smart Cut. When the preparation method is used for preparing the SOI substrate, the thickness and the thickness uniformity of the buried oxide layer and the single crystal silicon layer are not easy to control, and the preparation method is not suitable for preparing the SOI substrate with the thickness of the single crystal silicon layer less than 100nm, so that the quality of the SOI substrate is influenced, and the application range of the SOI substrate in the fields of high speed, low pressure and low power consumption is limited. In addition, when the conventional production method is used to produce an SOI substrate, the crystal orientation of the single crystal silicon layer is random, and an SOI substrate having a single crystal silicon layer with a specific crystal orientation cannot be produced. Therefore, the present application is directed to an ultra-thin silicon-on-insulator (SOI) substrate and a method for fabricating the same, which solve the problems of the conventional silicon-on-insulator (SOI) substrate.
According to one aspect of the present application, a method of fabricating an ultra-thin silicon-on-insulator (SOI) substrate is provided. Referring to fig. 1, the preparation method comprises the following steps:
s1, providing a single-crystal silicon back substrate 100, and forming a buried oxide layer 200 with a first thickness on the upper surface of the single-crystal silicon back substrate 100.
In one embodiment, referring to FIG. 2, the crystal orientation of single crystal silicon back substrate 100 can be selected as [100], [110], or [111 ]. A buried oxide layer 200 is formed on the upper surface of the single-crystal silicon back substrate 100, and the material of the buried oxide layer 200 is an oxide of silicon, specifically including one or more of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride, which may be formed by a method such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The buried oxide layer 200 has a thickness equal to or less than 50nm and a thickness uniformity equal to or less than 5 angstroms. Preferably, the thickness of the buried oxide layer 200 is between 20nm and 30nm or between 10nm and 20 nm.
S2, the buried oxide layer 200 is etched, and a window 210 is formed through the buried oxide layer 200, the window 210 exposing a portion of the upper surface of the single-crystal silicon back substrate 100.
In one embodiment, referring to fig. 3, the buried oxide layer 200 is etched and a window 210 is formed for subsequent growth of a single crystal silicon layer, the window 210 extending through the buried oxide layer 200 from top to bottom and exposing a portion of the upper surface of the single crystal silicon back substrate 100. The number of the windows 210 may be one or more; when the number of the windows 210 is plural, the plural windows 210 are arranged on the buried oxide layer 200 in a predetermined arrangement. The cross-section of the window 210 is circular, polygonal, arc-shaped or ring-shaped, and its total area is equal to or more than 1% of the total area of the upper surface of the single-crystal silicon back substrate 100.
When the SOI substrate is subsequently utilized to manufacture an SOI device, a Shallow Trench (STI) needs to be manufactured on the SOI substrate, the position of the Shallow Trench (STI) is the same as that of the window 210, and the Shallow Trench (STI) is further etched on the basis of the window 210. The total area of the Shallow Trenches (STI) is 10-50% of the total area of the upper surface of the monocrystalline silicon back substrate 100.
S3, taking the monocrystalline silicon back substrate 100 as a seed crystal, and growing a monocrystalline silicon layer 400 with a second thickness along the window 210; the monocrystalline silicon layer 400 covers the upper surface of the buried oxide layer 200 and the window 210, and has the same crystal orientation as the monocrystalline silicon back substrate 100.
In one embodiment, referring to fig. 4 and 5, an amorphous silicon layer or polysilicon layer 300 is deposited on the upper surface of the buried oxide layer 200 and the window 210. And annealing the amorphous silicon layer or the polysilicon layer 300, wherein the amorphous silicon layer or the polysilicon layer 300 takes the monocrystalline silicon back substrate 100 as a seed crystal and is crystallized from the window 210 to form the monocrystalline silicon layer 400 with the same crystal orientation as the monocrystalline silicon back substrate 100. The thickness of the single crystal silicon layer 400 is equal to or less than 20nm and the thickness uniformity is equal to or less than 5 angstroms. Preferably, the thickness of the single crystal silicon layer 400 is 10 to 15nm or 5 to 10 nm.
When the amorphous silicon layer or polysilicon layer 300 is annealed, the SOI substrate is placed in a vacuum or at a low pressure (inert gas or H2 ambient) and annealed at 1400 ℃, the amorphous silicon layer or polysilicon layer 300 begins to crystallize from the window 210 and continues to crystallize the amorphous silicon layer or polysilicon layer 300 on the top surface of the buried oxide layer 200 into the single crystal silicon layer 400. Since the amorphous silicon layer or the polysilicon layer 300 is connected to the single crystal silicon back substrate 100 through the window 210, the amorphous silicon layer or the polysilicon layer 300 is crystallized into the single crystal silicon layer 400 having the same crystal orientation as the single crystal silicon back substrate 100 with the single crystal silicon back substrate 100 as a seed crystal and the window 210 as a growth window. For example, when the crystal orientation of the single-crystal silicon back substrate 100 is [100], the crystal orientation of the single-crystal silicon layer 400 is [100 ]; when the crystal orientation of the single-crystal silicon back substrate 100 is [110], the crystal orientation of the single-crystal silicon layer 400 is [110 ].
When the amorphous silicon layer or the polycrystalline silicon layer 300 is annealed, the entire region of the amorphous silicon layer or the polycrystalline silicon layer 300 is simultaneously annealed by using a heater, white light, or laser scanning; alternatively, the annealing process is performed on a local region of the amorphous silicon layer or the polycrystalline silicon layer 300 by multi-channel scanning using a heater, white light, or laser.
Preferably, after the formation of the single crystal silicon layer 400, the entire SOI substrate may be subjected to hydrogen H2And processed to smooth the surface of the single crystal silicon layer 400.
In the present embodiment, the thicknesses of the buried oxide layer 200 and the single crystal silicon layer 400 are determined by the thickness of the deposited silicon oxide before the annealing process and the thickness of the amorphous silicon layer or the polysilicon layer 300, respectively.
In one embodiment, in the step of seeding the single crystal silicon back substrate 100 and growing the single crystal silicon layer 400 having the second thickness along the window 210, the number of the single crystal silicon layers 400 is one.
As an alternative embodiment, the number of the single crystal silicon layers 400 is plural, and the crystal orientation is the same between the plural single crystal silicon layers 400. A plurality of single crystal silicon layers 400 are arranged in a direction of a height of the single crystal silicon back substrate 100 (perpendicular to an upper surface of the single crystal silicon back substrate 100), the single crystal silicon layers 400 being defined as a 1 st single crystal silicon layer, an n-1 st single crystal silicon layer, and an n-th single crystal silicon layer, n being greater than or equal to 2, in that order from bottom to top. And depositing an amorphous silicon layer or a polycrystalline silicon layer with a preset thickness on the upper surface of the n-1 th monocrystalline silicon layer, wherein the amorphous silicon layer or the polycrystalline silicon layer takes the n-1 th monocrystalline silicon layer as a seed crystal and is crystallized into the n-th monocrystalline silicon layer.
According to one aspect of the present application, an ultra-thin silicon-on-insulator (SOI) substrate is provided. The ultra-thin silicon-on-insulator (SOI) substrate was prepared by the preparation method in the above example. Referring to fig. 5, the ultra-thin silicon-on-insulator (SOI) substrate includes a single crystal silicon back substrate 100, a buried oxide layer 200, and a single crystal silicon layer 400. The buried oxide layer 200 is arranged on the upper surface of the monocrystalline silicon back substrate 100 and is provided with a window 210; the window 210 penetrates the buried oxide layer 200 from top to bottom and exposes a portion of the upper surface of the single-crystal silicon back substrate 100; the buried oxide layer 200 has a first thickness. The monocrystalline silicon layer 400 covers the upper surface of the buried oxide layer 200 and the window 210, and the monocrystalline silicon layer 400 is crystallized from the amorphous silicon layer or the polycrystalline silicon layer 300 by taking the monocrystalline silicon back substrate 100 as a seed crystal and the window 210 as a growth window; the crystal orientation of the single crystal silicon layer 400 is the same as that of the single crystal silicon back substrate 100; the single crystal silicon layer 400 has a second thickness.
Wherein, the crystal orientation of the monocrystalline silicon back substrate 100 can be selected as [100], [110] or [111 ]. When the crystal orientation of the single-crystal silicon back substrate 100 is [100], the crystal orientation of the single-crystal silicon layer 400 is [100 ]; when the crystal orientation of the single-crystal silicon back substrate 100 is [110], the crystal orientation of the single-crystal silicon layer 400 is [110 ].
In one embodiment, the number of windows 210 may be one or more; when the number of the windows 210 is plural, the plural windows 210 are arranged on the buried oxide layer 200 in a predetermined arrangement. The cross-section of the window 210 is circular, polygonal, arc-shaped or ring-shaped, and its total area is equal to or more than 1% of the total area of the upper surface of the single-crystal silicon back substrate 100.
In one embodiment, the buried oxide layer 200 is one or more of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, or a silicon oxynitride layer. The buried oxide layer 200 has a thickness equal to or less than 50nm and a thickness uniformity equal to or less than 5 angstroms. Preferably, the thickness of the buried oxide layer 200 is between 20nm and 30nm or between 10nm and 20 nm.
The thickness of the single crystal silicon layer 400 is equal to or less than 20nm and the thickness uniformity is equal to or less than 5 angstroms. Preferably, the thickness of the single crystal silicon layer is 10 to 15nm or 5 to 10 nm.
It should be noted that the thickness and thickness uniformity of the single crystal silicon layer 400 and the buried oxide layer 200 are exemplary, and the thickness and thickness uniformity of the single crystal silicon layer 400 and the buried oxide layer 200 can be adjusted according to the practical application requirements of a silicon-on-insulator (SOI) substrate.
In one embodiment, the number of the single crystal silicon layers 400 is one; alternatively, the number of the single crystal silicon layers 400 is plural. When the number of the single crystal silicon layers 400 is plural, the plural single crystal silicon layers 400 are arranged in a height direction (perpendicular to an upper surface of the single crystal silicon back substrate 100) of the single crystal silicon back substrate 100, and crystal directions between the plural single crystal silicon layers 400 are the same. The plurality of single crystal silicon layers 400 are defined as a 1 st single crystal silicon layer, an n-1 st single crystal silicon layer, and an n-th single crystal silicon layer in order from bottom to top, n being greater than or equal to 2. And depositing an amorphous silicon layer or a polycrystalline silicon layer with a preset thickness on the upper surface of the n-1 th monocrystalline silicon layer, wherein the amorphous silicon layer or the polycrystalline silicon layer takes the n-1 th monocrystalline silicon layer as a seed crystal and is crystallized into the n-th monocrystalline silicon layer.
From the above technical solutions, it can be seen that the SOI substrate having the buried oxide layer 200 and the single crystal silicon layer 400 with thin and good thickness uniformity, which has a small vertical field due to the thin buried oxide layer 200 and the single crystal silicon layer 400, can be obtained by the preparation method provided in the present application, which improves the short channel effect and reduces the threshold voltage (V)T) The variability enhances the stability of the SOI substrate and increases the application range of the SOI substrate in the fields of low voltage and low power consumption. In addition, the buried oxide layer 200 and the single crystal silicon layer 400 each have good thickness uniformity, which can reduce the threshold voltage (V) caused by thickness non-uniformityT) Variability.
Further, the preparation method provided by the present application uses the monocrystalline silicon back substrate 100 as a seed crystal and uses the window 210 as a growth window to grow the monocrystalline silicon layer 400 with the same crystal orientation as the monocrystalline silicon back substrate 100, i.e. the SOI substrate having the monocrystalline silicon layer 400 with a specific crystal orientation can be prepared by using the method.
The foregoing is only a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and substitutions can be made without departing from the technical principle of the present application, and these modifications and substitutions should also be regarded as the protection scope of the present application.
Claims (12)
1. A method of making an ultra-thin silicon-on-insulator (SOI) substrate, comprising:
providing a monocrystalline silicon back substrate, and forming a buried oxide layer with a first thickness on the upper surface of the monocrystalline silicon back substrate;
etching the buried oxide layer and forming a window penetrating through the buried oxide layer, wherein the window exposes part of the upper surface of the monocrystalline silicon back substrate;
taking the monocrystalline silicon back substrate as a seed crystal, and growing a monocrystalline silicon layer with a second thickness along the window; the monocrystalline silicon layer covers the upper surface of the buried oxide layer and the window, and the crystal orientation of the monocrystalline silicon layer is the same as that of the monocrystalline silicon back substrate.
2. The method of claim 1, wherein the step of seeding a single crystal silicon back substrate and growing a single crystal silicon layer having a second thickness along the window comprises:
depositing an amorphous silicon layer or a polysilicon layer on the upper surface of the buried oxide layer and the window;
annealing the amorphous silicon layer or the polycrystalline silicon layer; the amorphous silicon layer or the polycrystalline silicon layer takes the monocrystalline silicon back substrate as seed crystal and is crystallized from the window to be the monocrystalline silicon layer with the same crystal orientation as the monocrystalline silicon back substrate.
3. The method of manufacturing an ultra-thin silicon-on-insulator (SOI) substrate according to claim 2, wherein the thickness of the single crystal silicon layer depends on the thickness of the amorphous silicon layer or the polycrystalline silicon layer.
4. The method for manufacturing an ultra-thin silicon-on-insulator (SOI) substrate base wafer according to any one of claims 1 to 3, wherein in the step of seeding the single-crystal silicon back substrate and growing a single-crystal silicon layer having a second thickness along the window, the number of the single-crystal silicon layer is one;
or the number of the single crystal silicon layers is multiple, and the multiple single crystal silicon layers are arranged along the height direction of the single crystal silicon backing bottom (vertical to the upper surface of the single crystal silicon backing bottom); the monocrystalline silicon layer is defined as a 1 st monocrystalline silicon layer, an n-1 st monocrystalline silicon layer and an n-th monocrystalline silicon layer in the order from bottom to top, wherein n is greater than or equal to 2; and depositing an amorphous silicon layer or a polycrystalline silicon layer on the upper surface of the n-1 th monocrystalline silicon layer, wherein the amorphous silicon layer or the polycrystalline silicon layer takes the n-1 th monocrystalline silicon layer as a seed crystal and is crystallized into the n-th monocrystalline silicon layer.
5. An ultra-thin silicon-on-insulator (SOI) substrate comprising:
a monocrystalline silicon back substrate;
the buried oxide layer with a first thickness is arranged on the upper surface of the monocrystalline silicon back substrate; the buried oxide layer is provided with a window, and the window penetrates through the buried oxide layer and exposes out of part of the upper surface of the monocrystalline silicon back substrate;
a single crystal silicon layer having a second thickness covering the upper surface of the buried oxide layer and the window; the monocrystalline silicon layer is formed by crystallizing an amorphous silicon layer or a polycrystalline silicon layer by taking the monocrystalline silicon back substrate as a seed crystal and taking the window as a growth window; the crystal orientation of the monocrystalline silicon layer is the same as that of the monocrystalline silicon back substrate.
6. The ultra-thin silicon-on-insulator (SOI) substrate wafer of claim 5, wherein the total area of the windows is equal to or greater than 1% of the total area of the upper surface of the single-crystal silicon back-substrate.
7. The ultra-thin silicon-on-insulator (SOI) substrate according to claim 5, wherein the window has a cross-section of a circle, a polygon, an arc or a ring shape.
8. The ultra-thin silicon-on-insulator (SOI) substrate according to claim 5, wherein the thickness of the single crystal silicon layer is equal to or less than 20 nm; the thickness of the buried oxide layer is equal to or less than 50 nm.
9. The ultra-thin silicon-on-insulator (SOI) substrate according to claim 8, wherein the thickness of the single crystal silicon layer is 10 to 15nm or 5 to 10 nm; the thickness of the buried oxide layer is 20-30 nm or 10-20 nm.
10. The ultra-thin silicon-on-insulator (SOI) substrate of claim 5, wherein the buried oxide layer and the single crystal silicon layer each have a thickness uniformity of 5 angstroms or less.
11. The ultra-thin silicon-on-insulator (SOI) substrate according to claim 5, wherein the single crystal silicon layer has a crystal orientation of [100], [110] or [111 ]; the crystal orientation of the monocrystalline silicon back substrate is the same as that of the monocrystalline silicon layer.
12. The ultra-thin silicon-on-insulator (SOI) substrate as claimed in any one of claims 5 to 11, wherein the number of the single crystal silicon layers is one; or, the number of the single crystal silicon layers is multiple, and the multiple single crystal silicon layers are arranged along the height direction of the single crystal silicon backing bottom (vertical to the upper surface of the single crystal silicon backing bottom).
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| CN112242342A (en) * | 2019-07-17 | 2021-01-19 | 上海新微技术研发中心有限公司 | Monocrystalline silicon local area SOI substrate, photoelectric device and preparation method |
| CN111564528A (en) * | 2020-05-29 | 2020-08-21 | 佛山职业技术学院 | Preparation process of polycrystalline silicon multi-grain film |
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