CN114265147A - Optical communication waveband broadband high-efficiency horizontal end face coupler and manufacturing method thereof - Google Patents
Optical communication waveband broadband high-efficiency horizontal end face coupler and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a wide-bandwidth high-efficiency horizontal end face coupler of an optical communication waveband and a manufacturing method thereof, wherein the coupler comprises the following steps: the silicon substrate layer, the silicon dioxide coating layer and the fully-etched inverted cone-shaped silicon nanowire waveguide are arranged on the silicon substrate layer; and three silicon nitride waveguide arrays with the same quantity, size and structure are arranged in the silicon dioxide coating layer above the fully-etched inverted cone silicon nanowire waveguide. The high-efficiency and large-bandwidth silicon integrated photonic chip can realize the high-efficiency and large-bandwidth non-polarization-related effective coupling of the common single-mode optical fiber and the silicon integrated photonic chip in an optical communication waveband, has the obvious advantages of large alignment tolerance, flexible selection of device structure parameters, easiness in processing and the like, and is favorable for promoting the packaging of the silicon integrated optical chip and further the application research in the aspects of optical communication and optical interconnection.
Description
Technical Field
The invention belongs to the technical field of structural design and manufacturing of silicon-based integrated optoelectronic devices, and particularly relates to an optical communication waveband wide-bandwidth high-efficiency horizontal end face coupler and a manufacturing method thereof, in particular to an optical communication waveband wide-bandwidth high-efficiency polarization independent horizontal end face coupler and a high-efficiency preparation method thereof.
Background
The coupling mode of the existing silicon integrated photonic chip and a common single-mode fiber or a semiconductor laser mainly comprises two modes of grating coupling at a specific angle and horizontal edge end face coupling. The large alignment tolerance and wafer-level non-contact damage test capability are obvious advantages of the grating coupling method, but the disadvantages of strong polarization correlation and narrow bandwidth caused by the high refractive index difference between silicon and silicon dioxide are also outstanding, and the corresponding packaging process cost is high. In comparison, the horizontal edge end-face coupling mode has the advantages of high coupling efficiency, large coupling bandwidth and small polarization correlation, and meanwhile, the packaging process is high in maturity and low in cost. However, its application to the currently mainstream silicon integrated photonic chip manufactured based on SOI platform still faces the following challenges for a long time:
1. the coupling efficiency with standard single mode fibers is difficult to further improve. As the typical value of the cross-sectional dimension of the single-mode silicon waveguide on the silicon integrated photonic chip is (the width is 450nm multiplied by the height is 220 nm), the difference of the refractive index of the single-mode silicon waveguide and the refractive index of the silicon integrated photonic chip is 2.0. The diameter of a fiber core of the standard single-mode optical fiber is about-9 mu m, and the refractive index difference between a core layer and a cladding layer is only-0.005. Therefore, the size difference of the mode spots of the two is huge, and low-loss direct coupling cannot be realized. One of the main solutions at present is to indirectly use the small mode field characteristic (mode field diameter 3-7 μm) of high numerical aperture fibers to achieve low loss horizontal edge-facet coupling with on-chip single-mode silicon waveguides. And the high numerical aperture fiber is then subjected to low-loss fusion with the standard single-mode fiber. Although the scheme can improve the coupling efficiency of the photonic chip, the cost and the difficulty of packaging are obviously improved.
2. The thickness of the silicon dioxide buffer layer of the SOI wafer provided by the current mainstream wafer factory is 2-3 μm, so that when the silicon integrated photonic chip is coupled with the horizontal edge end face of the optical fiber, part of light inevitably leaks to the silicon substrate. Meanwhile, the silicon device layer is generally 220nm thick, so that the improvement of the mode field diameter of the input/output port at the edge of the chip, which can be realized by the horizontal edge end face coupler, in the direction vertical to the chip is limited, and further improvement of the coupling efficiency of the chip is limited. One of the existing solutions is to "undercut" a portion of the silicon substrate with an additional process, or to use a special end-face structure (such as a sub-wavelength grating), but this increases the complexity of the process and the manufacturing cost; in addition, the coupling efficiency can be improved to a certain extent by changing the material of the upper cladding layer of the waveguide. But some materials (e.g., optical polymers) are not compatible with standard CMOS processes.
3. The existing solution always inevitably compromises and balances the key performance indexes such as coupling efficiency, coupling bandwidth, polarization correlation and the like, and the complexity and cost of the manufacturing process. For the TE polarization in a single-mode silicon waveguide, high coupling efficiency is obtained as part of the structural scheme, but the coupling efficiency is low for the TM polarization, and the advantage of non-polarization dependence of the horizontal edge end-face coupler is sacrificed. In addition, the existing structure often has insufficient adjustable parameters, different applications (different optical fibers, inter-chip/on-chip interconnection, etc.) need to be designed and manufactured again, good mode field matching or interconnection effect cannot be obtained only by adjusting the parameters, and the applicability is poor.
In a word, the realization of the horizontal edge end face coupler of the silicon integrated photonic chip, which has the obvious advantages of high efficiency, large bandwidth, non-polarization correlation, large alignment tolerance, flexible selection of device structure parameters, easy processing and the like, in an optical communication waveband is important and meaningful work, and is beneficial to promoting the packaging of the silicon integrated optical chip and further the application research in the aspects of optical communication and optical interconnection.
Disclosure of Invention
In view of the above, in order to fill up the blank in the prior art, the present invention provides a broadband high-efficiency horizontal end-face coupler for optical communication bands and a manufacturing method thereof, wherein the device includes, from bottom to top: the silicon nanowire waveguide comprises a silicon substrate layer, a silicon dioxide spacing layer with a certain thickness, a fully-etched inverted cone-shaped silicon nanowire waveguide and a silicon dioxide upper coating layer, wherein the silicon dioxide spacing layer and the silicon dioxide upper coating layer are made of the same material and cover the silicon nanowire waveguide together. Wherein, three layers of silicon nitride waveguide arrays with the same quantity, size and structure are arranged in the silicon dioxide coating layer at a certain distance above the fully-etched inverted cone type silicon nanowire waveguide. The constituent materials and the preparation process are all completely compatible with the standard CMOS process. The three-layer silicon nitride waveguide array structure in the structure can be formed by etching the silicon dioxide coating layer and the three-layer silicon nitride film at one time, and does not need to pattern the three-layer silicon nitride film respectively, so that the process complexity can be effectively reduced. The invention can realize high efficiency and large bandwidth of the common single-mode fiber and the silicon integrated photonic chip in the optical communication band, has effective coupling related to non-polarization, has the obvious advantages of larger alignment tolerance, flexible selection of device structure parameters, easy processing and the like, and is beneficial to promoting the packaging of the silicon integrated optical chip and further the application research in the aspects of optical communication and optical interconnection.
The invention specifically adopts the following technical scheme:
an optical communications band wide bandwidth high efficiency horizontal end-face coupler, comprising: the silicon substrate layer, the silicon dioxide coating layer and the fully-etched inverted cone-shaped silicon nanowire waveguide are arranged on the silicon substrate layer; and three silicon nitride waveguide arrays with the same quantity, size and structure are arranged in the silicon dioxide coating layer above the fully-etched inverted cone silicon nanowire waveguide.
Further, the number, the size and the structure of the silicon nitride waveguides of each layer of the three-layer silicon nitride waveguide array are the same; the number, size or spacing of the silicon nitride waveguides in each layer is determined by the diameter of the spot to be coupled.
Furthermore, all the silicon nitride waveguides in the three silicon nitride waveguide arrays are all etched strip waveguides without width gradual change structures.
Furthermore, the three silicon nitride waveguide arrays are positioned right above the fully-etched inverted cone-shaped silicon nanowire waveguide and are symmetrically arranged along the horizontal direction.
Furthermore, the thickness of the fully-etched inverted cone-shaped silicon nanowire waveguide is selected to be compatible with a standard CMOS (complementary metal oxide semiconductor) process, and the width of the fully-etched inverted cone-shaped silicon nanowire waveguide gradually increases from the edge end face of the chip along the light transmission direction and is used for being connected with the on-chip waveguide in a low-loss mode.
Further, the materials required for the preparation include only silicon, silicon dioxide and silicon nitride. All three are fully compatible with standard CMOS processes and do not require the inclusion of other specialized materials (e.g., optical polymers, etc.).
Furthermore, the three-layer silicon nitride waveguide array structure is prepared by adopting a 193nm deep ultraviolet CMOS process without a special process (such as electron beam exposure), is formed by etching the silicon dioxide coating layer and the three-layer silicon nitride film at one time, does not need to pattern the three-layer silicon nitride film respectively, and effectively reduces the process complexity.
Further, a method for preparing a high-efficiency horizontal end-face coupler with wide bandwidth in optical communication waveband is provided, which is characterized in that: after a silicon device layer of a standard SOI wafer is subjected to full etching to form an inverted cone-shaped silicon nanowire waveguide, a silicon dioxide film is grown to serve as a spacing layer by utilizing a PECVD (plasma enhanced chemical vapor deposition) process in a subsequent process and combining a CMP (chemical mechanical polishing) process; then, alternately growing silicon nitride films and silicon dioxide films by utilizing a PECVD process; then, growing a layer of aluminum by utilizing a magnetron sputtering process; patterning the aluminum by utilizing a photoetching process and a dry etching process; then, carrying out one-time etching on the silicon dioxide layer and the three layers of silicon nitride films by using a dry etching process, and forming a silicon nitride waveguide array with three layers of completely same quantity, size and structure by controlling etching time until reaching the lower surface of the bottom layer of the silicon nitride film; and finally, finishing the manufacture of the silicon dioxide coating layer by utilizing a PECVD process or a PSG high-temperature planarization process, thereby finishing the preparation of the whole device.
Further, the number, the size and the structure of the silicon nitride waveguides of each layer of the three-layer silicon nitride waveguide array are the same; the number or the interval of the silicon nitride waveguides of each layer is determined according to the diameter of a light spot to be coupled; all the silicon nitride waveguides in the three silicon nitride waveguide arrays are all full-etching strip waveguides and do not have a width gradually-changing structure.
Furthermore, the three silicon nitride waveguide arrays are positioned right above the fully-etched inverted cone-shaped silicon nanowire waveguide and are symmetrically arranged along the horizontal direction.
Compared with the prior art, the beneficial effects of the invention and the preferred scheme thereof comprise:
1. the direct high-efficiency coupling of the silicon integrated photonic chip and the standard single-mode fiber can be realized in an optical communication waveband, a scheme of transition by using a high-numerical-aperture fiber is avoided, and the packaging cost and difficulty are obviously reduced.
2. Under the condition that the overall structure of the device is not changed, several key performance indexes such as high coupling efficiency, large bandwidth, independence of polarization and the like can be simultaneously met through reasonable parameter setting.
3. By utilizing the technical route of the invention, a good solution can be provided for the optical interconnection between chips (such as a semiconductor laser chip and a silicon integrated photonic chip) and on chips (such as three-dimensional optical interconnection).
4. The materials involved, including only silicon, silicon dioxide and silicon nitride, are fully compatible with standard CMOS processes and do not require the inclusion of other specialty materials (e.g., optical polymers, etc.). The preparation process is completely compatible with the mainstream 193nm deep ultraviolet CMOS process, and a special process (such as electron beam exposure) is not required.
5. The three-layer silicon nitride waveguide array structure can be formed by etching silicon dioxide and three-layer silicon nitride films at one time, and does not need to pattern the three-layer silicon nitride films respectively, so that the process complexity can be effectively reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
the accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a three-view diagram of a silicon integrated photonic chip horizontal edge end-face coupler based on silicon nitride waveguide array assistance according to an embodiment of the present invention: (a) is a cross-sectional view, (b) is a top view, and (c) is a side view;
FIG. 2 is a schematic diagram of a key preparation process of the embodiment of the invention: (a) etching silicon waveguide, (b) alternately growing silicon oxide and silicon nitride layers, (c) etching the silicon oxide and silicon nitride layers at one time, and (d) preparing a silicon dioxide upper coating layer.
In the figure: 1 is a silicon substrate, 2 is a silicon nanowire waveguide, 3 is a silicon nitride waveguide array, and 4 is a silicon dioxide coating layer.
Detailed Description
In order to make the features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail as follows:
the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components generally described and illustrated in the figures herein may be designed in various combinations and configurations. Thus, the following detailed description of selected embodiments of the invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the invention without making any creative effort, fall within the protection scope of the invention.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The silicon nitride waveguide array-based assisted silicon integrated photonic chip horizontal edge end-face coupler provided by the embodiment has a three-dimensional view as shown in fig. 1, and the structure thereof is from bottom to top, and includes: the silicon nanowire waveguide comprises a silicon substrate 1 layer, a fully-etched inverted cone-shaped silicon nanowire waveguide 2 and a silicon dioxide coating layer 4 coated outside the silicon nanowire waveguide. Wherein, three layers of silicon nitride waveguide arrays 3 with the same quantity, size and structure are arranged in the silicon dioxide coating layer at a certain distance above the fully etched inverted cone type silicon nanowire waveguide.
In this embodiment, the thickness of the silicon dioxide spacer layer is set to 3 μm. On the silicon device layer, the thickness of the fully-etched inverted cone type silicon nanowire waveguide is selected to be 150nm or 220nm compatible with a standard CMOS (complementary metal oxide semiconductor) process, the width of the waveguide gradually increases from the edge end face of the chip along the light transmission direction, and the waveguide is connected with the on-chip waveguide in a low-loss mode. Its initial width can be set to the minimum value (e.g. 150nm or less) that can be achieved by mainstream 193nm deep ultraviolet CMOS processes, and its actual shape approaches "reverse taper" through a graded structure with a length set to 1000 μm, increasing to 400 nm. And then, realizing low-loss connection with a single-mode silicon waveguide with the width of 450nm on the same layer through a small-section transition structure.
Silicon dioxide upper cladding layer and wherein three-layer silicon nitride waveguide array, from bottom to top, set gradually as: g from the upper surface of the silicon device layer1Within a distance, is provided as a silicon dioxide layer, g1=1.0 μm; arranging a silicon nitride waveguide array layer with the thickness of t on the silicon dioxide layer, wherein t =200nm, the width of each silicon nitride waveguide in the silicon nitride waveguide array layer is set as w, w =200nm, and silicon dioxide materials are also filled between adjacent silicon nitride waveguides, wherein the distance between the adjacent silicon nitride waveguides is s, and s =550 nm; thereafter, the sequence was repeated to set the thickness g2Silicon dioxide layer of g2A silicon nitride waveguide array layer with a thickness of t of =2.5 μm, a thickness of g3Silicon dioxide layer of g3A silicon nitride waveguide array layer of =2.7 μm and thickness t; finally, the thickness is set to g4Silicon dioxide layer of g4=8 μm. Thereby realizing the structure described in the present embodiment. The structural parameters can be adjusted according to the diameter of the light spot to be coupled or the function to be realized. The involved three-layer silicon nitride waveguide array is positioned right above the fully-etched inverted cone-shaped silicon nanowire waveguide and symmetrically arranged along the horizontal direction.
The preparation process of the embodiment adopts the mainstream 193nm deep ultraviolet CMOS process, and does not need special processes (such as electron beam exposure)Photo, silicon substrate undercut). In order to realize the silicon nitride waveguide array-based assisted silicon integrated photonic chip horizontal edge end-face coupler of the embodiment, the embodiment provides a corresponding key manufacturing method. As shown in fig. 2, after the silicon device layer of the standard SOI wafer is fully etched to form the fully etched inverted tapered silicon nanowire waveguide, a PECVD process in a subsequent process may be used in combination with a CMP process to grow and realize a thickness of 150/220nm + g1The silicon dioxide film is used as a spacing layer; then, only PECVD process is needed and CMP process is not needed, and the accurate alternative growth thickness is t and g respectively2、t、g3T, silicon dioxide and silicon nitride films; then, growing a layer of aluminum by utilizing a magnetron sputtering process; then, patterning the aluminum by utilizing a photoetching process and a dry etching process; and then, carrying out one-time etching on the silicon dioxide coating layer and the three layers of silicon nitride films by using a dry etching process, and stopping until the lower surface of the bottom layer of silicon nitride film is reached by controlling the etching time. Partial over-etching does not affect the performance of the device, so that the device has larger process tolerance; and then, finishing the manufacture of the silicon dioxide coating layer by utilizing a PECVD process or a PSG high-temperature planarization process, thereby finishing the preparation of the whole device. Particularly, compared with the existing disclosed structure, the manufacturing method does not need to respectively pattern three layers of silicon nitride, and the overall process complexity is effectively reduced.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.
The present invention is not limited to the above preferred embodiments, and any other various types of optical communication band broadband high efficiency horizontal end-face couplers and their manufacturing methods can be obtained according to the teaching of the present invention.
Claims (10)
1. An optical communications band wide bandwidth high efficiency horizontal end-face coupler, comprising: the silicon substrate layer, the silicon dioxide coating layer and the fully-etched inverted cone-shaped silicon nanowire waveguide are arranged on the silicon substrate layer; and three silicon nitride waveguide arrays with the same quantity, size and structure are arranged in the silicon dioxide coating layer above the fully-etched inverted cone silicon nanowire waveguide.
2. The optical communications band wide bandwidth high efficiency horizontal end-face coupler of claim 1, wherein: the number, the size and the structure of the silicon nitride waveguides of each layer of the three silicon nitride waveguide arrays are the same; the number or spacing of the silicon nitride waveguides in each layer is determined according to the diameter of the light spot to be coupled.
3. The optical communications band wide bandwidth high efficiency horizontal end-face coupler of claim 1, wherein: all the silicon nitride waveguides in the three silicon nitride waveguide arrays are all full-etching strip waveguides and do not have a width gradually-changing structure.
4. The optical communications band wide bandwidth high efficiency horizontal end-face coupler of claim 1, wherein: and the three silicon nitride waveguide arrays are positioned right above the fully-etched inverted cone-shaped silicon nanowire waveguide and are symmetrically arranged along the horizontal direction.
5. The optical communications band wide bandwidth high efficiency horizontal end-face coupler of claim 1, wherein: the thickness of the fully-etched inverted cone-shaped silicon nanowire waveguide is selected to be compatible with a standard CMOS (complementary metal oxide semiconductor) process, the width of the fully-etched inverted cone-shaped silicon nanowire waveguide gradually increases from the edge end face of the chip along the light transmission direction, and the fully-etched inverted cone-shaped silicon nanowire waveguide is used for being connected with the on-chip waveguide in a low-loss mode.
6. The optical communications band wide bandwidth high efficiency horizontal end-face coupler of claim 1, wherein: the materials required for the preparation include only silicon, silicon dioxide and silicon nitride.
7. The optical communications band wide bandwidth high efficiency horizontal end-face coupler of claim 1, wherein: the three-layer silicon nitride waveguide array structure is prepared by adopting 193nm deep ultraviolet CMOS (complementary metal oxide semiconductor) process and is formed by etching a silicon dioxide coating layer and three silicon nitride films at one time.
8. A preparation method of a high-efficiency horizontal end face coupler with wide bandwidth of an optical communication waveband is characterized by comprising the following steps: after a silicon device layer of a standard SOI wafer is subjected to full etching to form an inverted cone-shaped silicon nanowire waveguide, a silicon dioxide film is grown to serve as a spacing layer by utilizing a PECVD (plasma enhanced chemical vapor deposition) process in a subsequent process and combining a CMP (chemical mechanical polishing) process; alternately growing silicon nitride and silicon dioxide films by utilizing a PECVD process; then, growing a layer of aluminum by utilizing a magnetron sputtering process; patterning the aluminum by utilizing a photoetching process and a dry etching process; then, etching the silicon dioxide and the three layers of silicon nitride films at one time by using a dry etching process, and forming a silicon nitride waveguide array with three layers of completely same quantity, size and structure by controlling etching time until reaching the lower surface of the bottom layer of the silicon nitride film; and finally, finishing the manufacture of the silicon dioxide coating layer by utilizing a PECVD process or a PSG high-temperature planarization process, thereby finishing the preparation of the whole device.
9. The method of making a broadband high efficiency horizontal end-face coupler for optical communications bands according to claim 8, wherein: the number, the size and the structure of the silicon nitride waveguides of each layer of the three silicon nitride waveguide arrays are the same; the number or the interval of the silicon nitride waveguides of each layer is determined according to the diameter of a light spot to be coupled; all the silicon nitride waveguides in the three silicon nitride waveguide arrays are all full-etching strip waveguides and do not have a width gradually-changing structure.
10. The method of making a broadband high efficiency horizontal end-face coupler for optical communications bands according to claim 8, wherein: and the three silicon nitride waveguide arrays are positioned right above the fully-etched inverted cone-shaped silicon nanowire waveguide and are symmetrically arranged along the horizontal direction.
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