CN114253483B - Command-based write cache management method and device, computer equipment and storage medium - Google Patents
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- 238000004590 computer program Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 13
- 239000007787 solid Substances 0.000 claims description 8
- 238000000605 extraction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a write cache management method, a device, a computer device and a storage medium based on commands, wherein the method comprises the following steps: acquiring a write cache management request based on a command; according to the command-based write cache management request, forming a write cache command chain table from the write cache command according to a chain table form; when the total effective logic unit number or the total cache command number in the write cache exceeds a threshold value, triggering the cached command to write into the NAND; if the cached commands form a sequence flow, rearranging the logic address intervals corresponding to the sequence flow according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND. The command level write cache management mode provided by the invention can effectively reduce the requirement on RAM resources and meet the requirement of the DRAM-less SSD.
Description
Technical Field
The present invention relates to the field of storage systems, and in particular, to a command-based write cache management method, device, computer apparatus, and storage medium.
Background
With the development of Solid State Disk technology, SSD (Solid State Disk) has been widely used in various occasions, and the PC market has gradually replaced the conventional HDD (Hard Disk Drive), so as to provide better experience for users in terms of reliability and performance.
At present, one of functions of SSD write cache is to collect enough sequential write data, and write the data into NAND in a rearranged manner according to optimal read concurrency requirements so as to ensure optimal read performance. However, the existing write cache management is generally managed according to the size of the mapping unit (typically 4 KB), and in order to cache enough data, a large number of write cache management units are required, and the RAM space requirement is high.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, an apparatus, a computer device, and a storage medium for managing write buffers based on commands.
A method of command-based write cache management, the method comprising:
acquiring a write cache management request based on a command;
according to the command-based write cache management request, forming a write cache command chain table from the write cache command according to a chain table form;
when the total effective logic unit number or the total cache command number in the write cache exceeds a threshold value, triggering the cached command to write into the NAND;
if the cached commands form a sequence flow, rearranging the logic address intervals corresponding to the sequence flow according to the optimal read concurrency requirement before writing;
otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND.
In one embodiment, the method further comprises:
in command-based write cache management, a management unit of write cache is an indefinite-length command, and the indefinite-length command is used for managing an effective mapping unit bitmap;
when the write command is rewritten, the corresponding mapping unit bitmap in the rewritten command is cleared.
In one embodiment, the method further comprises:
and (3) completing the read-write command hit check by the ASIC logic in the solid state disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
In one embodiment, the step of performing the read-write hit processing according to the read-write hit result of the ASIC includes:
if hit is detected, traversing a command linked list of the command cache, and clearing bits corresponding to the effective logical address bitmap in the hit command.
A command-based write cache management apparatus, the apparatus comprising:
the acquisition module is used for acquiring a write cache management request based on a command;
the composition module is used for composing the write cache command into a write cache command linked list according to the command-based write cache management request in a linked list form;
the trigger module is used for triggering the cached command to be written into the NAND when the total number of the effective logic units or the total number of the cached commands in the write cache exceeds a threshold value;
the arrangement module is used for rearranging the logic address interval corresponding to the sequence flow according to the optimal read concurrency requirement before writing if the cached commands form the sequence flow;
and the extraction and writing module is used for traversing the command linked list if not, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
In one embodiment, the apparatus further comprises a unit management module for:
in command-based write cache management, a management unit of write cache is an indefinite-length command, and the indefinite-length command is used for managing an effective mapping unit bitmap;
when the write command is rewritten, the corresponding mapping unit bitmap in the rewritten command is cleared.
In one embodiment, the apparatus further comprises a hit-checking module for:
and (3) completing the read-write command hit check by the ASIC logic in the solid state disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
In one embodiment, the hit checking module is further configured to:
if hit is detected, traversing a command linked list of the command cache, and clearing bits corresponding to the effective logical address bitmap in the hit command.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the methods described above when the computer program is executed.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
The command-based write cache management method, the device, the computer equipment and the storage medium are used for acquiring a command-based write cache management request; according to the command-based write cache management request, forming a write cache command chain table from the write cache command according to a chain table form; when the total effective logic unit number or the total cache command number in the write cache exceeds a threshold value, triggering the cached command to write into the NAND; if the cached commands form a sequence flow, rearranging the logic address intervals corresponding to the sequence flow according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND. The command level write cache management mode provided by the invention can effectively reduce the requirement on RAM resources and meet the requirement of the DRAM-less SSD.
Drawings
FIG. 1 is a schematic diagram of write cache management based on a mapping unit;
FIG. 2 is a schematic diagram of command-based write cache management;
FIG. 3 is a flow diagram of a method of command-based write cache management in one embodiment;
FIG. 4 is a flow chart of a command-based write cache management method according to another embodiment;
FIG. 5 is a flow chart of a method of command-based write cache management in yet another embodiment;
FIG. 6 is a block diagram of a command-based write cache management apparatus in one embodiment;
FIG. 7 is a block diagram of another embodiment of a command-based write cache management apparatus;
FIG. 8 is a block diagram of a command-based write cache management apparatus in yet another embodiment;
fig. 9 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
At present, one of functions of SSD write cache is to collect enough sequential write data, and write the data into NAND in a rearranged manner according to optimal read concurrency requirements so as to ensure optimal read performance. However, the existing write cache management is generally managed according to the size of the mapping unit (typically 4 KB), and in order to cache enough data, a large number of write cache management units are required, and the RAM space requirement is high.
Based on the above, the invention provides a command-based write cache management method, which aims to reduce the demand on RAM resources to meet the requirement of DRAM-less SSD.
In one embodiment, as shown in FIG. 3, a command-based write cache management method is provided, the method comprising:
step 302, obtaining a write cache management request based on a command;
step 304, according to the command-based write cache management request, forming a write cache command list from the write cache command according to the form of the list;
step 306, when the total number of valid logic units or the total number of cache commands in the write cache exceeds a threshold, triggering the cached commands to write into the NAND;
step 308, if the buffered commands form a sequential stream, rearranging the logical address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing;
step 310, otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND.
In this embodiment, a command-level write cache management method is provided, which reduces the RAM resource requirement to meet the DRAM-less SSD requirement, and the specific implementation steps are as follows:
the mapping unit based cache management is described with reference to fig. 1, and fig. 2 is the command based write cache management proposed in this embodiment. Firstly, acquiring a write cache management request based on a command; and according to the command-based write cache management request, forming a write cache command chain table from the write cache commands according to the form of the chain table. In particular, the write commands are organized in a linked list, requiring less additional management information.
Then, when the total number of valid logical units in the write cache exceeds a threshold or the total number of commands in the cache exceeds a threshold, the command in the cache is triggered to write to the NAND. If the cached commands form a sequence flow, rearranging the logic address intervals corresponding to the sequence flow according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND.
In this embodiment, by acquiring a command-based write cache management request; according to the command-based write cache management request, forming a write cache command chain table from the write cache command according to a chain table form; when the total effective logic unit number or the total cache command number in the write cache exceeds a threshold value, triggering the cached command to write into the NAND; if the cached commands form a sequence flow, rearranging the logic address intervals corresponding to the sequence flow according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND. The command level write cache management mode provided by the scheme can effectively reduce the requirement on RAM resources and meets the requirement of the DRAM-less SSD.
In one embodiment, as shown in fig. 4, there is provided a command-based write cache management method, which further includes:
step 402, in command-based write cache management, a management unit of write cache is an indefinite-length command, and the indefinite-length command is used for managing an effective mapping unit bitmap;
step 404, when the write command overwrite occurs, the corresponding mapping unit bitmap in the overwrite command is cleared.
In one embodiment, as shown in fig. 5, there is provided a command-based write cache management method, which further includes:
step 502, completing the checking of the read-write command hit by the ASIC logic in the solid state disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC;
step 504, if hit is detected, traversing the command linked list of the command cache, and clearing the bits corresponding to the effective logical address bitmap in the hit command.
In this embodiment, a command-based write cache management method is provided, in which read-write hit checking is instead performed by custom ASIC logic in the SSD controller to speed up read-write command processing.
Specifically, the management structure described with reference to fig. 1, which is commonly used for read-write hit checking: if the software maintains the query structure and performs hit checking, a larger read/write command processing delay must be increased. In this embodiment, as shown in fig. 2, the command-based write cache management scheme changes the hit checking process to be processed by the custom ASIC logic of the SSD controller, and the software only needs to perform corresponding processing according to the checking result provided by the controller. If hit is detected, traversing the command linked list of the command cache, and clearing the bits corresponding to the effective logical address bitmap in the hit command.
In this embodiment, by checking in the read/write command of the command level completed by the ASIC logic customized in the SSD controller, the software performs the read/write hit processing according to the read/write hit result of the ASIC, accelerating the processing of the read/write command.
It should be understood that, although the steps in the flowcharts of fig. 1-5 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-5 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or steps.
In one embodiment, as shown in FIG. 6, a command-based write cache management apparatus 600 is provided, the apparatus comprising:
an obtaining module 601, configured to obtain a write cache management request based on a command;
a composition module 602, configured to compose a write cache command list according to the command-based write cache management request, where the write cache command list is formed by a write cache command according to a list form;
the trigger module 603 is configured to trigger the buffered command to write into the NAND when the total number of valid logic units or the total number of buffered commands in the write buffer exceeds a threshold;
an arrangement module 604, configured to rearrange, if the buffered commands form a sequential stream, logical address intervals corresponding to the sequential stream according to an optimal read concurrency requirement before writing;
and the extraction and writing module 605 is used for traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
In one embodiment, as shown in FIG. 7, a command-based write cache management apparatus 600 is provided, the apparatus further comprising a unit management module 606 for:
in command-based write cache management, a management unit of write cache is an indefinite-length command, and the indefinite-length command is used for managing an effective mapping unit bitmap;
when the write command is rewritten, the corresponding mapping unit bitmap in the rewritten command is cleared.
In one embodiment, as shown in FIG. 8, a command-based write cache management apparatus 600 is provided, the apparatus further comprising a hit-checking module 607 for:
and (3) completing the read-write command hit check by the ASIC logic in the solid state disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
In one embodiment, the hit checking module 607 is further configured to:
if hit is detected, traversing a command linked list of the command cache, and clearing bits corresponding to the effective logical address bitmap in the hit command.
For specific limitations on the command-based write cache management apparatus, reference may be made to the above limitations on the command-based write cache management method, and no further description is given here.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 9. The computer device includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a command-based write cache management method.
It will be appreciated by those skilled in the art that the structure shown in fig. 9 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the computer device to which the present application applies, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method embodiments above when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the above method embodiments.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method for command-based write cache management, the method comprising:
acquiring a write cache management request based on a command;
according to the command-based write cache management request, forming a write cache command chain table from the write cache command according to a chain table form;
when the total effective logic unit number or the total cache command number in the write cache exceeds a threshold value, triggering the cached command to write into the NAND;
if the cached commands form a sequence flow, rearranging the logic address intervals corresponding to the sequence flow according to the optimal read concurrency requirement before writing;
otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND.
2. The command-based write cache management method of claim 1, further comprising:
in command-based write cache management, a management unit of write cache is an indefinite-length command, and the indefinite-length command is used for managing an effective mapping unit bitmap;
when the write command is rewritten, the corresponding mapping unit bitmap in the rewritten command is cleared.
3. The command-based write cache management method of claim 1, further comprising:
and (3) completing the read-write command hit check by the ASIC logic in the solid state disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
4. The command-based write cache management method as claimed in claim 3, wherein said step of performing read-write hit processing according to a read-write hit result of the ASIC comprises:
if hit is detected, traversing a command linked list of the command cache, and clearing bits corresponding to the effective logical address bitmap in the hit command.
5. A command-based write cache management apparatus, the apparatus comprising:
the acquisition module is used for acquiring a write cache management request based on a command;
the composition module is used for composing the write cache command into a write cache command linked list according to the command-based write cache management request in a linked list form;
the trigger module is used for triggering the cached command to be written into the NAND when the total number of the effective logic units or the total number of the cached commands in the write cache exceeds a threshold value;
the arrangement module is used for rearranging the logic address interval corresponding to the sequence flow according to the optimal read concurrency requirement before writing if the cached commands form the sequence flow;
and the extraction and writing module is used for traversing the command linked list if not, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
6. The command-based write cache management apparatus of claim 5, further comprising a unit management module to:
in command-based write cache management, a management unit of write cache is an indefinite-length command, and the indefinite-length command is used for managing an effective mapping unit bitmap;
when the write command is rewritten, the corresponding mapping unit bitmap in the rewritten command is cleared.
7. The command-based write cache management apparatus of claim 5, further comprising a hit-checking module to:
and (3) completing the read-write command hit check by the ASIC logic in the solid state disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
8. The command-based write cache management apparatus of claim 7, wherein the hit checking module is further to:
if hit is detected, traversing a command linked list of the command cache, and clearing bits corresponding to the effective logical address bitmap in the hit command.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 4 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
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Effective date of registration: 20231201 Address after: Room 4-B703, No. 328 Xinghu Street, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Pilot Free Trade Zone, Suzhou City, Jiangsu Province, 215000 Patentee after: Suzhou Yilian Information System Co.,Ltd. Address before: D24 / f-02, dongjiaotou workshop, Shekou Houhai Avenue, Shekou street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN UNIONMEMORY INFORMATION SYSTEM Co.,Ltd. |