CN114245411A - Method and device for testing message delay time, terminal equipment and storage medium - Google Patents
Method and device for testing message delay time, terminal equipment and storage medium Download PDFInfo
- Publication number
- CN114245411A CN114245411A CN202111316080.8A CN202111316080A CN114245411A CN 114245411 A CN114245411 A CN 114245411A CN 202111316080 A CN202111316080 A CN 202111316080A CN 114245411 A CN114245411 A CN 114245411A
- Authority
- CN
- China
- Prior art keywords
- count
- message
- delay time
- counter
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/08—Testing, supervising or monitoring using real traffic
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a method and a device for testing message delay time, terminal equipment and a storage medium, wherein the method comprises the following steps: acquiring a message, writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count; sending the message, and writing the count generated by the counter into the filling field again when the message is sent, and recording the count as a second count; and determining the message delay time according to the first count and the second count. The method and the device can directly test the delay time of the message without depending on other equipment, and improve the accuracy and convenience of the delay test.
Description
Technical Field
The invention relates to the field of message delay testing, in particular to a method and a device for testing message delay time, terminal equipment and a storage medium.
Background
5G network networks are becoming more and more popular, and one important characteristic is low latency. The 5G technique is effective in reducing latency and increasing data transmission rates, and response times can be reduced from an average of 50 milliseconds (0.05s) for 4G to 1-2 milliseconds (0.001-0.002 s). And the UPF equipment processes and gathers user data from the base station and then sends the user data to the uplink equipment. In order to test the delay of message processing, special equipment is needed, which is inconvenient for accurately testing the delay time of the message on one hand, and increases the testing cost on the other hand.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method, an apparatus, a terminal device and a storage medium for testing message delay time, aiming at improving the accuracy of testing message delay and reducing the testing cost by providing a method for testing message delay time.
The technical scheme adopted by the invention for solving the technical problem is as follows:
in a first aspect, the present invention provides a method for testing message delay time, where the method includes:
acquiring a message, writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count;
sending the message, and writing the count generated by the counter into the filling field again when the message is sent, and recording the count as a second count;
and determining the message delay time according to the first count and the second count.
In an implementation manner, when the packet is obtained, marking a count generated by a preset counter on the padding field, and recording as a first count includes:
when the message is acquired, acquiring the address of the first 8 bytes of the filling field;
reading the count value of the counter;
and writing the read count value into the first 8 bytes of the padding field according to the address of the first 8 bytes of the padding field, and recording as a first count.
In one implementation, the sending the packet and writing the count generated by the counter into the padding field again when the sending of the packet is completed, and the recording as the second count includes:
after the message is sent, acquiring the address of the last 8 bytes of the filling field;
reading the count value of the counter again;
and writing the read count value into the last 8 bytes of the padding field according to the address of the last 8 bytes of the padding field, and recording the count value as a second count.
In an implementation manner, the determining a packet delay time according to the first count and the second count includes:
after the message is sent, recovering the memory occupied by a preset cache SKB, wherein the first count and the second count are recorded in the cache SKB;
and recording the difference value obtained by subtracting the first count from the second count as the message delay time.
In one implementation, the obtaining a packet and writing a count generated by a preset counter in a padding field of the packet, before the writing the count as a first count, includes:
setting a field length of the pad field to 16 bytes;
initializing the counter and setting the maximum counting times of the counter;
defining a counting statistical table and clearing the counting statistical table, wherein the content of each record item in the counting statistical table is the counting times of a counter for completing the transmission of the message from the acquisition.
In an implementation manner, the determining a packet delay time according to the first count and the second count further includes:
acquiring a preset index in the counting statistical table, and determining a statistical item in the counting statistical table according to the index;
and after the message delay time is determined according to the first count and the second count, enabling the index to point to the next statistical item.
In an implementation manner, the determining a packet delay time according to the first count and the second count further includes:
and when the statistical item exceeds a preset threshold value, the first statistical item in the counting statistical table is redirected.
In a second aspect, an embodiment of the present invention further provides a device for testing a message delay time, where the device includes:
the first counting determining module is used for acquiring a message, writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count;
a second count determining module, configured to send the packet, and write the count generated by the counter into the padding field again when the sending is completed, where the count is recorded as a second count;
and the message delay time determining module is used for determining the message delay time according to the first count and the second count.
In a third aspect, an embodiment of the present invention further provides a terminal device, where the terminal device includes: a processor, a storage medium communicatively coupled to the processor, the storage medium adapted to store a plurality of instructions; the processor is adapted to call instructions in the storage medium to execute a method for testing message delay time according to any one of the above schemes.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement a method for testing a message delay time according to any one of the above schemes.
The invention has the beneficial effects that: compared with the prior art, the invention provides a method for testing the message delay time, which comprises the steps of firstly obtaining a message, and obtaining the message firstly because the message needs to be tested for the delay time in the processing process in the embodiment, and then sending the message, wherein the message delay time can be calculated according to the first count and the second count by writing the first count generated by a counter in a filling field of the message when the message is obtained and writing the second count generated by the counter in the filling field of the message when the message is sent.
Drawings
Fig. 1 is a flowchart of a specific implementation of a method for testing message delay time according to an embodiment of the present invention.
Fig. 2 is a flowchart of determining a first count in a method for testing a message delay time according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an effective packet and a padding field in a packet in the method for testing packet delay time according to the embodiment of the present invention.
Fig. 4 is a flowchart for performing initialization in the method for testing message delay time according to the embodiment of the present invention.
Fig. 5 is a flowchart of writing a count value in a padding field when a packet is acquired in the method for testing packet delay time according to the embodiment of the present invention.
Fig. 6 is a flowchart of determining a second count in the method for testing packet delay time according to the embodiment of the present invention.
Fig. 7 is a flowchart of writing a count value in a padding field again after sending a message in the method for testing message delay time according to the embodiment of the present invention.
Fig. 8 is a schematic diagram of a message obtained after a count value is written in a padding field in the method for testing message delay time according to the embodiment of the present invention.
Fig. 9 is a flowchart illustrating that the cache SKB is recovered by the index in the method for testing the message delay time according to the embodiment of the present invention.
Fig. 10 is a schematic block diagram of a device for testing message delay time according to an embodiment of the present invention.
Fig. 11 is a schematic block diagram of an internal structure of a terminal device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, counting schemes and advantages of the present invention clearer and clearer, the present invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
5G network networks are becoming more and more popular, and one important characteristic is low latency. The 5G technique is effective in reducing latency and increasing data transmission rates, and response times can be reduced from an average of 50 milliseconds (0.05s) for 4G to 1-2 milliseconds (0.001-0.002 s). And the UPF equipment processes and gathers user data from the base station and then sends the user data to the uplink equipment.
In order to solve the problems of the prior art,
research shows that in order to test the delay of message processing, special equipment is usually used to test the message delay in the prior art, and the conventional test of the message delay through external equipment is not convenient to accurately test the delay time of the message on one hand, and the test cost is increased on the other hand.
In order to solve the problems of the prior art, this embodiment provides a method for testing a message delay time, where the method includes first obtaining a message, and because this embodiment needs to test a delay of the message in a processing process, the message needs to be obtained first, and then the message is sent, and the message delay time can be calculated according to a first count and a second count by writing the first count generated by a counter in a padding field of the message when the message is obtained and writing the second count generated by the counter in the padding field of the message when the message is sent.
Exemplary method
The method for testing the message delay time in this embodiment may be applied to a terminal device, such as a smart phone, a tablet computer, and a notebook computer, where the terminal device has a function of receiving and sending a message. In specific implementation, as shown in fig. 1, the method for testing message delay time in this embodiment includes the following steps:
and S100, acquiring a message, and writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count.
In this embodiment, the delay time of the message in the processing process is tested, and the count generated by the preset timer is obtained twice when the message is obtained and sent, and the difference between the two counts is obtained, so that the time difference between the message obtaining and the message sending is the message delay time.
In one implementation, as shown in fig. 2, the step S100 includes the following steps:
s101, when the message is acquired, acquiring the address of the first 8 bytes of the filling field;
s102, reading the count value of the counter;
s103, writing the read count value into the first 8 bytes of the padding field according to the address of the first 8 bytes of the padding field, and recording the count value as a first count.
In specific implementation, as shown in fig. 3, when the network port hardware receives a message, it allows a padding space with a certain length to be added at the front end of the message for storing user-defined data of a user, the padding field is followed by an effective message, and the content of the padding field is not included in the effective message and sent out, so that the padding field in the SKB can be read when the buffering SKB is sent and recovered. Specifically, when the packet is acquired, the address of the first 8 bytes of the padding field is acquired, the count value of the current timer is read, and the count value of the current timer is written into the first 8 bytes of the padding field and is recorded as a first count.
Preferably, the embodiment needs to initialize the socket driver before obtaining the packet, and when the linux kernel is started and the socket driver is loaded, the socket driver starts to initialize, as shown in fig. 4, first, the field length of the padding field is set to 16 bytes, then a preset counter is initialized, specifically, the counter in the embodiment is a 100M hardware counter, the counter is 64 bits, the maximum count number is 64 times of 2, finally, a count statistical table is defined, and a threshold of the count statistical table is set to 10 ten thousand times, where the content of each record item is the count number of the counter that the packet has undergone from obtaining to sending.
For example, as shown in fig. 5, after receiving a message, the gateway hardware triggers hardware interrupt, acquires an address of a padding field of the message as pRxTimeCount at the first time when the message is acquired, then reads a current count value count of a 100M hardware counter, writes a value of the count into the first 8 bytes of the padding field, records the value as a first count, that is, pRxTimeCount is the count, and then enters a normal processing flow.
And step S200, sending the message, and writing the count generated by the counter into the filling field again when the message is sent, wherein the count is recorded as a second count.
In this embodiment, after the normal processing flow is performed on the message, the message can be sent, and after the message is sent, the count generated by the counter can be obtained again, and the obtained count is written into the padding field of the message and recorded as the second count, so that the difference between the first count and the second count can be obtained, and the delay time when the message is processed can be obtained.
In one implementation, as shown in fig. 6, the step S200 includes the following steps:
s201, after the message is sent, acquiring the address of the last 8 bytes of the filling field;
s202, reading the count value of the counter again;
and S203, writing the read count value into the last 8 bytes of the padding field according to the address of the last 8 bytes of the padding field, and recording the count value as a second count.
In specific implementation, in this embodiment, after the internet access hardware sends a message, the hardware is triggered to interrupt, then the address of the last 8 bytes of the padding field is obtained, the count value of the counter is read again, and the read count value of the counter is written into the last 8 bytes of the padding field according to the address of the last 8 bytes of the padding field and is recorded as a second count. For example, as shown in fig. 7, after the message is sent, the address of the last 8 bytes of the padding field of the current message is pTxTimeCount, then the current count value count of the 100M hardware counter is read again, and the value of the count is written into the last 8 bytes of the padding field and is recorded as the second count, that is, pTxTimeCount is counted. Preferably, the count values of the counters at the time of receiving and sending, which are recorded in the padding field, are recorded in the cache SKB, so that after the first count and the second count are determined, the recovery thread of the sending cache SKB needs to be awakened, the first count and the second count are conveniently acquired and processed, and the message delay time is conveniently obtained.
And step S300, determining message delay time according to the first count and the second count.
Specifically, after the first count and the second count are determined, since both the first count and the second count are recorded in the cache SKB, after the message is sent, the sending cache SKB recovery thread needs to be waken up, the first count and the second count are read, and then the first count is subtracted from the second count, that is, the first 8-byte value is subtracted from the second 8-byte value in the padding field of the message, so as to obtain the message delay time. For example, as shown in fig. 8, since the timer in the present embodiment is a 100M hardware timer, the interval of one period is 10 ns, one count is 10 ns, and assuming that the first count at the time of message reception is 50000 and the second count at the time of message transmission is 550000, the message delay time is (550000-50000) 10 ns, 5000000 ns, 5000 μ s, and 5 ms.
Preferably, in the embodiment, in the thread of sending the cache SKB, the count number of times that the packet is obtained from the counter after the completion of sending is further recorded through a preset count statistics table, specifically, as shown in fig. 9, a current index of the count statistics table is obtained first, then a current statistical item of the count statistics table is obtained as account [ index ], after the delay time of the packet is obtained according to the first count and the second count, the index of the current count statistics table points to a next statistical item, and then the next cache SKB is continuously recovered. Preferably, when the number of the statistical items in the counting statistical table of this embodiment reaches 10 ten thousand, the average processing time of the message can be obtained by averaging 10 ten thousand statistical items; the maximum processing time of the message can be obtained by finding the maximum value of 10 ten thousand statistical items; the minimum processing time of the message can be obtained by finding the minimum value of 10 ten thousand statistical items; the median processing time of the message can be obtained by finding the median of 10 ten thousand statistical items.
To sum up, the present embodiment first obtains the message, since the present embodiment needs to test the delay of the message in the processing process, the message needs to be obtained first, when the message is acquired, the current value in the preset timer is written into the first 8 bytes in the padding field of the message to obtain a first count, then the message is sent, after the message is sent, the current value in the counter is written into the last 8 bytes of the padding field of the message, obtaining a second count, finally, by recycling the cache SKB, subtracting the value of the first 8 bytes from the last 8 bytes of the field, namely subtracting the first count from the second count, the method and the device can obtain the message delay time, can more accurately test the message delay time through the technical scheme of the invention, and simultaneously does not need to depend on other equipment, thereby improving the convenience of the delay test.
Exemplary devices
As shown in fig. 10, the present embodiment further provides a device for testing a message delay time, which includes a first count determining module 10, a second count determining module 20, and a message delay time determining module 30. Specifically, the first count determining module 10 is configured to obtain a packet, and write a count generated by a preset counter into a padding field of the packet, which is recorded as a first count. The second count determining module 20 is configured to send the packet, and write the count generated by the counter into the padding field again when the sending is completed, and record the count as a second count. The message delay time determining module 30 is configured to determine the message delay time according to the first count and the second count.
In one implementation, the first count determining module 10 includes:
a first address obtaining unit, configured to obtain an address of the first 8 bytes of the padding field when the packet is obtained;
a first reading unit configured to read a count value of the counter;
and the first writing unit is used for writing the read count value into the first 8 bytes of the padding field according to the address of the first 8 bytes of the padding field, and recording the read count value as a first count.
In one implementation, the second count determining module 20 includes:
a second address obtaining unit, configured to obtain, after the message is sent, an address of the last 8 bytes of the padding field;
a second reading unit configured to read the count value of the counter again;
and the second writing unit is used for writing the read count value into the last 8 bytes of the padding field according to the address of the last 8 bytes of the padding field, and recording the read count value as a second count.
In one implementation, the message delay time determining module 30 includes:
a recovery unit, configured to recover, after the message is sent, a memory occupied by a preset cache SKB, where the first count and the second count are recorded in the cache SKB;
and the calculating unit is used for recording the difference value obtained by subtracting the first count from the second count as the message delay time.
Based on the above embodiments, the present invention further provides a terminal device, and a schematic block diagram thereof may be as shown in fig. 11. The terminal equipment comprises a processor, a memory, a network interface, a display screen and a temperature sensor which are connected through a system bus. Wherein the processor of the terminal device is configured to provide computing and control capabilities. The memory of the terminal equipment comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the terminal device is used for connecting and communicating with an external terminal through a network. The computer program is executed by a processor to implement a method for testing message latency. The display screen of the terminal equipment can be a liquid crystal display screen or an electronic ink display screen, and the temperature sensor of the terminal equipment is arranged in the terminal equipment in advance and used for detecting the operating temperature of the internal equipment.
It will be understood by those skilled in the art that the block diagram of fig. 11 is only a block diagram of a portion of the structure associated with the solution of the present invention, and does not limit the terminal device to which the solution of the present invention is applied, and a specific terminal device may include more or less components than those shown in the figure, or may combine some components, or have a different arrangement of components.
In one embodiment, a terminal device is provided, where the terminal device includes a memory, a processor, and a message delay time test program stored in the memory and executable on the processor, and when the processor executes the message delay time test program, the following operation instructions are implemented:
acquiring a message, writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count;
sending the message, and writing the count generated by the counter into the filling field again when the message is sent, and recording the count as a second count;
and determining the message delay time according to the first count and the second count.
It will be understood by those of ordinary skill in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the above embodiments of the methods. Any reference to memory, storage, databases, or other media used in embodiments provided herein may include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
In summary, the present invention provides a method for testing a message delay time, the method includes obtaining a message first, and since this embodiment needs to test a delay of the message in a processing process, the message needs to be obtained first, and then the message is sent, and by writing a first count generated by a counter in a padding field of the message when the message is obtained, and writing a second count generated by the counter in the padding field of the message when the message is sent, the message delay time can be calculated according to the first count and the second count.
Finally, it should be noted that: the above examples are intended only to illustrate the counting scheme of the present invention and not to limit it; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the counting scheme described in the previous embodiments can be modified, or some of the counting features can be replaced equivalently; such modifications or substitutions do not depart from the spirit and scope of the counting scheme of the embodiments of the present invention.
Claims (10)
1. A method for testing message delay time is characterized in that the method comprises the following steps:
acquiring a message, writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count;
sending the message, and writing the count generated by the counter into the filling field again when the message is sent, and recording the count as a second count;
and determining the message delay time according to the first count and the second count.
2. The method according to claim 1, wherein the step of marking a count generated by a preset counter on the padding field when the packet is acquired, and the step of marking the count as the first count includes:
when the message is acquired, acquiring the address of the first 8 bytes of the filling field;
reading the count value of the counter;
and writing the read count value into the first 8 bytes of the padding field according to the address of the first 8 bytes of the padding field, and recording as a first count.
3. The method according to claim 2, wherein the sending the packet and writing the count generated by the counter again in the padding field when the packet is sent, and the writing the count as the second count includes:
after the message is sent, acquiring the address of the last 8 bytes of the filling field;
reading the count value of the counter again;
and writing the read count value into the last 8 bytes of the padding field according to the address of the last 8 bytes of the padding field, and recording the count value as a second count.
4. The method according to claim 2, wherein the determining the packet delay time according to the first count and the second count comprises:
after the message is sent, recovering the memory occupied by a preset cache SKB, wherein the first count and the second count are recorded in the cache SKB;
and recording the difference value obtained by subtracting the first count from the second count as the message delay time.
5. The method according to claim 1, wherein the obtaining the packet and writing the count generated by the preset counter into the padding field of the packet before the count is recorded as the first count comprises:
setting a field length of the pad field to 16 bytes;
initializing the counter and setting the maximum counting times of the counter;
defining a counting statistical table and clearing the counting statistical table, wherein the content of each record item in the counting statistical table is the counting times of a counter for completing the transmission of the message from the acquisition.
6. The method according to claim 5, wherein the determining the packet delay time according to the first count and the second count further comprises:
acquiring a preset index in the counting statistical table, and determining a statistical item in the counting statistical table according to the index;
and after the message delay time is determined according to the first count and the second count, enabling the index to point to the next statistical item.
7. The method of claim 6, wherein the determining the packet delay time according to the first count and the second count further comprises:
and when the statistical item exceeds a preset threshold value, the first statistical item in the counting statistical table is redirected.
8. A device for testing message delay time is characterized in that the device comprises:
the first counting determining module is used for acquiring a message, writing a count generated by a preset counter into a filling field of the message, and recording the count as a first count;
a second count determining module, configured to send the packet, and write the count generated by the counter into the padding field again when the sending is completed, where the count is recorded as a second count;
and the message delay time determining module is used for determining the message delay time according to the first count and the second count.
9. A terminal device, characterized in that the terminal device comprises: a processor, a storage medium communicatively coupled to the processor, the storage medium adapted to store a plurality of instructions; the processor is adapted to invoke instructions in the storage medium to perform a test method that implements a message latency according to any one of claims 1 to 7.
10. A computer-readable storage medium, storing one or more programs, the one or more programs being executable by one or more processors to implement a method for testing message latency as recited in any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111316080.8A CN114245411A (en) | 2021-11-08 | 2021-11-08 | Method and device for testing message delay time, terminal equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111316080.8A CN114245411A (en) | 2021-11-08 | 2021-11-08 | Method and device for testing message delay time, terminal equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114245411A true CN114245411A (en) | 2022-03-25 |
Family
ID=80748664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111316080.8A Pending CN114245411A (en) | 2021-11-08 | 2021-11-08 | Method and device for testing message delay time, terminal equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114245411A (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235184A1 (en) * | 2002-06-20 | 2003-12-25 | Dorenbosch Jheroen P. | Method and apparatus for speaker arbitration in a multi-participant communication session |
| WO2007095801A1 (en) * | 2006-02-24 | 2007-08-30 | Huawei Technologies Co., Ltd. | A method, apparatus, and system for measuring the network performance |
| CN103312542A (en) * | 2013-05-28 | 2013-09-18 | 盛科网络（苏州）有限公司 | Message processing method and message processing device |
| CN103607267A (en) * | 2013-07-23 | 2014-02-26 | 王健 | End-to-end transmission delay carrying measurement method of data network message |
| CN104202131A (en) * | 2014-08-21 | 2014-12-10 | 云南电力试验研究院（集团）有限公司电力研究院 | Method for improving transmission real-time of sample data in electric power distribution network system |
| CN104348568A (en) * | 2013-07-23 | 2015-02-11 | 中兴通讯股份有限公司 | Time synchronization processing method and device |
| CN104601497A (en) * | 2013-10-31 | 2015-05-06 | 华为技术有限公司 | 1588V2 message transmission method and device based on WAN (Wide Area Network) interface |
| WO2018076651A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Time synchronization method, device and computer storage medium |
| CN109699199A (en) * | 2017-08-23 | 2019-04-30 | 华为技术有限公司 | A kind of method and the network equipment of Message processing |
| WO2020001213A1 (en) * | 2018-06-28 | 2020-01-02 | 中兴通讯股份有限公司 | Message transmission method, switching apparatus, wireless communication device and storage medium |
| WO2021004005A1 (en) * | 2019-07-10 | 2021-01-14 | 烽火通信科技股份有限公司 | Timestamp jitter compensation method and system |
| CN112838903A (en) * | 2020-12-31 | 2021-05-25 | 广东大普通信技术有限公司 | Clock synchronization method, equipment and storage medium |
-
2021
- 2021-11-08 CN CN202111316080.8A patent/CN114245411A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235184A1 (en) * | 2002-06-20 | 2003-12-25 | Dorenbosch Jheroen P. | Method and apparatus for speaker arbitration in a multi-participant communication session |
| WO2007095801A1 (en) * | 2006-02-24 | 2007-08-30 | Huawei Technologies Co., Ltd. | A method, apparatus, and system for measuring the network performance |
| CN103312542A (en) * | 2013-05-28 | 2013-09-18 | 盛科网络（苏州）有限公司 | Message processing method and message processing device |
| CN103607267A (en) * | 2013-07-23 | 2014-02-26 | 王健 | End-to-end transmission delay carrying measurement method of data network message |
| CN104348568A (en) * | 2013-07-23 | 2015-02-11 | 中兴通讯股份有限公司 | Time synchronization processing method and device |
| CN104601497A (en) * | 2013-10-31 | 2015-05-06 | 华为技术有限公司 | 1588V2 message transmission method and device based on WAN (Wide Area Network) interface |
| CN104202131A (en) * | 2014-08-21 | 2014-12-10 | 云南电力试验研究院（集团）有限公司电力研究院 | Method for improving transmission real-time of sample data in electric power distribution network system |
| WO2018076651A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Time synchronization method, device and computer storage medium |
| CN109699199A (en) * | 2017-08-23 | 2019-04-30 | 华为技术有限公司 | A kind of method and the network equipment of Message processing |
| WO2020001213A1 (en) * | 2018-06-28 | 2020-01-02 | 中兴通讯股份有限公司 | Message transmission method, switching apparatus, wireless communication device and storage medium |
| WO2021004005A1 (en) * | 2019-07-10 | 2021-01-14 | 烽火通信科技股份有限公司 | Timestamp jitter compensation method and system |
| CN112838903A (en) * | 2020-12-31 | 2021-05-25 | 广东大普通信技术有限公司 | Clock synchronization method, equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| ALCATEL-LUCENT / KEITH DRAGE: "C1-085016 "Editiorial consistency and best practice"", 3GPP TSG_CN\\WG1_MM-CC-SM_EX-CN1, no. 1 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106910528B (en) | Optimization method and device for data inspection of solid state disk | |
| TWI662410B (en) | Data storage device and methods for processing data in the data storage device | |
| CN109582228B (en) | Hardware acceleration method and device for automatic read retry based on NAND flash memory controller | |
| CN111290973B (en) | Data writing method and device, computer equipment and storage medium | |
| CN103984506B (en) | The method and system that data of flash memory storage equipment is write | |
| CN111277836B (en) | Video extraction frame loss control method, system, terminal and storage medium | |
| WO2020073691A1 (en) | Flash memory self-test method, solid hard disk and storage device | |
| US20230053582A1 (en) | System and method for error reporting and handling | |
| CN110543281A (en) | Storage compression implementation method, device, equipment and storage medium | |
| US11960396B2 (en) | Method and computer program product for performing data writes into a flash memory | |
| CN109164978A (en) | Flash memory management method, flash memory device and computer readable storage medium | |
| CN115248791A (en) | Hardware equipment and method for realizing memory management based on address monitoring | |
| CN110209605B (en) | Register read-write method of PCIE bus network card and computing equipment | |
| EP3371702A1 (en) | Systems and methods for implementing error correcting code in a memory | |
| CN109246234B (en) | Image file downloading method and device, electronic equipment and storage medium | |
| CN111752482A (en) | Method and system for writing data in full-flash distributed storage system | |
| CN109656474B (en) | Data storage method and device, computer equipment and storage medium | |
| US20170103797A1 (en) | Calibration method and device for dynamic random access memory | |
| CN102722456B (en) | Flash memory device and data writing method thereof | |
| CN111897485A (en) | Data storage method and device, electronic equipment and storage medium | |
| US11966398B2 (en) | Video data storage method, apparatus, terminal device and storage medium | |
| CN114245411A (en) | Method and device for testing message delay time, terminal equipment and storage medium | |
| US20060161822A1 (en) | Method and apparatus for compressing error information, and computer product | |
| CN114721602B (en) | Nor Flash rolling storage method and device based on FreeRTOS | |
| CN106776393B (en) | uninterrupted serial port data receiving method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |