CN114237949A - Debugging information access method and electronic equipment thereof - Google Patents
Debugging information access method and electronic equipment thereof Download PDFInfo
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- CN114237949A CN114237949A CN202111366422.7A CN202111366422A CN114237949A CN 114237949 A CN114237949 A CN 114237949A CN 202111366422 A CN202111366422 A CN 202111366422A CN 114237949 A CN114237949 A CN 114237949A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0787—Storage of error reports, e.g. persistent data storage, storage using memory protection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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Abstract
The application discloses a debugging information access method and electronic equipment thereof. The debugging information access method comprises the following steps: starting a debugging information engine module in the main control chip to acquire effective waveform signals output by a debugging interface connected with the debugging information engine module and convert the effective waveform signals into debugging waveform data; when the trigger condition is met, storing the debugging waveform data into a nonvolatile memory externally connected with the main control chip, and stopping collecting effective waveform signals after a certain amount of debugging waveform data is stored; and after receiving a reading command from the host, reading the debugging waveform data stored in the nonvolatile memory, and sending the read debugging waveform data to the host. Therefore, the problem that debugging interfaces connected with an external logic analyzer are not reserved in the main control chip, and signals inside the main control chip cannot be analyzed to be debugged is solved.
Description
Technical Field
The present disclosure relates to the field of chip verification technologies, and in particular, to a method for accessing built-in debugging information in a chip and an electronic device thereof.
Background
In the prior art, when an error (bug) occurs during the operation of a developed integrated circuit, a logic analyzer is usually connected to a debugging interface of the integrated circuit to capture the waveform of an internal signal and perform data analysis to eliminate the occurrence of the error.
With the continuous progress of science and technology, electronic devices are gradually developing towards miniaturization trend, so that the area design of a main control chip of the electronic device is also reduced (the number of PINs (PIN) of the main control chip is also limited and reduced), and a condition that a debugging interface or PINs capable of being externally connected with a logic analyzer are not reserved exists, or due to circuit layout factors, signals of a plurality of signal test points in the main control chip cannot be smoothly connected to the PINs of the chip, so that when an internal circuit of the main control chip works in error, the logic analyzer cannot be used for capturing waveforms of internal signals through the debugging interface to analyze and debug.
Disclosure of Invention
The embodiment of the application provides a debugging information access method and electronic equipment thereof, and can solve the problem that in the prior art, a main control chip of the electronic equipment has no debugging interface which can be externally connected with a logic analyzer due to the fact that the area is reduced, and when an error occurs in the work of an internal circuit of the main control chip, the logic analyzer cannot be used to capture the waveform of an internal signal through the debugging interface for analysis and debugging.
In order to solve the technical problem, the present application is implemented as follows:
the application provides a debugging information access method which is applied to a main control chip. The debugging information access method comprises the following steps: starting a debugging information engine module in the main control chip to acquire effective waveform signals output by a debugging interface connected with the debugging information engine module and convert the effective waveform signals into debugging waveform data; when the trigger condition is met, storing the debugging waveform data into a nonvolatile memory externally connected with the main control chip, and stopping collecting effective waveform signals after a certain amount of debugging waveform data is stored; and after receiving a reading command from the host, reading the debugging waveform data stored in the nonvolatile memory, and sending the read debugging waveform data to the host.
The application provides an electronic device, it includes: the main control chip is connected with the nonvolatile memory, and the nonvolatile memory is connected with the main control chip. The main control chip comprises: microprocessor, debugging information engine module and connection interface module. The debugging information engine module is used for acquiring effective waveform signals in the main control chip after being started by the microprocessor and converting the effective waveform signals into debugging waveform data; and storing the converted debugging waveform data to a nonvolatile memory when the trigger condition is satisfied. The connection interface module is used for being connected with an external host. After receiving a read command from the host, the main control chip reads the debugging waveform data stored in the nonvolatile memory and sends the read debugging waveform data to the host.
In the embodiment of the application, the debugging information engine module is configured inside the main control chip, so that the main control chip can meet the market development requirement without reserving a debugging interface which can be externally connected with a logic analyzer; through the configuration of the debugging information engine module, the setting of the triggering condition and the configuration of the main control chip external nonvolatile memory, when the internal circuit of the main control chip works in error, debugging waveform data before and after the error can be stored in the nonvolatile memory, and the host can read the debugging waveform data before and after the internal circuit works in error through the main control chip, so that the technical scheme that the signal waveform of the debugging interface of the internal circuit is captured by the main control chip external logic analyzer to be analyzed in the prior art is replaced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a block diagram of an embodiment of an electronic device connected to a host according to the present application;
FIG. 2 is a block diagram of another embodiment of an electronic device connected to a host according to the present application;
FIG. 3 is a schematic diagram illustrating an embodiment of a debug information engine module and associated debug interface according to the present application;
FIG. 4 is a schematic diagram illustrating another embodiment of a debug information engine module and associated debug interface according to the present application;
FIG. 5 is a flowchart of an embodiment of a method for accessing debug information according to the present application;
FIG. 6 is a flowchart of another embodiment of a method for accessing debug information according to the present application; and
FIG. 7 is a flowchart of a method of accessing debug information according to another embodiment of the present application.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operations, components, and/or components, but do not preclude the presence or addition of further features, values, method steps, operations, components, and/or groups thereof.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Please refer to fig. 1, which is a block diagram illustrating an embodiment of an electronic device and a host according to the present application. As shown in fig. 1, the electronic device 100 includes: the main control chip 110 is connected with the nonvolatile memory 120, and the nonvolatile memory 120 is connected with the main control chip 110. The electronic device 100 may be, but is not limited to, a solid state disk; the main control chip 110 may be a main control module of the solid state disk; the non-volatile memory 120 may be, but is not limited to, a flash memory having a characteristic that the stored data is not lost when the electronic device 100 is powered down or the host 200 connected to the electronic device 100 is powered down.
In an example, the non-volatile memory 120 may be a Serial Peripheral Interface Flash (SPI Flash) and is connected to the SPI control module 112 of the main control chip 110 through an SPI. The non-volatile memory 120 is a Nor flash (Nor flash), which is simpler to operate than a NAND flash (NAND flash), and can access data at any address.
In another example, the nonvolatile memory 120 may be a NAND Flash memory included in a storage module of the solid state disk, and the NAND Flash memory is managed by a NAND Flash Control (NAND Flash Control) module of the solid state disk.
In this embodiment, the main control chip 110 includes: microprocessor 111, debug information engine module 114 and connection interface module 116, connection interface module 116 is used to connect with external host 200. The connection interface module 116 may be, but not limited to, a PCIE (peripheral component interconnect express) interface module, a SATA interface module, a USB interface module …, etc.
The microprocessor 111 has two modes of operation, one being an operating mode and the other being a debug mode. The operation mode is an original operation mode of the electronic device 100, for example: the main control chip 110 may be a main control module of a solid state disk, the working mode is a mode for accessing the solid state disk, and the debugging mode is a mode for starting the debugging information engine module 114 to collect an effective waveform signal in the main control chip 110 and store the collected effective waveform signal in the nonvolatile memory 120. The following further description is made with respect to the debug mode of the microprocessor 111:
the debug information engine module 114 is used for acquiring an effective waveform signal output by the debug interface 10 of a module to be debugged, which is connected with the debug information engine module 114 in the main control chip 110, after being turned on by the microprocessor 111, and converting the effective waveform signal into debug waveform data; and when it is detected that the trigger condition is satisfied, storing the debugging waveform data in the nonvolatile memory 120, and stopping collecting the effective waveform signal after storing a certain amount of the debugging waveform data. The debug interface 10 in the main control chip 110 connected to the debug information engine module 114 may be, but is not limited to, a debug interface of at least one module circuit in the main control chip 110 (please refer to the description of other embodiments later), it should be noted that, in order to avoid the complexity of the drawing of fig. 1, only one debug interface 10 is drawn and presented in fig. 1 in an independent component manner; the format of the debugging waveform data can be, but is not limited to, binary data or cvs (comma Value separated) data, and the debugging waveform data includes a timestamp for marking the sequence of different debugging waveform data; the amount of the debugging waveform data can be adjusted according to the actual requirement (since each debugging waveform data corresponds to a timestamp, the conversion of the amount of the debugging waveform data can be interpreted as the conversion of the effective waveform signals in a certain time section).
In the present embodiment, after receiving the read command from the host 200, the main control chip 110 reads the debug waveform data stored in the nonvolatile memory 120, and sends the read debug waveform data to the host 200.
In an embodiment, the trigger condition may include, but is not limited to, a level trigger, an edge trigger, a timeout trigger, a width trigger, or a firmware trigger. Wherein the level trigger is triggered within the time of high or low level hold; the edge triggering is triggered by a rising edge or a falling edge; the overtime trigger is triggered when the time of the signal lasting above (or below) the default trigger level reaches the set time; the width trigger is a trigger generated according to the pulse width of the signal; the firmware trigger is a forced trigger through setting, for example: the instruction of the register related to the trigger is put in the firmware program before a certain program to force the trigger, so that a certain amount of debugging waveform data after the program can be recorded. In an embodiment, the debug information engine module 114 may further include a register 60 for storing a size of a memory space in which the nonvolatile memory 120 is set to store the debug waveform data, a base address of the memory space, and the trigger condition. In one embodiment, if the non-volatile memory 120 is a Nor flash (Nor flash), the base address of the memory space refers to an address of a Nor flash (Nor flash); in another embodiment, if the nonvolatile memory 120 is a NAND flash (NAND flash), the base address of the memory space refers to an address of an SRAM in the main control chip 110; in yet another embodiment, if the non-volatile memory 120 can be a serial peripheral interface flash memory, the base address of the memory space is a serial peripheral interface address (SPI address). The size of the storage space, the base address of the storage space and the trigger condition can be set according to actual requirements.
In one embodiment, please refer to fig. 2, which is a block diagram illustrating another embodiment of an electronic device and a host according to the present application. As shown in fig. 2, the debug information engine module 114 may include a buffer 20, a debug information control unit 30, a debug trigger control unit 40, and a debug engine bus interface unit 50, the debug engine bus interface unit 50 being connected to the buffer 20, the debug information control unit 30 being connected to the buffer 20. The debug information control unit 30 is configured to acquire the effective waveform signal after being turned on by the microprocessor 111, convert the effective waveform signal into the debug waveform data, and store the debug waveform data in the buffer 20; the debug trigger control unit 40 may be configured to detect whether the trigger condition is satisfied, and when the trigger condition is satisfied, the debug engine bus interface unit 50 is enabled to transmit the debug waveform data temporarily stored in the buffer 20 to the non-volatile memory 120 through the bus 118 of the main control chip 110 for storage. The buffer 20 may be, but is not limited to, a First-In-First-out (FIFO) buffer. Further, register 60 may connect debug information control unit 30 and debug trigger control unit 40.
In an embodiment, since the read command received by the host chip 110 may be a command customized by a manufacturer, the read command may have a limited data amount read at one time (e.g., read 4k bytes of data at most at one time), and if the data amount of the debug waveform data stored in the nonvolatile memory 120 exceeds the data amount read at one time (e.g., the size of the storage space for storing the debug waveform data exceeds 4k bytes), a segmented read is required. Therefore, after receiving the read command from the host 200, the main control chip 110 reads the debug waveform data stored in the nonvolatile memory 120 in a segmented manner according to the read data amount corresponding to the read command, and sends the debug waveform data read in a segmented manner to the host 200.
In an embodiment, the main Control chip 110 may further include a nand flash Memory Control module, a SATA/PCIE interface module, a System Control (System Control) module, a Direct Memory Access (DMA) module, and/or a Power Control (Power Control) module, and thus, the debug interface 10 of the module to be debugged may include a debug interface of any one of the above modules (that is, the debug interface 10 connected to the debug information engine module 114 in the main Control chip 110 may be, but is not limited to, a debug interface of at least one module circuit in the main Control chip 110).
In an embodiment, please refer to fig. 3, which is a connection diagram illustrating an embodiment of a debug information engine module and a connected debug interface according to the present application. As shown in fig. 3, the debug information engine module 114 may further include a register 70 and a multiplexing unit 80, the register 70 is connected to the multiplexing unit 80, the register 70 may be configured to store at least one set debug interface index (index), and the multiplexing unit 80 may be configured to select a debug interface connected to the debug information engine module 114 based on the at least one debug interface index, where the at least one debug interface index may be set according to an actual requirement of a user. That is, since the debug interface 10 connected to the debug information engine module 114 in the host chip 110 may be, but is not limited to, a debug interface of at least one module circuit in the host chip 110, the debug interface connected to the debug information engine module 114 may be selected by setting the debug interface index. Specifically, the multiplexing unit 80 can be connected to the debug interfaces of the plurality of module circuits in the main control chip 110 (for example, the debug interface 10a of the nand-type flash memory control module, the debug interface 10b of the SATA/PCIE interface module, the debug interface 10c of the system control module, the debug interface 10d of the direct memory access module, and the debug interface 10e of the power control module), and the debug interface of each module circuit corresponds to a debug interface index, so that the multiplexing unit 80 can select the debug interface connected to the debug information engine module 114 based on the at least one debug interface index set by the user. The debug information engine module 114 is connected with a plurality of output channels of the debug interface selected by the multiplexing unit 80 through a plurality of input channels (channels) included therein; the number of the input channels and the output channels may be, but is not limited to, 64, and the number of the actual input channels and the number of the actual output channels may be adjusted according to actual requirements. Note that the debug interface index of the setting stored in register 70 may instead be stored in register 60 (i.e., debug information engine module 114 may include only one register for storing all the settings set by the user).
In another embodiment, please refer to fig. 4, which is a connection diagram illustrating another embodiment of a debug information engine module and a connected debug interface according to the present application. As shown in fig. 4, since the user may need to know the relationship between the plurality of module circuits in the main control chip 110 when the set trigger condition is satisfied, at this time, the debug information engine module 114 may not be connected to only one debug interface, and each input channel of the debug information engine module 114 may be connected to one output channel of different debug interfaces. That is, the register 70 may be used to store a plurality of debug interface indexes, and the multiplexing unit 80 may be used to select one output channel of different debug interfaces correspondingly connected to each input channel of the debug information engine module 114 based on the plurality of debug interface indexes, wherein one output channel of the debug interface of each module circuit corresponds to one debug interface index, and the debug interface index may be set according to the actual requirement of the user. Specifically, the debug information engine module 114 may include N input channels, the debug interface of each module circuit in the main control chip 110 (for example, the debug interface 10a of the nand-type flash memory control module, the debug interface 10b of the SATA/PCIE interface module, the debug interface 10c of the system control module, the debug interface 10d of the direct memory access module, and the debug interface 10e of the power control module) may include N output channels, the multiplexing unit 80 may include N multiplexers (for example, the multiplexer 80a to the multiplexer 80N), N is a positive integer greater than or equal to 2, and the input channels and the multiplexers are connected in a one-to-one manner; the output channels are connected with the multiplexer in a many-to-one manner, that is, the multiplexer 80a is further connected with a first output channel of the debugging interface of each module circuit in the main control chip 110, the multiplexer 80b is further connected with a second output channel of the debugging interface of each module circuit in the main control chip 110, and so on, the multiplexer 80N is further connected with an nth output channel of the debugging interface of each module circuit in the main control chip 110; the multiplexer 80a to the multiplexer 80n may be configured to select one output channel of different debug interfaces correspondingly connected to the input channels of the debug information engine module 114 based on a plurality of debug interface indexes set by a user.
In an embodiment, referring to fig. 4, the debug information engine module 114 may further include a synchronization unit 90, configured to synchronously send the multi-channel waveform signals to each input channel of the debug information engine module 114, so that the debug information engine module 114 collects the multi-channel effective waveform signals and converts the multi-channel effective waveform signals into the corresponding debug waveform data.
Referring to fig. 1 and 5, fig. 5 is a flowchart illustrating a method of accessing debug information according to an embodiment of the present disclosure. In this embodiment, the method for accessing debugging information can be applied to the main control chip 110 of the electronic device 100 and includes the following steps: starting a debugging information engine module 114 inside the main control chip 110 to collect an effective waveform signal output by a debugging interface 10 connected with the debugging information engine module 114, and converting the effective waveform signal into debugging waveform data (step 210); when the trigger condition is satisfied, storing the debugging waveform data in a nonvolatile memory 120 externally connected to the main control chip 111, and stopping collecting effective waveform signals after a certain amount of debugging waveform data is stored (step 220); and after receiving the read command from the host 200, reading the debug waveform data stored in the nonvolatile memory 120 and transmitting the read debug waveform data to the host 200 (step 230). Through steps 210 to 230, the host 200 can read the debugging waveform data before and after the internal circuit operation has an error through the main control chip 110, and the detailed description may refer to the related description of the electronic device 100, which is not repeated herein.
In an embodiment, before step 210, the method of accessing debug information may further comprise: the set nonvolatile memory 120 stores the memory size of the debug waveform data, the base address of the memory, and the trigger condition in the register 60 of the debug information engine module 114 (step 201). For a detailed description, reference may be made to the above description of the electronic device 100, which is not repeated herein.
In an embodiment, please refer to fig. 3 and 6, wherein fig. 6 is a flowchart illustrating another embodiment of a method for accessing debug information according to the present application. As shown in fig. 6, before step 210, the method for accessing debug information may further include: the set at least one debug interface index is stored in register 70 of debug information engine module 114 (step 202); and selecting a debug interface connected to the debug information engine module 114 based on the at least one debug interface index (step 203). For a detailed description, reference may be made to the above description of the electronic device 100, which is not repeated herein.
In another embodiment, please refer to fig. 4 and 7, wherein fig. 7 is a flowchart illustrating a method for accessing debug information according to another embodiment of the present application. As shown in fig. 7, before step 210, the method for accessing debug information may further include: the set plurality of debug interface indices are stored in registers 70 of debug information engine module 114 (step 204); and selecting one output channel of different debug interfaces connected corresponding to the respective input channels of the debug information engine module 114 based on the plurality of debug interface indexes (step 205). Wherein, step 210 may further include: the debug information engine module 114 inside the main control chip 110 is turned on, and the synchronization unit 90 of the debug information engine module 114 synchronously sends the valid waveform signal to the debug information engine module 114. For a detailed description, reference may be made to the above description of the electronic device 100, which is not repeated herein.
In an embodiment, referring to fig. 2, step 210 may further include: the debug information control unit 30 of the debug information engine module 114 is turned on by the microprocessor 111 to collect the valid waveform signal in the main control chip 110, convert the valid waveform signal into the debug waveform data, and store the debug waveform data in the buffer 20. For a detailed description, reference may be made to the above description of the electronic device 100, which is not repeated herein.
In an embodiment, referring to fig. 2, step 220 may further include: when the trigger condition is satisfied, the debug information engine module 114 causes the debug engine bus interface unit 50 of the debug information engine module 114 to transmit the debug waveform data temporarily stored in the buffer 20 to the non-volatile memory 120 for storage. For a detailed description, reference may be made to the above description of the electronic device 100, which is not repeated herein.
In an embodiment, referring to fig. 1 and fig. 2, step 230 may further include: the debugging waveform data stored in the nonvolatile memory 120 is read in segments according to the read data amount corresponding to the read command from the host 200, and the debugging waveform data read in segments is sent to the host 200. For a detailed description, reference may be made to the above description of the electronic device 100, which is not repeated herein.
In summary, in the embodiment of the present application, the debug information engine module is configured inside the main control chip, so that the main control chip does not need to reserve a debug interface capable of being externally connected to the logic analyzer according to the market development requirement; through the configuration of the debugging information engine module, the setting of the triggering condition and the configuration of the main control chip external nonvolatile memory, when the internal circuit of the main control chip works in error, debugging waveform data before and after the error can be stored in the nonvolatile memory, and the host can read the debugging waveform data before and after the internal circuit works in error through the main control chip, so that the technical scheme that the signal waveform of the debugging interface of the internal circuit is captured by the main control chip external logic analyzer to be analyzed in the prior art is replaced.
Although the above-described elements are included in the drawings of the present application, it is not excluded that more additional elements may be used to achieve better technical results without departing from the spirit of the invention.
While the invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. Rather, this invention encompasses modifications and similar arrangements as would be apparent to one skilled in the art. The scope of the claims is, therefore, to be construed in the broadest manner to include all such obvious modifications and similar arrangements.
Claims (11)
1. A debugging information access method is applied to a main control chip and is characterized by comprising the following steps:
step (A): starting a debugging information engine module in the main control chip to acquire an effective waveform signal output by a debugging interface connected with the debugging information engine module and convert the effective waveform signal into debugging waveform data;
step (B): when the trigger condition is met, storing the debugging waveform data into a nonvolatile memory externally connected with the main control chip, and stopping collecting the effective waveform signal after a certain amount of debugging waveform data is stored; and
step (C): and after receiving a reading command from a host, reading the debugging waveform data stored in the nonvolatile memory, and sending the read debugging waveform data to the host.
2. The method of accessing debug information according to claim 1, further comprising, before said step (a):
the set storage space size of the nonvolatile memory for storing the debugging waveform data, the base address of the storage space and the trigger condition are stored in a register of the debugging information engine module.
3. The method of accessing debug information according to claim 1, further comprising, before said step (a):
the set at least one debugging interface index is stored in a register of the debugging information engine module; and
selecting the debug interface connected with the debug information engine module based on the at least one debug interface index.
4. The method according to claim 1, wherein the step (C) further comprises:
and reading the debugging waveform data stored in the nonvolatile memory in a segmented manner according to the read data amount corresponding to the read command, and sending the debugging waveform data read in the segmented manner to the host.
5. An electronic device, comprising:
a non-volatile memory; and
a main control chip, and the main control chip is connected, and includes:
a microprocessor;
the debugging information engine module is used for acquiring effective waveform signals in the main control chip after being started by the microprocessor and converting the effective waveform signals into debugging waveform data; and storing the converted debugging waveform data to the non-volatile memory when a trigger condition is satisfied; and
the connection interface module is used for being connected with an external host;
after receiving a read command from the host, the main control chip reads the debugging waveform data stored in the nonvolatile memory and sends the read debugging waveform data to the host.
6. The electronic device of claim 5, wherein the trigger condition comprises a level trigger, an edge trigger, a timeout trigger, a width trigger, or a firmware trigger.
7. The electronic device according to claim 5, wherein the debug information engine module includes a register for storing a set memory size of the nonvolatile memory in which the debug waveform data is stored, a base address of the memory space, and the trigger condition.
8. The electronic device of claim 5, wherein the debug information engine module comprises a register and a multiplexing unit, the register is connected to the multiplexing unit, the register is used for storing at least one set debug interface index, and the multiplexing unit is used for selecting a debug interface connected to the debug information engine module based on the at least one debug interface index.
9. The electronic device of claim 5, wherein the debug information engine module comprises a synchronization unit configured to synchronously send the valid waveform signal to the debug information engine module.
10. The electronic device of claim 5, wherein the debug information engine module comprises:
a buffer;
the debugging engine bus interface unit is connected with the buffer;
the debugging information control unit is connected with the buffer and used for converting the effective waveform signal into the debugging waveform data and storing the debugging waveform data into the buffer; and
and the debugging trigger control unit is used for enabling the debugging engine bus interface unit to transmit the debugging waveform data temporarily stored in the buffer to the nonvolatile memory for storage when the trigger condition is met.
11. The electronic device of claim 5, wherein the non-volatile memory is a serial peripheral interface flash memory and is connected to the serial peripheral interface control module of the main control chip through a serial peripheral interface.
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| TW111104634A TWI824406B (en) | 2021-11-18 | 2022-02-08 | Method for accessing debugging information of checkpoints in a chip and electronic apparatus thereof |
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| US9996449B2 (en) * | 2015-03-27 | 2018-06-12 | Intel Corporation | Instruction and logic for a convertible innovation and debug engine |
| JP2017045288A (en) * | 2015-08-27 | 2017-03-02 | 株式会社東芝 | Memory system |
| US10054636B2 (en) * | 2015-10-23 | 2018-08-21 | Intel IP Corporation | Device, system and method to support communication of test, debug or trace information with an external input/output interface |
| US10634723B2 (en) * | 2017-01-03 | 2020-04-28 | Advantest Corporation | Method and system for acquisition of test data |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115079803A (en) * | 2022-05-20 | 2022-09-20 | 上海瑞浦青创新能源有限公司 | Abnormal power failure data storage device suitable for microcontroller |
| CN115079803B (en) * | 2022-05-20 | 2024-03-29 | 上海瑞浦青创新能源有限公司 | Abnormal power-down data storage device suitable for microcontroller |
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| Publication number | Publication date |
|---|---|
| TW202321917A (en) | 2023-06-01 |
| TWI824406B (en) | 2023-12-01 |
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