CN114189797B - Earphone detection circuit, chip and audio equipment - Google Patents
Earphone detection circuit, chip and audio equipment Download PDFInfo
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- CN114189797B CN114189797B CN202111656077.0A CN202111656077A CN114189797B CN 114189797 B CN114189797 B CN 114189797B CN 202111656077 A CN202111656077 A CN 202111656077A CN 114189797 B CN114189797 B CN 114189797B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R29/00—Monitoring arrangements; Testing arrangements
- H04R29/001—Monitoring arrangements; Testing arrangements for loudspeakers
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- General Health & Medical Sciences (AREA)
- Otolaryngology (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Headphones And Earphones (AREA)
- Circuit For Audible Band Transducer (AREA)
- Stereophonic Arrangements (AREA)
Abstract
The embodiment of the invention relates to the technical field of electronic circuits, and provides an earphone detection circuit, a chip and audio equipment, wherein the earphone detection circuit comprises an earphone socket circuit for plugging earphones of different plug types; the first voltage bias circuit is electrically connected with the earphone jack circuit, and a first node is arranged on a connecting path of the first voltage bias circuit and the earphone jack circuit; the second voltage bias circuit is electrically connected with the earphone jack circuit, and a second node is arranged on a connecting path of the second voltage bias circuit and the earphone jack circuit; the controller is electrically connected with the first voltage bias circuit and the second voltage bias circuit respectively, can control the first voltage bias circuit and the second voltage bias circuit to be in different working states, and detects the plug type of the earphone according to the node voltages of the first node and the second node in the corresponding working states. Through the embodiment of the invention, the detection of the earphone with different plug types can be realized.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic circuits, in particular to an earphone detection circuit, a chip and audio equipment.
Background
According to whether the earphone has microphone function division or not, the earphone comprises a 3-section plug type and a 4-section plug type, wherein the 4-section plug type comprises a North American type standard and a European type standard, the audio configurations of audio equipment corresponding to the North American type standard and the European type standard are different, and the plug type of the earphone determines how the audio equipment matched with the earphone configures the microphone function and ensures the normal use of the audio function. Accordingly, it would be desirable to provide techniques for detecting the plug type of headphones.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a headset detecting circuit, a chip, and an audio device, which are capable of detecting a plug type of a headset.
In order to solve the technical problems, the embodiment of the invention provides the following technical scheme:
in a first aspect, an embodiment of the present invention provides an earphone detection circuit, including:
the earphone jack circuit is used for plugging earphones with different plug types;
the first voltage bias circuit is electrically connected with the earphone jack circuit, and a first node is arranged on a connecting path of the first voltage bias circuit and the earphone jack circuit;
the second voltage bias circuit is electrically connected with the earphone jack circuit, and a second node is arranged on a connecting path of the second voltage bias circuit and the earphone jack circuit;
the controller is respectively and electrically connected with the first voltage bias circuit and the second voltage bias circuit, can control the first voltage bias circuit and the second voltage bias circuit to be in different working states, and detects the plug type of the earphone according to node voltages of the first node and the second node in corresponding working states.
Optionally, the controller controls the first voltage bias circuit and the second voltage bias circuit to be in an enabled state, and configures node voltages of the first node and the second node to be initial voltages;
the controller controls the first voltage bias circuit to enter a non-enabling state, controls the second voltage bias circuit to enter a bias state, configures the node voltage of the first node from the initial voltage to a first voltage, and configures the node voltage of the second node from the initial voltage to a second voltage;
the controller detects the plug type of the earphone according to the first voltage and the second voltage.
Optionally, the second voltage bias circuit includes a clamp circuit and a current source circuit, and the clamp circuit is electrically connected with the current source circuit and is also commonly and electrically connected to the second node;
when the second voltage bias circuit is in an enabling state, the clamping circuit is in an enabling state, and the controller controls the current source circuit to enter a working state so that the second voltage bias circuit enters a bias state;
when the controller controls the first voltage bias circuit to enter a non-enabled state and the second voltage bias circuit enters a biased state, under the combined action of the clamp circuit and the current source circuit, the node voltage of the second node is configured to be a second voltage, and under the action of the clamp circuit, the current source circuit and the resistance values of the earphone jack circuit between the first node and the second node, the node voltage of the first node is configured to be a first voltage. Optionally, if the second voltage is equal to the first voltage, the controller detects that the plug type of the earphone is a 3-segment plug type;
and if the second voltage is not equal to the first voltage, the controller further judges the plug type of the earphone. Optionally, the earphone jack circuit includes a left channel port, a right channel port, a first detection port and a second detection port, where the first detection port is electrically connected to the first node, and the second detection port is electrically connected to the second node;
the controller controls the first voltage bias circuit to enter an enabling state again, and further judges the plug type of the earphone according to the left channel voltage of the left channel port and the right channel voltage of the right channel port.
Optionally, if the left channel voltage and the right channel voltage are equal to the initial voltages, respectively, the plug type of the earphone is north american;
if the left channel voltage and the right channel voltage are respectively equal to the second voltage, the plug type of the earphone is European;
if the left channel voltage and the right channel voltage are equal to zero, respectively, no earphone is inserted into the earphone jack circuit.
Optionally, if the left channel voltage and the right channel voltage are equal to the initial voltages respectively, the controller controls the clamping circuit to enter a non-enabled state, and configures an audio input channel of the earphone;
if the left channel voltage and the right channel voltage are respectively equal to the second voltage, the controller controls the first voltage bias circuit to enter a non-enabling state again, and the audio input channel of the earphone is configured;
and if the left channel voltage and the right channel voltage are equal to zero respectively, the controller controls the current source circuit to enter a non-working state, and the steps of detecting the plug type of the earphone after the controller controls the first voltage bias circuit to enter a non-enabling state and controls the second voltage bias circuit to enter a bias state are repeated.
Optionally, a microphone input circuit is further included, and the microphone input circuit is electrically connected with the earphone jack circuit and the controller respectively and is used for processing audio input signals.
Optionally, the device further comprises an audio output circuit, wherein the audio output circuit is respectively and electrically connected with the earphone jack circuit and the controller and is used for outputting an audio output signal.
In a second aspect, an embodiment of the present invention provides a chip including a headset detection circuit as described in any one of the preceding claims.
In a third aspect, an embodiment of the present invention provides an audio device, including a headphone detection circuit as described in any one of the preceding claims. Compared with the prior art, the embodiment of the invention provides an earphone detection circuit, a chip and audio equipment, wherein an earphone jack circuit is arranged for plugging earphones of different plug types, a first node is arranged on an electric connection path of a first voltage bias circuit and the earphone jack circuit, a second node is arranged on an electric connection path of a second voltage bias circuit and the earphone jack circuit, then the first voltage bias circuit and the second voltage bias circuit are controlled by a controller to be in different working states, and the plug type of the earphone is detected according to node voltages of the first node and the second node in corresponding working states. Therefore, the embodiment of the invention realizes the detection of the earphone with different plug types.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic structural diagram of an earphone detection circuit according to an embodiment of the present invention;
fig. 2a is a schematic structural diagram of a 3-section plug type earphone according to an embodiment of the present invention;
fig. 2b is a schematic structural diagram of a north american type earphone according to an embodiment of the present invention;
fig. 2c is a schematic structural diagram of a european earphone according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an earphone jack circuit shown in fig. 1 according to an embodiment of the present invention;
fig. 4a is a schematic plugging diagram of the earphone jack shown in fig. 3 and the 3-section plug type earphone shown in fig. 2a according to the embodiment of the present invention;
fig. 4b is a schematic illustration of plugging of the earphone jack shown in fig. 3 and the north american type earphone shown in fig. 2b according to the embodiment of the present invention;
fig. 4c is a schematic plugging diagram of the earphone jack shown in fig. 3 and the european earphone shown in fig. 2c according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of a second bias voltage circuit shown in FIG. 1 according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another earphone detection circuit according to an embodiment of the present invention;
fig. 7 is a schematic circuit connection diagram of an earphone detection circuit according to an embodiment of the present invention.
Detailed Description
In order to facilitate an understanding of the present application, the present application will be described in more detail below with reference to the accompanying drawings and detailed description. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or one or more intervening elements may be present therebetween. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Fig. 1 is a schematic structural diagram of an earphone detection circuit according to an embodiment of the present invention. As shown in fig. 1, the headphone detection circuit 100 includes a headphone jack circuit 10, a first voltage bias circuit 20, a second voltage bias circuit 30, and a controller 40.
The earphone jack circuit 10 is used for plugging in earphones of different plug types. The plug type comprises a 3-section plug type, a North American type and a European type, wherein the North American type and the European type are 4 sections.
As shown in fig. 2a, an end (not shown) of the earphone plug is defined as a near end, the 3-section plug type sequentially comprises a left channel end L, a right channel end R and a ground end G from the far end to the near end, a resistor LG1 is connected between the left channel end L and the ground end G, and a resistor RG1 is connected between the right channel end R and the ground end G.
As shown in fig. 2b, the north american type sequentially includes a left channel end L, a right channel end R, a ground end G, and a microphone end M from the far end to the near end, a resistor LG2 is connected between the left channel end L and the ground end G, a resistor RG2 is connected between the right channel end R and the ground end G, and a resistor MG1 is connected between the microphone end M and the ground end G.
As shown in fig. 2c, the european type sequentially includes a left channel end L, a right channel end R, a microphone end M, and a ground end G from the far end to the near end, a resistor LG3 is connected between the left channel end L and the ground end G, a resistor RG3 is connected between the right channel end R and the ground end G, and a resistor MG2 is connected between the microphone end M and the ground end G.
Specifically, as shown in fig. 3, the headphone jack circuit 10 includes a headphone jack 11 and a voltage generating circuit 12.
The earphone jack 11 includes a left channel port 11a, a right channel port 11b, a first detection port 11c, and a second detection port 11d, where the first detection port 11c is electrically connected to the first node a, and the second detection port 11d is electrically connected to the second node b.
It will be appreciated that the earphone jack 11 is adapted to an earphone plug, and that fig. 4a to 4c show schematic views of the plugging of earphones of different plug types to the earphone plug 11.
As shown in fig. 4a, when the earphone is of the 3-section plug type, the left channel end L is correspondingly connected to the left channel port 11a, the right channel end R is correspondingly connected to the left channel port 11b, and the ground end G is correspondingly connected to the first detection port 11c and the second detection port 11d, respectively, at this time, the potential of the first node a is equal to the potential of the second node b.
As shown in fig. 4b, when the earphone is of north american type, the left channel end L is correspondingly connected to the left channel port 11a, the right channel end R is correspondingly connected to the left channel port 11b, the ground end G is correspondingly connected to the first detection port 11c, and the microphone end M is correspondingly connected to the second detection port 11d, and at this time, the resistor MG1 between the microphone end M and the ground end G is connected to the current loop between the first node a and the second node b.
As shown in fig. 4c, when the earphone is of the european type, the left channel terminal L is correspondingly connected to the left channel port 11a, the right channel terminal R is correspondingly connected to the left channel port 11b, the microphone terminal M is correspondingly connected to the first detection port 11c, and the ground terminal G is correspondingly connected to the second detection port 11d, and at this time, the resistor MG2 between the microphone terminal M and the ground terminal G is connected to the current loop between the first node a and the second node b.
The voltage generating circuit 12 is electrically connected to the first detection port 11c and the second detection port 11d, the voltage generating circuit 12 intersects the first detection port 11c at one point, the voltage generating circuit 12 intersects the second detection port 11d at another point, the first node a is electrically connected to an intersection point of the voltage generating circuit 12 and the first detection port 11c, and the second node b is electrically connected to an intersection point of the voltage generating circuit 12 and the second detection port 11 d.
For example, referring to fig. 7, the voltage generating circuit 12 includes a resistor R1, a resistor R2, a capacitor C1 and a capacitor C2, wherein one end of the resistor R1 is configured with an input power supply voltage VCC, the other end of the resistor R1 is electrically connected to the first detection port 11C, one end of the capacitor C1 and the first node a, the other end of the capacitor C1 is grounded, one end of the resistor R2 is configured with an input power supply voltage VCC, and the other end of the resistor R2 is electrically connected to the second detection port 11d, one end of the capacitor C2 and the second node b, respectively, and the other end of the capacitor C2 is grounded.
The first voltage bias circuit 20 is electrically connected to the headphone jack circuit 10, and a first node a is provided on a connection path between the first voltage bias circuit 20 and the headphone jack circuit 10.
The first voltage bias circuit 20 is illustratively a voltage follower circuit. As shown in fig. 7, the first voltage bias circuit 20 may be configured to include an operational amplifier OPA1 and a resistor R3, the non-inverting input terminal of the operational amplifier OPA1 being configured to input the initial voltage VCM, and the inverting input terminal of the operational amplifier OPA1 being connected to the output terminal of the operational amplifier OPA1 and the first node a through the resistor R3.
In some embodiments, the first voltage bias circuit 20 further includes a resistor R4 and a switch SW1, and the output terminal of the operational amplifier OPA1 sequentially passes through the resistor R4 and the switch SW1 and then is grounded. When the operational amplifier OPA1 is in the enabled state and the switch SW1 is in the off state, the node voltage of the first node a is equal to the initial voltage VCM.
Optionally, the connection path between the first node a and the earphone jack circuit 10 further includes a current limiting circuit, such as a resistor R5 shown in fig. 7, where the resistor R5 is connected in series between the first detection port 11c and the first node a.
Referring to fig. 1, the second voltage bias circuit 30 is electrically connected to the earphone jack circuit 10, and a second node b is disposed on a connection path between the second voltage bias circuit 30 and the earphone jack circuit 10.
Specifically, as shown in fig. 5, the second voltage bias circuit 30 includes a clamp circuit 31 and a current source circuit 32, and the clamp circuit 31 is electrically connected to the current source circuit 32 and also commonly connected to the second node b.
As illustrated in fig. 7, the clamp circuit 31 includes an operational amplifier OPA2 and a resistor R5, wherein a non-inverting input terminal of the operational amplifier OPA2 is configured to input an initial voltage VCM, and an inverting input terminal of the operational amplifier OPA2 is connected to an output terminal of the operational amplifier OPA2 and the second node b through the resistor R5.
In some embodiments, the clamp circuit 31 further includes a resistor R7 and a switch SW3, and the output terminal of the operational amplifier OPA2 sequentially passes through the resistor R7 and the switch SW3 and then is grounded.
When the operational amplifier OPA2 is in the enabled state and the switch SW3 is in the off state, the node voltage of the second node b is equal to the initial voltage VCM.
The current source circuit 32 includes a current source i1 and a switch SW2, one end of the current source i1 is connected to the inverting input terminal of the operational amplifier OPA2, and the other end of the current source i1 is grounded through the switch SW 2.
When the operational amplifier OPA2 is in the enabled state and the switch SW2 is in the closed state, the node voltage of the second node b is configured as vcm+i1×r5.
Optionally, the connection path between the second node b and the earphone jack circuit 10 further includes a current limiting circuit, such as a resistor R8 shown in fig. 7, where the resistor R8 is connected in series between the second detection port 11d and the second node b.
The controller 40 is electrically connected to the first voltage bias circuit 20 and the second voltage bias circuit 30, and the controller 40 can control the first voltage bias circuit 20 and the second voltage bias circuit 30 to be in different working states, and detect the plug type of the earphone according to the node voltages of the first node a and the second node b in the corresponding working states.
The controller 40 can control the first voltage bias circuit 20 and the second voltage bias circuit 30 to be in different working states, and detect the plug type of the earphone according to the node voltages of the first node a and the second node b in the corresponding working states, and specifically includes: the controller 40 controls the first voltage bias circuit 20 and the second voltage bias circuit 30 to be in an enabled state, and configures node voltages of the first node a and the second node b to be initial voltages; the controller 40 controls the first voltage bias circuit 20 to enter a non-enabled state, controls the second voltage bias circuit 30 to enter a biased state, configures the node voltage of the first node a from an initial voltage to a first voltage, and configures the node voltage of the second node b from the initial voltage to a second voltage; the controller 40 detects the plug type of the earphone according to the first voltage and the second voltage.
Further, when the second voltage bias circuit 30 is in the enabled state, the clamp circuit 31 is in the enabled state, the controller controls the current source circuit 32 to enter the working state so as to enable the second voltage bias circuit 30 to enter the biased state, when the controller 40 controls the first voltage bias circuit 20 to enter the disabled state, the node voltage of the second node b is configured as the second voltage under the combined action of the clamp circuit 31 and the current source circuit 32, and the node voltage of the first node a is configured as the first voltage under the action of the resistance values of the earphone jack circuit 10 among the clamp circuit 31, the current source circuit 32 and the first node a and the second node b.
Further, detecting the plug type of the earphone according to the node voltages of the first node a and the second node b in the corresponding working states specifically includes: if the second voltage is equal to the first voltage, the controller 40 detects that the plug type of the earphone is a 3-segment plug type; if the second voltage is not equal to the first voltage, the controller further judges the plug type of the earphone.
Further, the controller 40 controls the first voltage bias circuit 20 to enter the enabled state again, and further determines the plug type of the earphone according to the left channel voltage of the left channel port 11a and the right channel voltage of the right channel port 11 b. Specifically, if the left channel voltage and the right channel voltage are equal to the initial voltages respectively, the plug type of the earphone is north american; if the left channel voltage and the right channel voltage are respectively equal to the second voltage, the plug type of the earphone is European; if the left channel voltage and the right channel voltage are both equal to zero, respectively, there is no earphone inserted into the earphone jack circuit 10.
As shown in fig. 7, the controller 40 includes a binary search analog-to-digital converter sar adc, a switch SW4, a switch SW5, a switch SW6, and a switch SW7, the switch SW4, the switch SW5, the switch SW6, and the switch SW7 are in an off state, one ends of the switch SW4, the switch SW5, the switch SW6, and the switch SW7 are respectively connected to a first node a, a second node b, a third node c, and a fourth node d, the other ends of the switch SW4, the switch SW5, the switch SW6, and the switch SW7 are respectively connected to the binary search analog-to-digital converter sar adc, the third node c is further connected to the left channel port 11a, the fourth node d is further connected to the right channel port 11b, and the binary search analog-to-digital converter sar adc is used for recording node voltages of the first node a, the second node b, the third node c, and the fourth node d are in different operation states of the first voltage bias circuit 20 and the second voltage bias circuit 30.
It will be appreciated that the controller 40 includes other control portions, not shown in the drawings, for controlling the closing of the switches SW1 to SW7, controlling the enable states of the operational amplifiers OPA1 and OPA2, and performing signal processing on the audio input output signals.
In the embodiment of the present invention, if the left channel voltage and the right channel voltage are equal to the initial voltages respectively, the controller 40 controls the clamping circuit 31 to enter a non-enabled state, and configures the audio input channel of the earphone; if the left channel voltage and the right channel voltage are equal to the second voltage, the controller 40 controls the first voltage bias circuit 20 to enter the non-enabled state again, and configures the audio input channel of the earphone; if the left channel voltage and the right channel voltage are equal to zero, the controller 40 controls the current source circuit 32 to enter a non-operating state, and the steps of detecting the plug type of the earphone after the controller 40 controls the first voltage bias circuit 20 to enter a non-enabling state and controls the second voltage bias circuit 30 to enter a bias state are repeated.
Referring to fig. 1, 5 and 7 again, the operation of the earphone detection circuit 100 is as follows:
in the first step, the chip is powered on, and during the power-on process of the chip, the controller 40 controls the operational amplifier OPA1 and the operational amplifier OPA2 to be in an enabled state, and the switches SW1, SW2, SW3 and SW4-SW7 are in an off state, and at this time, the node voltages of the first node a and the second node b are configured as the initial voltage VCM.
Step two, the controller 40 controls the operational amplifier OPA1 to enter a disabled state, controls the switch SW2 to be closed, and controls the current source circuit 32 to enter an operating state, so that the second voltage bias circuit 30 enters a biased state, and at this time, the node voltage of the first node a is configured from the initial voltage VCM to a first voltage, and the node voltage of the second node b is configured from the initial voltage VCM to a second voltage: vcm+i1×r5, the controller 40 controls the on switch SW5, the binary search analog-to-digital converter sar adc records the second voltage data_vb, and then the controller 40 controls the off switch SW5.
In step three, the controller 40 controls the switch SW4 to be closed, the binary search analog-to-digital converter sar adc records the first voltage data_va, and then the controller 40 controls the switch SW4 to be opened.
Step four, the controller 40 obtains the first voltage data_va and the second voltage data_vb, compares the magnitudes of the first voltage data_va and the second voltage data_vb, and if the first voltage data_va and the second voltage data_vb are equal, the controller 40 detects that the plug type of the earphone is a 3-segment plug type. As described above, since the 3-segment plug type does not include the microphone terminal, when the operational amplifier OPA1 enters the disabled state, the operational amplifier OPA2 is in the enabled state, the potential of the first node a is equal to that of the second node b when the current source circuit 3 enters the active state, the node voltage of the first node a is clamped to vcm+i1×r5, and when the first voltage data_va and the second voltage data_vb are equal, the plug type of the earphone is determined to be the 3-segment plug type.
Step five, if the first voltage data_va and the second voltage data_vb are not equal, the controller 40 controls the operational amplifier OPA1 to enter the enabled state again, and at this time, the node voltage of the first node a is equal to the initial voltage VCM, and the node voltage of the second node b is equal to the second voltage vcm+i1×r5. The controller 40 sequentially controls the on-off switches SW4-SW7, and the binary search analog-to-digital converter sar adc records node voltages of the first node a, the second node b, the third node c, and the fourth node d, wherein the third node c is electrically connected to the left channel port 11a, the node voltage of the third node c is a left channel voltage, the fourth node d is electrically connected to the right channel port 11b, and the node voltage of the fourth node d is a right channel voltage. The controller 40 detects the plug type of the earphone according to the node voltages of the first node a, the second node b, the third node c and the fourth node d, specifically, if the left channel voltage and the right channel voltage are equal to the initial voltage VCM respectively, the plug type of the earphone is determined to be north american type, the controller 40 controls the operational amplifier OPA2 to enter the non-enabled state, and the second node b is used as the input end of the microphone channel; if the left channel voltage and the right channel voltage are equal to the second voltage vcm+i1×r5, determining that the plug type of the earphone is european type, the controller 40 controls the operational amplifier OPA1 to enter the disabled state again, and uses the first node a as the input end of the microphone channel; if the left channel voltage and the right channel voltage are both equal to zero, respectively, then there is no earphone insertion.
Step six, the left channel port 11a and the right channel port 11b start to power up.
Fig. 6 is a schematic structural diagram of another earphone detection circuit according to an embodiment of the present invention. As shown in fig. 6, the earphone detection circuit 200 includes the earphone detection circuit 100 according to any of the above embodiments, and the microphone input circuit 50 and/or the audio output circuit 60, where the microphone input circuit 50 is electrically connected to the earphone jack circuit 10 and the controller 40, respectively, for processing the audio input signal. The audio output circuit 60 is electrically connected to the headphone jack circuit 10 and the controller 40, respectively, for outputting audio output signals.
Optionally, the microphone input circuit 50 includes a capacitor C3, a capacitor C4, an operational amplifier OPA3, variable resistors R9-R12, and an analog-to-digital converter ADC, and the connection relationship between the above components is shown in fig. 7, which is not repeated here. It should be noted that, the capacitor C3 and the capacitor C4 may be omitted in some application examples, and the resistance values of the variable resistors R9-R12 are set according to actual situations, and the analog-to-digital converter ADC is further connected to the controller 40.
Optionally, the audio output circuit 60 includes an operational amplifier OPA4, an operational amplifier OPA5, variable resistors R13-R16, a capacitor C5, a capacitor C6, a digital-to-analog converter DAC1 and a digital-to-analog converter DAC2, and the connection relationship between the above components is shown in fig. 7, which is not repeated here. It should be noted that, the resistance values of the variable resistors R13 to R16 are set according to actual situations, and the digital-to-analog converter DAC1 and the digital-to-analog converter DAC2 are further connected to the controller 40.
The embodiment of the invention provides an earphone detection circuit, which is characterized in that an earphone jack circuit is arranged for plugging earphones of different plug types, a first node is arranged on an electric connection path of a first voltage bias circuit and the earphone jack circuit, a second node is arranged on an electric connection path of a second voltage bias circuit and the earphone jack circuit, then the first voltage bias circuit and the second voltage bias circuit are controlled by a controller to be in different working states, and the plug type of the earphone is detected according to node voltages of the first node and the second node in corresponding working states. Therefore, the embodiment of the invention realizes the detection of the earphone with different plug types.
The embodiment of the invention also provides a chip, which comprises the earphone detection circuit in any embodiment. Taking a built-in Type-C to 3.5mm audio conversion chip as an example, the audio conversion chip includes the earphone detection circuit described in any embodiment, and when the earphone is inserted into a socket corresponding to the audio conversion chip, the plug Type of the earphone can be automatically detected.
The embodiment of the invention also provides audio equipment, which comprises the earphone detection circuit in any embodiment. It will be appreciated that the audio device may be any electronic device adapted to a headset/a microphone and having audio playback capabilities, such as a mobile terminal, a notebook computer, a digital television, an MP3/MP4 player, etc.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the invention, the steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. An earphone detection circuit, comprising:
the earphone jack circuit is used for plugging earphones with different plug types;
the first voltage bias circuit is electrically connected with the earphone jack circuit, and a first node is arranged on a connecting path of the first voltage bias circuit and the earphone jack circuit;
the second voltage bias circuit is electrically connected with the earphone jack circuit, and a second node is arranged on a connecting path of the second voltage bias circuit and the earphone jack circuit;
the controller is respectively and electrically connected with the first voltage bias circuit and the second voltage bias circuit, can control the first voltage bias circuit and the second voltage bias circuit to be in different working states, and detects the plug type of the earphone according to node voltages of the first node and the second node in corresponding working states;
the controller is specifically used for:
controlling the first voltage bias circuit and the second voltage bias circuit to be in an enabling state, and configuring node voltages of the first node and the second node to be initial voltages;
controlling the first voltage bias circuit to enter a non-enabled state, controlling the second voltage bias circuit to enter a biased state, configuring the node voltage of the first node from the initial voltage to a first voltage, and configuring the node voltage of the second node from the initial voltage to a second voltage;
and detecting the plug type of the earphone according to the first voltage and the second voltage.
2. The headset detection circuit of claim 1 wherein,
the second voltage bias circuit comprises a clamping circuit and a current source circuit, and the clamping circuit is electrically connected with the current source circuit and is also commonly and electrically connected with the second node;
when the second voltage bias circuit is in an enabling state, the clamping circuit is in an enabling state, and the controller controls the current source circuit to enter a working state so that the second voltage bias circuit enters a bias state;
when the controller controls the first voltage bias circuit to enter a non-enabled state and the second voltage bias circuit enters a biased state, under the combined action of the clamp circuit and the current source circuit, the node voltage of the second node is configured to be a second voltage, and under the action of the clamp circuit, the current source circuit and the resistance values of the earphone jack circuit between the first node and the second node, the node voltage of the first node is configured to be a first voltage.
3. The headset detection circuit of claim 2 wherein,
if the second voltage is equal to the first voltage, the controller detects that the plug type of the earphone is a 3-segment plug type;
and if the second voltage is not equal to the first voltage, the controller further judges the plug type of the earphone.
4. The headset detection circuit of claim 3 wherein,
the earphone jack circuit comprises a left sound channel port, a right sound channel port, a first detection port and a second detection port, wherein the first detection port is electrically connected to the first node, and the second detection port is electrically connected to the second node;
the controller controls the first voltage bias circuit to enter an enabling state again, and further judges the plug type of the earphone according to the left channel voltage of the left channel port and the right channel voltage of the right channel port.
5. The headset detection circuit of claim 4 wherein,
if the left channel voltage and the right channel voltage are respectively equal to the initial voltage, the plug type of the earphone is North America type;
if the left channel voltage and the right channel voltage are respectively equal to the second voltage, the plug type of the earphone is European;
if the left channel voltage and the right channel voltage are equal to zero, respectively, no earphone is inserted into the earphone jack circuit.
6. The headset detection circuit of claim 5 wherein the first circuit further comprises a second circuit configured to detect,
if the left channel voltage and the right channel voltage are equal to the initial voltage respectively, the controller controls the clamping circuit to enter a non-enabling state, and the audio input channel of the earphone is configured;
if the left channel voltage and the right channel voltage are respectively equal to the second voltage, the controller controls the first voltage bias circuit to enter a non-enabling state again, and the audio input channel of the earphone is configured;
and if the left channel voltage and the right channel voltage are equal to zero respectively, the controller controls the current source circuit to enter a non-working state, and the steps of detecting the plug type of the earphone after the controller controls the first voltage bias circuit to enter a non-enabling state and controls the second voltage bias circuit to enter a bias state are repeated.
7. The headphone detection circuit according to any one of claims 1 to 6 further comprising a microphone input circuit electrically connected to the headphone jack circuit and the controller, respectively, for processing audio input signals.
8. The headphone detection circuit according to any one of claims 1 to 6 further comprising an audio output circuit electrically connected to the headphone jack circuit and the controller, respectively, for outputting an audio output signal.
9. A chip comprising the earphone detection circuit according to any one of claims 1 to 8.
10. An audio device comprising a headset detection circuit according to any of claims 1 to 8.
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| CN202111656077.0A CN114189797B (en) | 2021-12-30 | 2021-12-30 | Earphone detection circuit, chip and audio equipment |
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| CN204350278U (en) * | 2015-02-02 | 2015-05-20 | 深圳市吉芯微半导体有限公司 | Communication device |
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| US9031253B2 (en) * | 2011-12-16 | 2015-05-12 | Qualcomm Incorporated | Plug insertion detection |
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| EP1536663A1 (en) * | 2003-11-28 | 2005-06-01 | Freescale Semiconductor, Inc. | Headset interface circuit |
| US9313595B1 (en) * | 2013-09-09 | 2016-04-12 | Marvell International Ltd. | Low-power method and circuitry of determining headphone type and monitoring activity |
| WO2015117374A1 (en) * | 2014-08-18 | 2015-08-13 | 中兴通讯股份有限公司 | Adaptive switching device and method for multi-standard earphone, and terminal |
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