CN114185830A - Multi-processor communication method, device, system and storage medium based on mailbox - Google Patents
Multi-processor communication method, device, system and storage medium based on mailbox Download PDFInfo
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Abstract
The invention discloses a multiprocessor communication method, equipment, a system and a storage medium based on a mailbox, wherein the method comprises the steps of receiving a data packet sent by a processor in a sending state based on the mailbox multiprocessor communication method; if the transmission information of the data packet meets the preset read condition, sending a notification signal to a processor in a receiving state; receiving a reading signal sent by the processor in the receiving state aiming at the notification signal; based on the synchronous FIFO principle, after the reading signal is subjected to metastable state processing, the data packet is sent to the processor in the receiving state, so that data writing and reading in the same clock domain are realized, the conversion between binary codes and Gray codes is avoided, the time sequence delay of cross-clock domain communication is effectively solved, the communication efficiency is improved, and the design complexity is reduced.
Description
Technical Field
The invention belongs to the technical field of instant messaging, and particularly relates to a multiprocessor communication method, equipment, a system and a storage medium based on a mailbox.
Background
With the continuous progress of semiconductor manufacturing processes, in order to satisfy high-end applications such as communication, multimedia, and digital processing, a system on chip has integrated not only one processor but also a plurality of processors into one system, and even needs to work in conjunction with off-chip processors.
At present, a shared Memory communication mechanism, a Direct Memory Access (DMA) data transfer communication mechanism, a serial port master-slave mode communication mechanism, and a Mailbox communication mechanism are mainly used for communication among multiple processors. The shared memory has the advantages of low transmission speed, poor real-time performance and high complexity of corresponding software configuration; although the DMA data carrying communication mechanism can transmit a large amount of data, the real-time performance is poor; the serial port master-slave mode communication mechanism has low speed and poor real-time performance; the Mailbox communication mechanism is a hardware mechanism for communication among multiple processors, and compared with other communication modes, the Mailbox communication mechanism is high in speed, high in real-time performance and overall performance. Therefore, the Mailbox communication mechanism is mostly adopted in the market at present.
However, the Mailbox in the current market is mainly implemented by using asynchronous FIFO, because the address and data belong to two clock domains, and the direct comparison can cause glitches, the address and data need to be synchronized and then compared, because the address and data are all multiple lines, gray codes are used, binary codes are converted into gray codes firstly, then the gray codes are used for transmission, and the gray codes are converted into binary codes for comparison after being synchronized to the same clock domain.
Disclosure of Invention
The invention mainly aims to provide a multiprocessor communication method, equipment, a system and a storage medium based on a mailbox, so as to solve the problem of low communication efficiency in the prior art.
In order to solve the above problems, the present invention provides a multiprocessor communication method based on a mailbox, in which, in any two communicating processors, each processor switches between a sending state and a receiving state, and after the switching state, the following steps are executed by a FIFO memory corresponding to the processor in the sending state in the mailbox:
receiving a data packet sent by a processor in a sending state;
if the transmission information of the data packet meets the preset read condition, sending a notification signal to a processor in a receiving state;
receiving a reading signal sent by the processor in the receiving state aiming at the notification signal;
and based on a synchronous FIFO principle, after carrying out metastable state processing on the read signal, sending the data packet to the processor in a receiving state.
Further, in the above mailbox-based multiprocessor communication method, the transmission information includes a count value of receiving the data packet and/or a timing value of receiving the data packet;
after receiving the data packet sent by the processor in the sending state, the method further comprises:
if the count value reaches a preset count threshold value and/or the timing value reaches a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition;
and if the count value does not reach a preset count threshold value and the timing value does not reach a preset timing threshold value, determining that the transmission information of the data packet does not meet the preset read condition.
Further, in the above mailbox-based multiprocessor communication method, the preset count threshold is a preset fixed value.
Further, in the above mailbox-based multiprocessor communication method, the transmission information includes a count value for receiving the data packet and a timing value for receiving the data packet;
if the count value reaches a preset count threshold and/or the timing value reaches a preset timing threshold, determining that the transmission information of the data packet meets the preset read condition, including:
if the count value reaches the preset fixed value but the timing value does not reach a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition;
and if the count value does not reach the preset fixed value but the timing value reaches a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition.
Further, in the above mailbox-based multiprocessor communication method, the preset count threshold is set according to the following steps:
extracting the data length of the data packet;
and taking a numerical value corresponding to the data length of the data packet as the preset counting threshold value.
Further, in the above mailbox-based multiprocessor communication method, the transmission information includes a count value for receiving the data packet and a timing value for receiving the data packet;
if the count value reaches a preset count threshold and/or the timing value reaches a preset timing threshold, determining that the transmission information of the data packet meets the preset read condition, including:
if the count value reaches the preset count threshold value but the timing value does not reach the preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition;
and if the timing value reaches a preset timing threshold value and the count value reaches the preset count threshold value, determining that the transmission information of the data packet meets the preset read condition.
Further, the above-mentioned mailbox-based multiprocessor communication method further includes:
if the processor in the sending state is detected to send the next data packet and simultaneously the reading signal of the processor in the receiving state is detected, after the data packet is sent to the processor in the receiving state, the next data packet sent by the processor in the sending state is received.
The invention also provides a multiprocessor communication device based on the mailbox, wherein each processor in any two communicating processors is switched between a sending state and a receiving state, and the multiprocessor communication device based on the mailbox comprises:
a communication unit corresponding to each processor, each communication unit comprising:
a register;
the FIFO memory is used for realizing the above mailbox-based multiprocessor communication method based on the configuration information of the register to the FIFO memory;
and the interrupt controller is used for sending the notification signal sent by the FIFO memory to the processor in the receiving state.
The invention also provides a multiprocessor communication system based on the mailbox, which is characterized by comprising at least two processors and the multiprocessor communication device based on the mailbox, wherein the multiprocessor communication device is used for processing the data;
each processor of any two communicating processors is switched between a sending state and a receiving state, and after the switching state, the mailbox-based multiprocessor communication device realizes the mailbox-based multiprocessor communication method.
The present invention also provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a controller, implements the steps of mailbox-based multiprocessor communication as described above.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
after receiving a data packet sent by a processor in a sending state, if transmission information of the data packet meets a preset read condition, sending a notification signal to the processor in a receiving state, receiving a read signal sent by the processor in the receiving state aiming at the notification signal, carrying out metastable state processing on the read signal based on a synchronous FIFO principle, and then sending the data packet to the processor in the receiving state, so that data writing and reading are realized in the same clock domain, conversion between binary codes and Gray codes is avoided, time sequence delay of cross-clock domain communication is effectively solved, communication efficiency is improved, and design complexity is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of an embodiment of a mailbox-based multiprocessor communication method of the present invention;
FIG. 2 is a schematic block diagram illustrating one embodiment of a mailbox-based multiprocessor communication apparatus of the present invention;
fig. 3 is a schematic structural diagram of another embodiment of the mailbox-based multiprocessor communication apparatus according to the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
Example one
In order to solve the above technical problems in the prior art, an embodiment of the present invention provides a multiprocessor communication method based on a mailbox. In any two communicating processors, each processor is switched between a sending state and a receiving state, and after the state is switched, the FIFO memory corresponding to the processor in the sending state in the mailbox realizes data interaction between any two communicating processors.
Fig. 1 is a flowchart of an embodiment of a multiprocessor communication method based on a mailbox in the present invention, and as shown in fig. 1, the multiprocessor communication method based on a mailbox in this embodiment may specifically include the following steps:
100. receiving a data packet sent by a processor in a sending state;
in a specific implementation process, a processor in a sending state in any two communicating processors may package data to be sent, and then send the data package to a FIFO memory corresponding to the processor in the sending state. The transmitted Data packet consists of a Header and a Data part Data, wherein the Header consists of an identifier for distinguishing the Header from the Data part, an identifier for matching a command and a response, an identifier for distinguishing the command or Error, a length for indicating the length of the Data packet, and the like.
101. If the transmission information of the data packet meets the preset read condition, sending a notification signal to a processor in a receiving state;
after receiving the data packet sent by the processor in the sending state, it may be determined whether transmission information of the data packet satisfies a preset condition to be read, that is, whether the data packet satisfies a condition to be read by the processor in the receiving state. If the transmission information of the data packet meets the preset read condition, sending a notification signal to the processor in the receiving state, and if the transmission information of the data packet does not meet the preset read condition, waiting for the data packet to continue to be transmitted until the transmission information of the data packet meets the preset read condition, and sending the notification signal to the processor in the receiving state.
Specifically, the transmission information of the data packet may include a count value of the received data packet and/or a timing value of the received data packet; after receiving the data packet sent by the processor in the sending state, the counter can count to obtain the count value of the received data packet, and/or the timer can count to obtain the timing value of the received data packet. If the count value reaches a preset count threshold value and/or the timing value reaches a preset timing threshold value, determining that the transmission information of the data packet meets a preset read condition; and if the count value does not reach the preset count threshold value and the timing value does not reach the preset timing threshold value, determining that the transmission information of the data packet does not meet the preset read condition.
In this embodiment, the transmission information, which is preferably a packet, may include a count value of a received packet and a timing value of the received packet. The preset counting threshold may be a preset fixed value. Thus, if the count value of the received data packet reaches a preset fixed value but the timing value of the received data packet does not reach a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition; and if the count value of the received data packet does not reach the preset fixed value but the timing value of the received data packet reaches the preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition.
For example, if the total length of the data packet is greater than or equal to a preset fixed value, the count value of the received data packet can inevitably reach the preset fixed value when the data packet is received, and if the count value of the received data packet reaches the preset fixed value first and the timing value of the received data packet does not reach the preset timing threshold, it can still be determined that the transmission information of the data packet satisfies the preset read condition. If the preset timing threshold is relatively short, the timing value of the received data packet reaches the preset timing threshold before the count value of the received data packet reaches the preset fixed value, and it can also be determined that the transmission information of the data packet meets the preset read condition.
If the total length of the data packet is less than the preset fixed value, the situation that the count value of the received data packet reaches the preset fixed value inevitably cannot occur when the data packet is received, that is, the last data of the data packet cannot be triggered to be interrupted by the preset fixed value, and at this time, after the timing value of the received data packet reaches the preset timing threshold value, it can be determined that the transmission information of the data packet meets the preset read condition.
In practical application, the preset counting threshold is configured to be a preset fixed value, the configuration is simple, and the configuration is not required to be changed after one time; however, the flexibility is poor, specifically, when the length of the data packet is greater than a preset fixed value, one packet needs to be transmitted twice or more times, for example, the preset fixed value is generally set at half the depth of the FIFO and is not usually set to the maximum value, that is, as long as the preset fixed value is not set to the maximum value, the utilization rate of the FIFO is not maximized, and therefore, the data transmission efficiency is also low in this manner.
In order to solve the above technical problem, in this embodiment, the preset count threshold may be a value that changes with a change of a data length of the data packet, and specifically, the preset count threshold is set according to the following steps: extracting the data length of the data packet; and taking a numerical value corresponding to the data length of the data packet as a preset counting threshold value.
In this embodiment, the transmission information of the data packet preferably includes a count value of the received data packet and a timing value of the received data packet; thus, if the count value of the received data packet reaches the preset count threshold value but the timing value of the received data packet does not reach the preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition; and if the timing value of the received data packet reaches the preset timing threshold value and the count value of the received data packet reaches the preset count threshold value, determining that the transmission information of the data packet meets the preset read condition.
For example, in order to transmit one or more complete packets, and to avoid that the received packets are incomplete because the timing value of the received packet reaches the preset timing threshold, the embodiment preferably determines that the transmission information of the packet meets the preset read condition by taking that the count value of the received packet reaches the preset count threshold, so that the processor in the receiving state reads the received packet after the complete packet is always received. Therefore, compared with the situation that a fixed value is set as the preset counting threshold value, one data packet does not need to be transmitted for many times, and the data transmission efficiency is improved.
102. Receiving a reading signal sent by the processor in a receiving state aiming at the notification signal;
in this embodiment, the clock of the FIFO of the processor in the transmission state is derived from the clock domain of the write FIFO, and in order to solve the problem that the FIFO read-write pointer crosses the clock domain, and avoid the mutual conversion between the binary code and the gray code, in this embodiment, the clock of the FIFO of the processor in the transmission state is also derived from the clock domain of the write FIFO, and the processor in the transmission state may generate a read signal with respect to the clock domain of the write FIFO with respect to the received notification signal, and may transmit the read signal to the FIFO memory, and the FIFO memory receives the read signal transmitted by the processor in the reception state with respect to the notification signal.
103. Based on the synchronous FIFO principle, after the reading signal is processed in the metastable state, the data packet is sent to the processor in the receiving state.
In this embodiment, the data packet may be sent to the processor in the receiving state after the read signal is processed in the metastable state based on the synchronous FIFO principle. Specifically, the read signal may be clocked into the clock domain of the write FIFO in two beats.
In the embodiment, only one line is needed for synchronization, conversion between binary codes and gray codes is not needed, and compared with a method for synchronizing after mutual conversion between the binary codes and the gray codes is carried out by utilizing multiple tracking lines in an asynchronous FIFO principle, the method has the advantages that the complexity of design is reduced while the communication performance is improved, the time sequence delay of clock domain crossing communication is effectively solved, and further the rear-end design layout is more convenient in layout and wiring, and the transmission speed of the Mailbox is obviously improved.
According to the multiprocessor communication method based on the mailbox, after a data packet sent by a processor in a sending state is received, if transmission information of the data packet meets a preset read condition, a notification signal is sent to the processor in a receiving state, a read signal sent by the processor in the receiving state aiming at the notification signal is received, and the data packet is sent to the processor in the receiving state after the read signal is processed in a metastable state based on a synchronous FIFO principle, so that data writing and reading are realized in the same clock domain, conversion between binary codes and Gray codes is avoided, time delay of cross-clock-domain communication is effectively solved, communication efficiency is improved, and design complexity is reduced.
Further, in the foregoing embodiment, data may be read by a processor in a receiving state while data is written by the processor in a transmitting state, and in order to avoid causing data overflow when the data is written, this embodiment preferably performs processing on a read-first principle, that is, if it is detected that the processor in the transmitting state transmits a next data packet and detects a read signal of the processor in the receiving state, after the data packet is transmitted to the processor in the receiving state, the next data packet transmitted by the processor in the transmitting state is received. In this way, the read priority will read the data packet in the FIFO memory to make room for the FIFO memory so that the processor in the transmit state can continue to write the data packet without causing the FIFO memory to overflow the data.
If the write priority is given, when a processor in a sending state has a large amount of data to be written, the data can be written all the time, and the space of the FIFO memory cannot be released in time, so that the FIFO memory is easy to overflow the data.
It should be noted that the method of the embodiment of the present invention may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In the case of such a distributed scenario, one of the multiple devices may only perform one or more steps of the method according to the embodiment of the present invention, and the multiple devices interact with each other to complete the method.
Example two
In order to solve the above technical problems in the prior art, an embodiment of the present invention provides a mailbox-based multiprocessor communication device, wherein in any two communicating processors, each processor switches between a sending state and a receiving state, and after the state switching is completed, the mailbox-based multiprocessor communication device implements data interaction between the two processors.
Fig. 2 is a schematic structural diagram of an embodiment of the mailbox-based multiprocessor communication device according to the present invention, and as shown in fig. 2, the mailbox-based multiprocessor communication device of the present embodiment includes a communication unit 20 corresponding to each processor 10, and each communication unit 20 includes a register 201, a FIFO memory 202, and an interrupt controller 203. In which fig. 2 illustrates the technical solution of the present invention by taking two processors 10 as an example.
A register 201 for configuring the FIFO memory 202.
The FIFO memory 202 is used for realizing the communication method of the multiprocessor 10 based on the mailbox in the embodiment based on the configuration information of the register 201 to the FIFO memory 202;
and an interrupt controller 203 for sending the notification signal sent from the FIFO memory 202 to the processor 10 in the receiving state.
Fig. 3 is a schematic structural diagram of another embodiment of the mailbox-based multiprocessor communication device according to the present invention, and fig. 3 illustrates a technical solution of the present invention by taking two processors as an example. As shown in fig. 3, the mailbox-based multiprocessor communication device of this embodiment may include a host interface AHB1, a host register Master reg. The main FIFO memory may include a main control module FIFO _ CTRL1, a main storage module CMD _ FIFO1, and a main synchronization module. Slave processor interface AHB2, Slave register Slave reg.file, Slave FIFO memory, Slave interrupt controller Slave int.handle corresponding to the Slave processor. The slave FIFO memory may comprise a slave control module FIFO _ CTRL2, a slave storage module RSPS _ FIFO, and a slave synchronization module Sync 2.
In this embodiment, the host processor interface AHB1, the Master register Master reg.file, the Master control module FIFO _ CTRL1, the Master storage module CMD _ FIFO1, the Master synchronization module, and the Slave interrupt controller Slave int.handle form a communication unit corresponding to the host processor. The Slave processor interface AHB2, the Slave register Slave re.file, the Slave control module FIFO _ CTRL2, the Slave storage module RSPS _ FIFO, the Slave synchronization module Sync2 and the Master interrupt controller Master int.handle form a communication unit corresponding to the Slave processor.
11. Main processor interface AHB 1: an interface to a host processor; slave interface AHB2, interface with slave's AHB bus.
12. File: this register set is accessible by the master processor, which cannot be accessed directly by the slave processor, and the master processor needs to configure the Mailbox via the register set and simultaneously needs to access the corresponding interrupt status via the register set.
13. File from register Slave reg: this register set is accessible by the slave processor, which is not directly accessible by the master processor, and the slave processor needs to access the corresponding interrupt state through this register set.
14. Master control module FIFO _ CTRL1 and slave control module FIFO _ CTRL 2: the controller is used for controlling the data reading and writing of the two FIFOs, and the change of the reading and writing pointers in the FIFOs, the comparison of the reading and writing pointers, the change of the counter and the like are all controlled by the two control modules. The problem of read-write priority sequence is also controlled by the two control modules, in the design, the read priority is adopted, namely when the read-write occurs simultaneously, the FIFO reads data preferentially, and the write operation is carried out after the read operation is finished.
15. Main memory module CMD _ FIFO 1: the module is characterized in that a master processor sends a command packet or a parameter packet to a FIFO of a slave processor, the master processor stores packaged data into a CMD _ FIFO of a master storage module, and then the slave processor is informed to read a data packet from the CMD _ FIFO of the master storage module.
16. From the memory module RSPS _ FIFO: the module stores the returned response after the slave processor executes the command, packs the response and puts the response into the slave storage module RSPS _ FIFO after the slave processor executes the command, and then informs the master processor to read the response from the slave storage module RSPS _ FIFO.
17. Master interrupt controller Master int. The module performs AND operation on an interrupt state bit transmitted from the slave processor and a corresponding enable bit, and then throws an interrupt signal (namely a notification signal) to the master processor.
18. Slave interrupt controller Slave int. handle: the module performs AND operation on an interrupt state bit transmitted by the master processor and a corresponding enable bit, and then throws an interrupt signal (namely a notification signal) to the slave processor.
19. Master Sync1 and Slave Sync 2: the module is a synchronous module, and because the clock domain of the read signal is not the clock domain of the write signal, when the receiving side needs to read data from the corresponding storage module, the read signal needs to be sent first, and then the data can be read only after being synchronized to the corresponding clock domain by the master synchronization module Sync1 or the slave synchronization module Sync 2.
The apparatus of the foregoing embodiment is used to implement the corresponding method in the foregoing embodiment, and has the beneficial effects of the corresponding method embodiment, which are not described herein again.
EXAMPLE III
In order to solve the above technical problems in the prior art, an embodiment of the present invention provides a multiprocessor communication system based on a mailbox.
The multiprocessor communication system based on the mailbox of the embodiment comprises at least two processors and the multiprocessor communication device based on the mailbox;
each of the two communicating processors is switched between a transmission state and a reception state, and after the switching state, the mailbox-based multiprocessor communication method of the above-described embodiment is implemented by the mailbox-based multiprocessor communication apparatus.
Example four
In order to solve the above technical problems in the prior art, embodiments of the present invention provide a storage medium.
The storage medium provided by the embodiment of the invention is stored with a computer program, and the computer program realizes the steps of the mailbox-based multiprocessor communication of the embodiment when being executed by a processor.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A multiprocessor communication method based on a mailbox, characterized in that, in any two communicating processors, each processor switches between a sending state and a receiving state, and after the switching state, the following steps are executed by a FIFO memory corresponding to the processor in the sending state in the mailbox:
receiving a data packet sent by a processor in a sending state;
if the transmission information of the data packet meets the preset read condition, sending a notification signal to a processor in a receiving state;
receiving a reading signal sent by the processor in the receiving state aiming at the notification signal;
and based on a synchronous FIFO principle, after carrying out metastable state processing on the read signal, sending the data packet to the processor in a receiving state.
2. A mailbox-based multiprocessor communication method as claimed in claim 1, wherein the transfer information includes a count value of receiving the data packet and/or a timing value of receiving the data packet;
after receiving the data packet sent by the processor in the sending state, the method further comprises:
if the count value reaches a preset count threshold value and/or the timing value reaches a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition;
and if the count value does not reach a preset count threshold value and the timing value does not reach a preset timing threshold value, determining that the transmission information of the data packet does not meet the preset read condition.
3. The mailbox-based multiprocessor communication method as claimed in claim 2, wherein the preset count threshold is a fixed value set in advance.
4. The mailbox-based multiprocessor communication method as claimed in claim 3, wherein the transmission information includes a count value for receiving the data packet and a timing value for receiving the data packet;
if the count value reaches a preset count threshold and/or the timing value reaches a preset timing threshold, determining that the transmission information of the data packet meets the preset read condition, including:
if the count value reaches the preset fixed value but the timing value does not reach a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition;
and if the count value does not reach the preset fixed value but the timing value reaches a preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition.
5. The mailbox-based multiprocessor communication method as claimed in claim 2, wherein the preset count threshold is set according to the following steps:
extracting the data length of the data packet;
and taking a numerical value corresponding to the data length of the data packet as the preset counting threshold value.
6. The mailbox-based multiprocessor communication method as claimed in claim 5, wherein the transmission information includes a count value for receiving the data packet and a timing value for receiving the data packet;
if the count value reaches a preset count threshold and/or the timing value reaches a preset timing threshold, determining that the transmission information of the data packet meets the preset read condition, including:
if the count value reaches the preset count threshold value but the timing value does not reach the preset timing threshold value, determining that the transmission information of the data packet meets the preset read condition;
and if the timing value reaches a preset timing threshold value and the count value reaches the preset count threshold value, determining that the transmission information of the data packet meets the preset read condition.
7. The mailbox-based multiprocessor communication method as claimed in claim 1, further comprising:
if the processor in the sending state is detected to send the next data packet and simultaneously the reading signal of the processor in the receiving state is detected, after the data packet is sent to the processor in the receiving state, the next data packet sent by the processor in the sending state is received.
8. A mailbox-based multiprocessor communication apparatus, wherein each of any two communicating processors switches between a sending state and a receiving state, the mailbox-based multiprocessor communication apparatus comprising:
a communication unit corresponding to each processor, each communication unit comprising:
a register;
a FIFO memory for implementing the mailbox-based multiprocessor communication method according to any one of claims 1 to 7, based on configuration information of the register to the FIFO memory;
and the interrupt controller is used for sending the notification signal sent by the FIFO memory to the processor in the receiving state.
9. A mailbox-based multiprocessor communication system, characterized in that it comprises at least two processors and a mailbox-based multiprocessor communication device as claimed in claim 8;
any two communicating processors, each processor switching between a sending state and a receiving state, and after switching the states, implementing by the mailbox-based multiprocessor communication device a mailbox-based multiprocessor communication method as claimed in any one of claims 1 to 7.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a controller, performs the steps of the mailbox-based multiprocessor communication according to any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116662248A (en) * | 2023-05-12 | 2023-08-29 | 珠海妙存科技有限公司 | Multi-CPU communication system and method, electronic device, and storage medium |
| KR102606224B1 (en) * | 2023-05-25 | 2023-11-29 | 메티스엑스 주식회사 | Electronic device including hardware architecture for supporting inter-process communication and method for performing inter-process communication |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116662248A (en) * | 2023-05-12 | 2023-08-29 | 珠海妙存科技有限公司 | Multi-CPU communication system and method, electronic device, and storage medium |
| KR102606224B1 (en) * | 2023-05-25 | 2023-11-29 | 메티스엑스 주식회사 | Electronic device including hardware architecture for supporting inter-process communication and method for performing inter-process communication |
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