CN114095960B

CN114095960B - Processing method, communication device, and storage medium

Info

Publication number: CN114095960B
Application number: CN202210007414.1A
Authority: CN
Inventors: 朱荣昌; 黄伟; 黄钧蔚
Original assignee: Shenzhen Transsion Holdings Co Ltd
Current assignee: Shenzhen Transsion Holdings Co Ltd
Priority date: 2022-01-06
Filing date: 2022-01-06
Publication date: 2022-07-08
Anticipated expiration: 2042-01-06
Also published as: WO2023130954A1; CN114095960A

Abstract

The application provides a processing method, a communication device and a storage medium, wherein the method comprises the following steps: and calculating or determining a delay budget result of the logical channel according to the delay budget value, wherein the delay budget result is used for indicating whether the cache delay of the data in the logical channel meets the delay budget or not. Then, the PBR of the logical channel is adjusted according to the delay budget result, and after the PBR of the logical channel is adjusted, the air interface resource obtained by the logical channel can be changed, so as to change the transmission rate of the data in the logical channel, and further change the buffer delay of the data in the logical channel. According to the scheme, the buffer delay of the data in the logic channel is controlled by dynamically adjusting the PBR of the logic channel.

Description

Processing method, communication device, and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a processing method, a communication device, and a storage medium.

Background

In some implementations, the terminal device may determine, based on an uplink transmission resource configured by the network device, a transmission Data amount of each logical channel in a media Access Control Packet Data Unit (MAC PDU for short).

In the course of conceiving and implementing the present application, the inventors found that at least the following problems existed: in order to realize multiplexing of uplink logical channels, a Radio Resource Control (RRC) configures the following parameters for each uplink logical channel: logical channel priority (priority): the smaller the value of the priority is, the higher the priority of the corresponding logical channel is; PBR: a priority bit rate indicating a minimum rate that the logical channel needs to guarantee; token Bucket Duration (BSD): this parameter determines the depth of the token bucket.

When the air interface capability is limited, the actual rate of data transmission on the logical channel may be reduced, and at this time, the buffering delay from the beginning of buffering the data on the logical channel to the transmission through the logical channel is large. At present, no corresponding scheme is available for solving the problem of how to control the cache delay of data in a logical channel under the condition of limited air interface capability.

The foregoing description is provided for general background information and is not admitted to be prior art.

Disclosure of Invention

The present application provides a processing method, a communication device and a storage medium to solve the above technical problems.

In a first aspect, the present application provides a processing method, applicable to a communication device such as a terminal device or a network device, including the following steps:

s1, calculating or determining the delay budget result of the logic channel according to the delay budget value;

and S2, adjusting the priority bit rate of the logic channel according to the delay budget result.

Optionally, the step of S1 includes:

and calculating or determining the delay budget result according to the actual data transmission rate and/or the buffer data volume of the logical channel in the first time length and the delay budget value.

Optionally, the delay budget result includes at least one of:

the buffering delay of the data in the logical channel does not meet the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is less than or equal to the current priority bit rate, and the cache data volume is greater than or equal to the product of the current priority bit rate and the first duration; the amount of the cache data is larger than or equal to the product of the actual speed and the delay budget value; the cache data amount is larger than or equal to the product of the actual speed, the delay budget value and a first threshold value;

the buffering delay of the data in the logical channel meets the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is greater than the current priority bit rate; the cache data amount is less than the product of the current priority bit rate and the first duration; the cache data volume is smaller than the product of the actual speed and the delay budget value; the amount of the buffered data is smaller than the product of the actual speed, the delay budget value and the first threshold value.

Optionally, the step S2 includes:

and adjusting the priority bit rate of the logic channel to be a target priority bit rate according to the delay budget result.

Optionally, the target priority bit rate is at least one of:

a current priority bit rate;

an initial priority bit rate;

the quotient of the buffer data volume and the delay budget value;

a product of the current priority bit rate and a second threshold, the second threshold being a positive number.

Optionally, the buffering delay of the data in the logical channel does not meet the delay budget, and the target priority bit rate is greater than or equal to the current priority bit rate; and/or the presence of a gas in the gas,

the buffer delay of the data in the logic channel meets the delay budget, and the target priority bit rate is smaller than or equal to the current priority bit rate.

Optionally, the buffering delay of the data in the logical channel does not satisfy the delay budget, and includes at least one of:

the target priority bit rate is at least one of: the current priority bit rate, the quotient of the cache data volume and the delay budget value, and the product of the current priority bit rate and the second threshold value, wherein the second threshold value is a positive number greater than or equal to 1;

when the current priority bit rate is smaller than the quotient of the cache data volume and the delay budget value, the target priority bit rate is the quotient of the cache data volume and the delay budget value;

and when the current priority bit rate is greater than or equal to the quotient of the cache data volume and the delay budget value, the target priority bit rate is the current priority bit rate.

When the current priority bit rate is less than a priority bit rate threshold value, the target priority bit rate is the product of the current priority bit rate and the second threshold value;

when the current priority bit rate is greater than or equal to the priority bit rate threshold value, the target priority bit rate is the current priority bit rate.

Optionally, the priority bit rate threshold is a quotient of the buffered data amount and the delay budget value; alternatively, the priority bit rate threshold is a third threshold.

Optionally, the buffering delay of the data in the logical channel meets the delay budget, which includes at least one of:

the target priority bit rate is at least one of: the current priority bit rate, the initial priority bit rate, a product of the current priority bit rate and the second threshold, the second threshold being a positive number less than or equal to 1.

When the current priority bit rate is less than or equal to the initial priority bit rate, the target priority bit rate is the current priority bit rate;

when the current priority bit rate is greater than or equal to the initial priority bit rate, the target priority bit rate is a product of the current priority bit rate and a third threshold.

In a second aspect, the present application provides a processing method, applicable to a communication device such as a terminal device or a network device, including the following steps:

and S10, responding to the time delay budget result of the logical channel meeting the preset condition, and adjusting the priority bit rate of the logical channel.

Optionally, the time delay budget result meeting the preset condition includes at least one of:

the buffer delay of the data in the logical channel does not meet the delay budget, and the actual rate and/or the buffer data amount of the data transmission of the logical channel in the first duration meet at least one of the following conditions: the actual rate is less than or equal to the current priority bit rate, the cache data amount is greater than or equal to the product of the current priority bit rate and the first duration, the cache data amount is greater than or equal to the product of the actual rate and the delay budget value, the cache data amount is greater than or equal to the product of the actual rate, the delay budget value and a first threshold value;

the buffering delay of the data in the logical channel meets the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is greater than the current priority bit rate, the amount of the buffered data is less than the product of the current priority bit rate and the first duration, the amount of the buffered data is less than the product of the actual rate and the delay budget, and the amount of the buffered data is less than the product of the actual rate, the delay budget and the first threshold.

Optionally, the adjusting the priority bit rate of the logical channel includes:

and adjusting the priority bit rate of the logical channel to be the target priority bit rate.

Optionally, the target priority bit rate is at least one of:

a current priority bit rate;

an initial priority bit rate;

the quotient of the buffer data volume and the delay budget value;

and the cache delay of the data in the logic channel meets the delay budget, and the target priority bit rate is less than or equal to the current priority bit rate.

the target priority bit rate is at least one of: the current priority bit rate, the quotient of the cache data amount and the delay budget value, and the product of the current priority bit rate and the second threshold value, wherein the second threshold value is a positive number greater than or equal to 1;

When the current priority bit rate is less than a priority bit rate threshold, the target priority bit rate is the product of the current priority bit rate and the second threshold;

In a third aspect, the present application provides a processing apparatus comprising:

the processing module is used for calculating or determining a delay budget result of the logic channel according to the delay budget value;

and the adjusting module is used for adjusting the priority bit rate of the logic channel according to the delay budget result.

In a fourth aspect, the present application provides a processing apparatus comprising:

and the processing module is used for responding to the time delay budget result of the logical channel to meet the preset condition and adjusting the priority bit rate of the logical channel.

In a fifth aspect, the present application provides a communication device, comprising: a memory and a processor;

the memory is to store program instructions;

the processor is configured to invoke program instructions in the memory to perform the processing method of any of the first or second aspects.

In a sixth aspect, the present application provides a computer readable storage medium having a computer program stored thereon; the computer program, when executed, implements a processing method as set forth in any one of the first or second aspects.

According to the processing method, the communication device and the storage medium provided by the application, firstly, a delay budget result of a logical channel is determined according to a delay budget value, and the delay budget result is used for indicating whether the cache delay of data in the logical channel meets the delay budget or not. And then, adjusting the PBR of the logical channel according to the delay budget result, and after adjusting the PBR of the logical channel, changing the air interface resource obtained by the logical channel, thereby changing the transmission rate of the data in the logical channel and further changing the cache delay of the data in the logical channel. According to the scheme, the buffer delay of the data in the logic channel is controlled by dynamically adjusting the PBR of the logic channel.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic diagram of a hardware structure of a terminal device according to an embodiment of the present disclosure;

fig. 2 is a diagram illustrating a communication network system architecture according to an embodiment of the present application;

fig. 3 is a first schematic flow chart of a processing method according to an embodiment of the present disclosure;

fig. 4 is a schematic flowchart of adjusting the PBR of a logical channel according to an embodiment of the present disclosure;

fig. 5 is a second flowchart illustrating a processing method according to an embodiment of the present application;

FIG. 6 is a first schematic view of PBR adjustment provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a PBR adjustment scheme II according to an embodiment of the present application;

FIG. 8 is a third schematic view of PBR adjustment provided by the present application;

fig. 9 is a first schematic structural diagram of a processing apparatus according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a processing apparatus according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a communication device according to an embodiment of the present application.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. The drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the statement that an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the processes, methods, articles, or apparatuses that comprise the element, and that elements, features, or elements having the same designation in different embodiments of the application may or may not have the same meaning as that of the other elements in the embodiment illustrated and/or described in further detail in connection with the context of that embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or," "and/or," "including at least one of the following," and the like, as used herein, are to be construed as inclusive or mean any one or any combination. For example, "includes at least one of: A. b, C "means" any of the following: a; b; c; a and B; a and C; b and C; a and B and C ", again for example," A, B or C "or" A, B and/or C "means" any of the following: a; b; c; a and B; a and C; b and C; a and B and C'. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.

It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or at least partially with respect to other steps or sub-steps of other steps.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.

It should be noted that step numbers such as S1 and S2 are used herein for the purpose of more clearly and briefly describing the corresponding contents, and do not constitute a substantial limitation on the sequence, and those skilled in the art may perform S2 first and then perform S1 in the specific implementation, which should be within the scope of the present application.

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.

The terminal device may be a smart terminal, which may be implemented in various forms. For example, the smart terminal described in the present application may include smart terminals such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and fixed terminals such as a Digital TV, a desktop computer, and the like.

In the following description, a terminal device will be exemplified, and it will be understood by those skilled in the art that the configuration according to the embodiment of the present application can be applied to a fixed type terminal in addition to elements particularly used for moving purposes.

Referring to fig. 1, which is a schematic diagram of a hardware structure of a terminal device for implementing various embodiments of the present application, the terminal device 100 may include: RF (Radio Frequency) unit 101, WiFi module 102, audio output unit 103, a/V (audio/video) input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, processor 110, and power supply 111. Those skilled in the art will appreciate that the terminal device architecture shown in fig. 1 is not intended to be limiting, and that the terminal device may include more or fewer components than shown, or some of the components may be combined, or a different arrangement of components.

The following describes each component of the terminal device in detail with reference to fig. 1:

the radio frequency unit 101 may be configured to receive and transmit signals during information transmission and reception or during a call, and optionally, receive downlink information of a base station and then process the downlink information to the processor 110; in addition, the uplink data is transmitted to the base station. Typically, radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 can also communicate with a network and other devices through wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to GSM (Global System for Mobile communications), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000 ), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division duplex-Long Term Evolution), TDD-LTE (Time Division duplex-Long Term Evolution, Time Division Long Term Evolution), 5G, and so on.

WiFi belongs to short-distance wireless transmission technology, and terminal equipment can help a user to receive and send e-mails, browse webpages, access streaming media and the like through the WiFi module 102, and provides wireless broadband internet access for the user. Although fig. 1 shows the WiFi module 102, it is understood that it does not belong to the essential constitution of the terminal device, and may be omitted entirely as needed within the scope not changing the essence of the invention.

The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into an audio signal and output as sound when the terminal device 100 is in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, or the like. Also, the audio output unit 103 may also provide audio output related to a specific function performed by the terminal device 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 may include a speaker, a buzzer, and the like.

The a/V input unit 104 is for receiving an audio or video signal. The a/V input Unit 104 may include a Graphics Processing Unit (GPU) 1041 and a microphone 1042, the Graphics processor 1041 Processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the graphic processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 may receive sounds (audio data) via the microphone 1042 in a phone call mode, a recording mode, a voice recognition mode, or the like, and may be capable of processing such sounds into audio data. The processed audio (voice) data may be converted into a format output transmittable to a mobile communication base station via the radio frequency unit 101 in case of a phone call mode. The microphone 1042 may implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the course of receiving and transmitting audio signals.

The terminal device 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Optionally, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display panel 1061 according to the brightness of ambient light, and the proximity sensor may turn off the display panel 1061 and/or the backlight when the terminal device 100 moves to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone, further description is omitted here.

The display unit 106 is used to display information input by a user or information provided to the user. The Display unit 106 may include a Display panel 1061, and the Display panel 1061 may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 107 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the terminal device. Alternatively, the user input unit 107 may include a touch panel 1071 and other input devices 1072. The touch panel 1071, also referred to as a touch screen, may collect a touch operation performed by a user on or near the touch panel 1071 (e.g., an operation performed by the user on or near the touch panel 1071 using a finger, a stylus, or any other suitable object or accessory), and drive a corresponding connection device according to a predetermined program. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Optionally, the touch detection device detects a touch orientation of a user, detects a signal caused by a touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 110, and can receive and execute commands sent by the processor 110. In addition, the touch panel 1071 may be implemented in various types, such as a resistive type, a capacitive type, an infrared ray, and a surface acoustic wave. The user input unit 107 may include other input devices 1072 in addition to the touch panel 1071. Optionally, other input devices 1072 may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like, and are not limited thereto.

Alternatively, the touch panel 1071 may cover the display panel 1061, and when the touch panel 1071 detects a touch operation thereon or nearby, the touch panel 1071 transmits the touch operation to the processor 110 to determine the type of the touch event, and then the processor 110 provides a corresponding visual output on the display panel 1061 according to the type of the touch event. Although in fig. 1, the touch panel 1071 and the display panel 1061 are two independent components to implement the input and output functions of the terminal device, in some embodiments, the touch panel 1071 and the display panel 1061 may be integrated to implement the input and output functions of the terminal device, and is not limited herein.

The interface unit 108 serves as an interface through which at least one external device is connected to the terminal apparatus 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the terminal apparatus 100 or may be used to transmit data between the terminal apparatus 100 and the external device.

The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a program storage area and a data storage area, and optionally, the program storage area may store an operating system, an application program required for at least one function (such as a sound playing function, an image playing function, and the like), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, etc. Further, the memory 109 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The processor 110 is a control center of the terminal device, connects various parts of the entire terminal device by using various interfaces and lines, and performs various functions of the terminal device and processes data by running or executing software programs and/or modules stored in the memory 109 and calling data stored in the memory 109, thereby performing overall monitoring of the terminal device. Processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor and a modem processor, optionally, the application processor mainly handles operating systems, user interfaces, application programs, etc., and the modem processor mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The terminal device 100 may further include a power supply 111 (such as a battery) for supplying power to each component, and preferably, the power supply 111 may be logically connected to the processor 110 through a power management system, so as to implement functions of managing charging, discharging, and power consumption through the power management system.

Although not shown in fig. 1, the terminal device 100 may further include a bluetooth module or the like, which is not described herein.

In order to facilitate understanding of the embodiments of the present application, a communication network system on which the terminal device of the present application is based is described below.

Referring to fig. 2, fig. 2 is an architecture diagram of a communication Network system according to an embodiment of the present disclosure, where the communication Network system is an LTE system of a universal mobile telecommunications technology, and the LTE system includes a UE (User Equipment) 201, an E-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an EPC (Evolved Packet Core) 203, and an IP service 204 of an operator, which are in communication connection in sequence.

Optionally, the UE201 may be the terminal device 100 described above, and details are not described here.

The E-UTRAN202 includes eNodeB2021 and other eNodeBs 2022, among others. Alternatively, the eNodeB2021 may be connected with other enodebs 2022 through a backhaul (e.g., X2 interface), the eNodeB2021 is connected to the EPC203, and the eNodeB2021 may provide the UE201 access to the EPC 203.

The EPC203 may include an MME (Mobility Management Entity) 2031, an HSS (Home Subscriber Server) 2032, other MMEs 2033, an SGW (Serving gateway) 2034, a PGW (PDN gateway) 2035, and a PCRF (Policy and Charging Rules Function) 2036, and the like. Optionally, the MME2031 is a control node that handles signaling between the UE201 and the EPC203, providing bearer and connection management. HSS2032 is used to provide registers to manage functions such as home location register (not shown) and holds subscriber specific information about service characteristics, data rates, etc. All user data may be sent through SGW2034, PGW2035 may provide IP address assignment for UE201 and other functions, and PCRF2036 is a policy and charging control policy decision point for traffic data flow and IP bearer resources, which selects and provides available policy and charging control decisions for a policy and charging enforcement function (not shown).

The IP services 204 may include the internet, intranets, IMS (IP Multimedia Subsystem), or other IP services, among others.

Although the LTE system is described as an example, it should be understood by those skilled in the art that the present application is not limited to the LTE system, but may also be applied to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, and future new network systems (e.g. 5G), and the like.

Based on the above hardware structure of the terminal device and the communication network system, various embodiments of the present application are provided.

Fig. 3 is a first schematic flowchart of a processing method provided in an embodiment of the present application, where a main body for executing the processing method is a terminal device (e.g., a UE) in this embodiment for example, and in an actual implementation, the processing method may also be executed by a network device, as shown in fig. 3, where the method includes:

and S31, calculating or determining the delay budget result of the logic channel according to the delay budget value.

In 5G NR, the network allocates uplink transmission resources on a per UE basis rather than on a per-bearer basis, and it is determined by the UE which radio bearers whose data can be put in the allocated uplink transmission resources for transmission. Based on the uplink transmission resources configured by the network, the UE needs to determine the transmission Data amount of each logical channel in the primary media Access Control Packet Data Unit (MAC PDU), and in some cases, the UE needs to allocate resources for a MAC Control Element (MAC CE). In order to realize multiplexing of uplink Logical Channels (LCHs), a priority needs to be assigned to each uplink Logical Channel. For a MAC PDU with a given size, under the condition that a plurality of uplink logical channels have data transmission requirements at the same time, resources of the MAC PDU are sequentially distributed according to the descending order of the logical channel priority corresponding to each uplink logical channel. Meanwhile, in order to take fairness among different logical channels into account, probability of Prioritized Bit Rate (PBR) is introduced, and when the UE multiplexes logical channels, it is necessary to first ensure a minimum data Rate requirement of each logical channel, so as to avoid that uplink logical channels with high priority always occupy uplink resources allocated to the UE by the network, which causes other uplink logical channels with low priority of the UE to be starved.

In order to realize multiplexing of the uplink logical channels, the network radio resource control configures the following parameters for each uplink logical channel:

logical channel priority (priority): the smaller the value of the priority is, the higher the priority of the corresponding logical channel is;

PBR: a priority bit rate indicating a minimum rate that the logical channel needs to guarantee;

token bucket duration BSD: this parameter determines the depth of the token bucket.

The MAC of the UE uses a token bucket mechanism to implement uplink logical channel multiplexing. The UE maintains a variable Bj for each uplink logical channel j, which indicates the number of tokens currently available in the token bucket. Optionally, when the UE establishes the logical channel j, initializing Bj to 0; before each Logical Channel Priority (LCP) processing procedure, the UE increases Bj by PBR × T, where T is a time interval from a time of increasing Bj last time to a current time; if Bj updated according to the above steps is greater than the maximum capacity of the token bucket (i.e., PBR BSD), Bj is set to the maximum capacity of the token bucket.

When the UE receives an uplink grant (UL grant) indicating new transmission, the UE performs logical channel priority processing according to the following steps:

1: for all logical channels with Bj >0, allocating resources according to the sequence from high priority to low priority, where the resource allocated to each logical channel can only meet the PBR requirement, that is, allocating resources for the logical channel according to the number of tokens in the PBR token bucket corresponding to the logical channel. When the PBR of a certain logical channel is set to infinity, a logical channel with a lower priority than that of the logical channel is considered only when the resources of the logical channel are satisfied.

2: the size of all MAC SDUs multiplexed into the MAC PDU by the logical channel j subtracted from Bj in S1.

3: if there are remaining uplink resources after the execution of S1 and S2, the remaining resources are sequentially allocated to the respective logical channels in the order of logical channel priority from high to low regardless of the size of Bj. Only when the data of the logical channel with high priority is transmitted and the UL grant is not exhausted, the logical channel with low priority can be served. I.e. when the UE maximizes data transmission for the logical channel of high priority.

When the air interface capability is limited, the data transmission rate in the logical channel depends on the air interface rate, and thus the data transmission rate in the logical channel is correspondingly limited. The buffering delay of data in the logical channel refers to the time length from buffering to the logical channel until the transmission from the logical channel is completed, and when the data transmission rate in the logical channel is limited, the buffering delay of data in the logical channel is also increased.

In order to control the buffering delay of data in the logical channel, a delay budget value (delay budget value) may be set for the logical channel to implement dynamic adjustment of the buffering delay, thereby achieving the purpose of delay control.

Optionally, when the logical channel is configured with the delay budget value, the buffering delay of the data in the logical channel may be controlled based on the delay budget value.

Optionally, when the logical channel is not configured with the delay budget value, the buffering delay of the data in the logical channel is not guaranteed.

Optionally, the delay budget value is configured for the terminal device by the network device.

The terminal device can calculate or determine a delay budget result of the logical channel according to the delay budget value, and the delay budget result is used for indicating whether the cache delay of the data in the logical channel meets the delay budget.

And S32, adjusting the priority bit rate of the logic channel according to the delay budget result.

The buffering delay of the data in the logical channel may or may not meet the delay budget. When the cache delay of the data in the logical channel meets the delay budget, it indicates that the cache delay of the data in the logical channel is small, and at this time, the PBR of the logical channel may not be adjusted, or the PBR of the logical channel may be adjusted to be small, so that more air interface resources are allocated to other logical channels with higher requirements on the delay budget.

When the buffering delay of the data in the logical channel does not meet the delay budget, the buffering delay of the data in the logical channel is larger, and at this time, the PBR of the logical channel can be increased, so that more resources can be allocated to the logical channel, and the buffering delay of the data in the logical channel is reduced.

First, a scheme for determining a delay budget result of a logical channel is described.

Fig. 4 is a schematic flowchart of adjusting the PBR of a logical channel according to an embodiment of the present application, and as shown in fig. 4, the method includes:

and S41, determining that the logical channel is configured with the parameter delay budget value.

S42, determine whether the timer reaches the first time length, if yes, execute S43.

Optionally, the first duration is a duration configured by the network device, and the first duration is a duration of the timer.

Optionally, PBR is periodically adjusted according to the first time period.

And S43, obtaining the delay budget result of the logic channel.

Optionally, the actual rate and/or the amount of the buffered data of the data transmission of the logical channel in the first duration are obtained, and then the delay budget result is calculated or determined according to the actual rate and/or the amount of the buffered data and the delay budget value.

The actual rate is the transmission rate of the data in the logical channel in the first time period, and since the data transmission rate in the logical channel is dynamically changed, the actual rate can be obtained in various ways.

One possible way is to obtain the amount of data transmitted in the logical channel in the first time period, and then determine the actual rate according to the amount of data transmitted in the logical channel in the first time period and the first time period, i.e. v = L/t, v is the actual rate, L is the amount of data transmitted in the logical channel in the first time period, and t is the first time period.

One possible implementation is to determine the actual rate by a sliding window average or a filtered average. For example, the data transmission rates of the logical channel at N times within the first duration may be obtained, and then the N data transmission rates are averaged to obtain the actual rate. For example, the data transmission rates of the logical channels in M periods within the first duration may be obtained, and then the actual rates may be obtained by averaging the M data transmission rates.

The buffer data size is the size of the data newly buffered to the logical channel in the first time duration, taking the time duration between t1 and t2 as an example, the data newly buffered to the logical channel in the time duration between t1 and t2 is the buffer data, and the size of the data newly buffered to the logical channel is the buffer data size.

After obtaining the actual rate and/or the amount of buffered data, the delay budget result of the logical channel may be determined as follows.

Method 1.1: and judging whether the actual rate is less than or equal to the current PBR or not, and the cache data amount is greater than or equal to the product of the current PBR and the first time length.

If yes, determining that the delay budget result is that the cache delay of the data in the logic channel does not meet the delay budget.

And/or if not, namely the actual rate is greater than the current PBR, or the cache data volume is less than the product of the current PBR and the first duration, determining the delay budget result as that the cache delay of the data in the logic channel meets the delay budget.

Method 1.2: judging whether the cache data volume is larger than or equal to the product of the actual speed and the delay budget value, if so, determining the delay budget result that the cache delay of the data in the logic channel does not meet the delay budget; and/or if not, determining that the delay budget result is that the cache delay of the data in the logic channel meets the delay budget.

Method 1.3: judging whether the cache data volume is greater than or equal to the product of the actual speed, the delay budget value and the first threshold value, if so, determining that the delay budget result is that the cache delay of the data in the logic channel does not meet the delay budget; and/or if not, determining that the delay budget result is that the cache delay of the data in the logic channel meets the delay budget.

Alternatively, the first threshold is a value greater than or equal to 0, and may be, for example, 80%, 90%, or the like.

Optionally, the first threshold may be configured for the terminal device by the network device, and may also be configured by the terminal device.

And S44, adjusting the PBR of the logical channel to be the target PBR.

After the delay budget result of the logical channel is obtained, the PBR can be adjusted to be the target PBR according to the delay budget result.

Optionally, when the delay budget result is that the buffer delay of the data in the logical channel does not meet the delay budget, the target PBR is greater than or equal to the current PBR, that is, when the delay budget result is not met, the PBR of the logical channel is increased, so that the logical channel acquires more air interface resources, the transmission rate of the data in the logical channel is increased, and the buffer delay of the data in the logical channel is further reduced.

Alternatively, when the buffering delay of the data in the logical channel does not meet the delay budget, the PBR of the logical channel may be adjusted as follows:

method 2.1: if the current PBR is smaller than the quotient of the cache data volume and the delay budget value, adjusting the current PBR to be the quotient of the cache data volume and the delay budget value, namely target PBR = cache data volume/delay budget value; and/or if the current PBR is greater than or equal to the quotient of the buffer data volume and the delay budget value, not adjusting the current PBR, i.e. the target PBR = the current PBR.

Method 2.2: and if the current PBR is smaller than the PBR threshold value, multiplying the current PBR by a second threshold value to obtain the target PBR, wherein the second threshold value a is a positive number which is greater than or equal to 1, namely the target PBR = a × the current PBR. And/or if the current PBR is greater than or equal to the PBR threshold value, not adjusting the current PBR, i.e., the target PBR = the current PBR.

Optionally, the second threshold a may be a value configured by the network device, and may also be a value configured by the terminal device.

Optionally, the PBR threshold is a quotient of the buffered data amount and the delay budget.

Alternatively, the PBR threshold value may be a third threshold value.

Optionally, the third threshold may be a value configured by the network device, and may also be a value configured by the terminal device.

In summary, when the buffering delay of the data in the logical channel does not meet the delay budget, the target PBR is at least one of the current PBR, the quotient of the buffered data amount and the delay budget value, and the product of the current priority bit rate and a second threshold a, where the second threshold a is a positive number greater than or equal to 1.

Optionally, when the delay budget result is that the cache delay of the data in the logical channel meets the delay budget, the target PBR is smaller than the current PBR, that is, when the delay budget is met, the PBR of the logical channel is reduced, so that the air interface resources acquired by the logical channel are reduced, and further, the limited air interface resources can be more allocated to the logical channel which does not meet the delay budget.

Optionally, when the buffering delay of the data in the logical channel meets the delay budget, the PBR of the logical channel may be adjusted as follows:

method 2.3: the PBR of the logical channel is restored to the initial PBR.

Method 2.4: if the current PBR is less than or equal to the initial PBR, the current PBR is not adjusted, i.e., the target PBR = the current PBR. And/or, if the current PBR is greater than the PBR, multiplying the current PBR by a second threshold to obtain the target PBR, wherein the second threshold b is a positive number less than 1, i.e., the target PBR = b × the current PBR.

Optionally, the second threshold b may be a value configured by the network device, and may also be a value configured by the terminal device.

To sum up, when the buffering delay of the data in the logical channel meets the delay budget, the target PBR is at least one of the current PBR, the initial PBR, the product of the current priority bit rate and a second threshold b, and the second threshold b is a positive number smaller than 1.

Fig. 5 is a second flowchart of the processing method provided in the embodiment of the present application, where the main body for executing the processing method is a terminal device (e.g., UE) for example, and in an actual implementation, the processing method may also be executed by a network device, as shown in fig. 5, where the method includes:

and S51, responding to the time delay budget result of the logical channel meeting the preset condition, and adjusting the priority bit rate of the logical channel.

In 5G NR, the network allocates uplink transmission resources on a per UE basis rather than on a per-bearer (per-bearer) basis, and it is determined by the UE which radio bearers' data can be put into the allocated uplink transmission resources for transmission. Based on the uplink transmission resources configured by the network, the UE needs to determine the transmission Data amount of each logical channel in the primary media Access Control Packet Data Unit (MAC PDU), and in some cases, the UE needs to allocate resources for a MAC Control Element (MAC CE). In order to realize multiplexing of uplink Logical Channels (LCHs), a priority needs to be assigned to each uplink Logical Channel. For a MAC PDU with a given size, under the condition that a plurality of uplink logical channels have data transmission requirements at the same time, resources of the MAC PDU are sequentially distributed according to the descending order of the logical channel priority corresponding to each uplink logical channel. Meanwhile, in order to take fairness among different logical channels into account, probability of Prioritized Bit Rate (PBR) is introduced, and when the UE multiplexes logical channels, it is necessary to first ensure a minimum data Rate requirement of each logical channel, so as to avoid that uplink logical channels with high priority always occupy uplink resources allocated to the UE by the network, which causes other uplink logical channels with low priority of the UE to be starved.

In order to realize the multiplexing of the uplink logical channels, the network radio resource control configures the following parameters for each uplink logical channel:

1: and for all the logical channels with Bj >0, allocating resources according to the sequence of the priority from high to low, wherein the resources allocated to each logical channel can only meet the requirement of PBR (provider-base ratio), namely allocating the resources for the logical channel according to the number of tokens in a PBR token bucket corresponding to the logical channel. When the PBR of a certain logical channel is set to infinity, a logical channel with a lower priority than that of the logical channel is considered only when the resources of the logical channel are satisfied.

3: if there are remaining uplink resources after the execution of S1 and S2, the remaining resources are sequentially allocated to the logical channels in the order of logical channel priority from high to low regardless of the size of Bj. Only when the data of the logical channel with high priority is completely transmitted and the UL grant is not exhausted, the logical channel with low priority can be served. I.e. when the UE maximizes data transmission for the logical channel of high priority.

And when the delay budget result of the logical channel meets the preset condition, the terminal equipment adjusts the PBR of the logical channel.

Optionally, the delay budget result meeting the preset condition includes at least one of:

the buffering delay of the data in the logic channel does not meet the delay budget, and the actual speed and/or the buffering data quantity meet at least one of the following conditions: the actual rate is less than or equal to the current PBR, and the cache data volume is greater than or equal to the product of the current PBR and the first duration; the amount of the buffered data is larger than or equal to the product of the actual speed and the delay budget value; the amount of the buffered data is larger than or equal to the product of the actual speed, the delay budget value and the first threshold value;

the buffering delay of the data in the logical channel meets the delay budget, and the actual speed and/or the buffering data quantity meet at least one of the following conditions: the actual rate is greater than the current PBR; the cache data volume is less than the product of the current PBR and the first duration; the amount of the buffered data is smaller than the product of the actual rate and the delay budget value; the amount of buffered data is less than the product of the actual rate, the delay budget and the first threshold.

The buffering delay of the data in the logical channel may or may not meet the delay budget. When the buffer delay of the data in the logical channel meets the delay budget, the buffer delay of the data in the logical channel is smaller, and at this time, the PBR of the logical channel may not be adjusted, or the PBR of the logical channel may be adjusted to be smaller, so that more air interface resources are allocated to other logical channels with higher requirements on the delay budget.

First, a scheme for determining a delay budget result of a logical channel is introduced.

As shown in fig. 4, it is first determined that the logical channel is configured with the parameter delay budget value, and then it is determined whether the timer reaches the first duration.

Optionally, PBR is periodically adjusted according to the first time period.

And after the timer reaches the first time length, acquiring a time delay budget result of the logic channel.

If so, determining the delay budget result as that the cache delay of the data in the logic channel does not meet the delay budget.

And after the time delay budget result is obtained, adjusting the PBR of the logic channel to be the target PBR.

Alternatively, the PBR threshold value may be a third threshold value.

method 2.3: the PBR of the logical channel is restored to the initial PBR.

Method 2.4: if the current PBR is less than or equal to the initial PBR, the current PBR is not adjusted, i.e., the target PBR = the current PBR. And/or if the current PBR is greater than the PBR, multiplying the current PBR by a second threshold to obtain the target PBR, wherein the second threshold b is a positive number less than 1, namely the target PBR = b × the current PBR.

In the above embodiments, how to obtain the delay budget result and how to adjust the PBR of the logical channel according to the delay budget result are described. Optionally, according to at least one of the method 1.1, the method 1.2, and the method 1.3 in the above embodiments, a delay budget result may be obtained. When the delay budget result indicates that the buffer delay of the data in the logical channel does not meet the delay budget, the PBR of the logical channel may be adjusted according to at least one of the methods 2.1 and 2.2 in the above embodiments; when the delay budget result is that the buffer delay of the data in the logical channel meets the delay budget, the PBR of the logical channel may be adjusted according to at least one of the methods 2.3 and 2.4 in the above embodiments. This will be described by way of example with reference to the accompanying drawings.

Fig. 6 is a first schematic view of PBR adjustment provided in the embodiment of the present application, where an execution subject is a terminal device (e.g., UE) for example in this embodiment, and in an actual implementation, the PBR adjustment may also be executed by a network device, as shown in fig. 6, where the PBR adjustment includes:

and S61, determining that the logic channel is configured with the delay budget value.

When the logical channel is configured with the delay budget value, the buffer delay of the logical channel is controlled.

And S62, judging whether the timer reaches the first time length, if so, executing S63, and/or otherwise, continuing to execute S62 after a certain time length.

In the embodiment of the application, the timer may be set to perform periodic detection, and the duration of the timer may be configured by the network device. S63 is executed when the timer reaches the first duration, and/or the running duration of the timer is continuously detected when the timer does not reach the first duration.

S63, whether the actual speed is less than or equal to the current PBR and the buffer data size is greater than or equal to the product of the current PBR and the first duration is judged. If so, then S64 is performed, and/or, if not, then S66 is performed.

S63 is an implementation manner of determining the delay budget result of the logical channel, that is, according to the method 1.1 in the foregoing embodiment, it is determined whether the buffer delay of the data in the logical channel meets the delay budget. S64 is performed when the buffering delay of the data in the logical channel does not satisfy the delay budget, and/or S66 is performed when the buffering delay of the data in the logical channel satisfies the delay budget.

S64, determine whether the current PBR is smaller than the quotient of the buffer data amount and the delay budget value, if yes, execute S65, and/or, if no, execute S67.

When the buffer delay of the data in the logical channel does not meet the delay budget, the PBR of the logical channel is adjusted according to the method 2.1 in the above embodiment. Optionally, it is determined whether the current PBR is smaller than the quotient of the buffered data amount and the delay budget value, if yes, then perform S65, and/or if no, then perform S67.

S65, adjust the target PBR to be the quotient of the buffered data amount and the delay budget value.

When the buffer delay of the data in the logic channel does not meet the delay budget and the current PBR is less than the quotient of the buffer data volume and the delay budget value, the target PBR is adjusted to be the quotient of the buffer data volume and the delay budget value. When the buffer delay of the data in the logical channel does not meet the delay budget and the current PBR is greater than or equal to the quotient of the buffer data amount and the delay budget value, the target PBR = the current PBR.

S66, the target PBR is adjusted to the initial PBR.

And when the buffer delay of the data in the logic channel meets the delay budget, adjusting the target PBR to the initial PBR.

And S67, determining the target PBR as the current PBR.

When the buffer delay of the data in the logical channel does not meet the delay budget and the current PBR is greater than or equal to the quotient of the buffer data amount and the delay budget value, the current PBR is already large and is not suitable for being adjusted again, so the PBR of the logical channel is not adjusted at the moment, and the target PBR of the logical channel is equal to the current PBR.

S68, saving the target PBR and using for LCP process, executing S62.

After the target PBR is determined, an LCP procedure may be performed according to the target PBR to implement dynamic adjustment of the buffering delay of data in the logical channel.

Fig. 7 is a schematic diagram of PBR adjustment provided in the embodiment of the present application, where an execution subject is a terminal device (e.g., UE) for example in this embodiment, and in an actual implementation, the PBR adjustment may also be executed by a network device, as shown in fig. 7, where the PBR adjustment includes:

and S71, determining that the logic channel is configured with the delay budget value.

And S72, judging whether the timer reaches the first time length, if so, executing S73, and/or otherwise, continuing to execute S72 after a certain time length.

In the embodiment of the application, the timer may be set to perform periodic detection, and the duration of the timer may be configured by the network device. When the timer reaches the first duration, S73 is executed, and when the timer does not reach the first duration, the running duration of the timer continues to be detected.

S73, judging whether the buffer data quantity is larger than or equal to the product of the actual speed and the delay budget value, if yes, executing S74, and/or otherwise executing S76.

S73 is an implementation manner of determining the delay budget result of the logical channel, that is, according to the method 1.2 in the foregoing embodiment, it is determined whether the buffer delay of the data in the logical channel meets the delay budget. S74 is performed when the buffering delay of the data in the logical channel does not satisfy the delay budget, and/or S76 is performed when the buffering delay of the data in the logical channel satisfies the delay budget.

S74, judging whether the current PBR is smaller than the PBRmax, if so, executing S75, and/or otherwise, executing S77.

When the buffering delay of the data in the logical channel does not meet the delay budget, the PBR of the logical channel is adjusted according to the method 2.2 in the above embodiment. Optionally, it is determined whether the current PBR is smaller than the PBR threshold (i.e., PBRmax), if so, S75 is executed, and/or if not, S77 is executed.

S75, the target PBR is adjusted to be the product of the current PBR and a.

When the buffer delay of the data in the logical channel does not meet the delay budget and the current PBR is smaller than PBRmax, the target PBR = the current PBR a, a is a second threshold, and a is a positive number greater than or equal to 1.

S76, the target PBR is adjusted to the initial PBR.

When the buffering delay of the data in the logical channel meets the delay budget, the PBR of the logical channel is adjusted according to the method 2.3 in the above embodiment. Optionally, the target PBR may be restored to the initial PBR.

And S77, determining the target PBR as the current PBR.

When the buffer delay of the data in the logical channel does not meet the delay budget and the current PBR is greater than or equal to PBRmax, the target PBR = the current PBR, that is, the PBR of the logical channel is not adjusted.

S78, saving the target PBR and using for LCP process, executing S72.

Fig. 8 is a third schematic view of PBR adjustment provided in the embodiment of the present application, where an execution subject is a terminal device (e.g., UE) for example in this embodiment, and in an actual implementation, the PBR adjustment may also be executed by a network device, as shown in fig. 8, where the PBR adjustment includes:

and S81, determining that the logic channel is configured with the delay budget value.

When the logic channel is configured with the delay budget value, the buffer delay of the logic channel is controlled.

And S82, judging whether the timer reaches the first time length, if so, executing S83, and/or otherwise, continuing to execute S82 after a certain time length.

In the embodiment of the application, the timer may be set to perform periodic detection, and the duration of the timer may be configured by the network device. S83 is executed when the timer reaches the first duration, and/or the running duration of the timer is continuously detected when the timer does not reach the first duration.

S83, judging whether the buffer data quantity is larger than or equal to the product of the actual speed and the delay budget value, if yes, executing S84, and/or otherwise executing S86.

S83 is an implementation manner of determining the delay budget result of the logical channel, that is, according to the method 1.2 in the foregoing embodiment, it is determined whether the buffer delay of the data in the logical channel meets the delay budget. S84 is performed when the buffering delay of the data in the logical channel does not satisfy the delay budget, and/or S86 is performed when the buffering delay of the data in the logical channel satisfies the delay budget.

S84, judging whether the current PBR is smaller than the PBRmax, if so, executing S85, and/or otherwise, executing S88.

When the buffering delay of the data in the logical channel does not meet the delay budget, the PBR of the logical channel is adjusted according to the method 2.2 in the above embodiment. Optionally, it is determined whether the current PBR is smaller than the PBR threshold (i.e., PBRmax), if so, S85 is executed, and/or if not, S88 is executed.

S85, the target PBR is adjusted to be the product of the current PBR and a.

S86, judging whether the current PBR is larger than the initial PBR, if yes, executing S87, and/or otherwise executing S88.

When the buffering delay of the data in the logical channel meets the delay budget, the PBR of the logical channel is adjusted according to the method 2.3 in the above embodiment. Optionally, it is determined whether the current PBR is greater than the initial PBR, if so, S87 is performed, and/or if not, S88 is performed.

S87, adjusting the target PBR to be the product of the current PBR and b.

And when the cache delay of the data in the logical channel meets the delay budget and the current PBR is greater than the initial PBR, multiplying the current PBR by a second threshold to obtain a target PBR, wherein the second threshold b is a positive number less than 1, namely the target PBR = b × the current PBR.

And S88, determining the target PBR as the current PBR.

S89, saving the target PBR and using for LCP process, executing S82.

Fig. 6 to 8 describe several control schemes for buffering delay of logical channels, and it can be understood that the delay budget result of a logical channel is determined according to at least one of the method 1.1, the method 1.2, and the method 1.3 in the above embodiments; when the buffer delay of the data in the logical channel does not meet the delay budget, the PBR of the logical channel may be adjusted according to the method 2.1 or the method 2.2 in the above embodiment; when the buffering delay of the data in the logical channel meets the delay budget, the PBR of the logical channel may be adjusted according to method 2.3 or method 2.4 in the above embodiment. That is, the method 1.1, the method 1.2, and the method 1.3, and the method 2.1, the method 2.2, the method 2.3, and the method 2.4 in the above embodiments may be combined at will to implement the control of the buffering delay of the logical channel.

According to the processing method provided by the application, firstly, a delay budget result of the logical channel is determined according to the delay budget value, and the delay budget result is used for indicating whether the cache delay of the data in the logical channel meets the delay budget or not. And then, adjusting the PBR of the logical channel according to the delay budget result, and after adjusting the PBR of the logical channel, changing the air interface resource obtained by the logical channel, thereby changing the transmission rate of the data in the logical channel and further changing the cache delay of the data in the logical channel. According to the scheme, the buffer delay of the data in the logic channel is controlled by dynamically adjusting the PBR of the logic channel.

Fig. 9 is a first schematic structural diagram of a processing device according to an embodiment of the present application, and as shown in fig. 9, the processing device 90 includes:

a processing module 91, configured to calculate or determine a delay budget result of the logical channel according to the delay budget value;

and an adjusting module 92, configured to adjust the priority bit rate of the logical channel according to the delay budget result.

Optionally, the processing module 91 is specifically configured to:

Optionally, the delay budget result includes at least one of:

the buffering delay of the data in the logical channel does not meet the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is less than or equal to the current priority bit rate, and the cache data volume is greater than or equal to the product of the current priority bit rate and the first duration; the cache data volume is larger than or equal to the product of the actual speed and the delay budget value; the cache data amount is greater than or equal to the product of the actual speed, the delay budget value and a first threshold value;

the buffering delay of the data in the logical channel meets the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is greater than the current priority bit rate; the cache data amount is less than the product of the current priority bit rate and the first duration; the cache data volume is smaller than the product of the actual speed and the delay budget value; the amount of the buffered data is smaller than the product of the actual rate, the delay budget value and the first threshold value.

Optionally, the adjusting module 92 is specifically configured to:

Optionally, the target priority bit rate is at least one of:

a current priority bit rate;

an initial priority bit rate;

the quotient of the buffer data volume and the delay budget value;

The processing apparatus provided in the embodiment of the present application may execute the technical solutions shown in the foregoing method embodiments, and the implementation principles and beneficial effects thereof are similar, and are not described herein again.

Fig. 10 is a schematic structural diagram of a second processing device according to an embodiment of the present application, and as shown in fig. 10, the processing device 100 includes:

the processing module 101 is configured to adjust a priority bit rate of the logical channel in response to that a delay budget result of the logical channel meets a preset condition.

Optionally, the processing module 101 is specifically configured to:

Optionally, the target priority bit rate is at least one of:

a current priority bit rate;

an initial priority bit rate;

the quotient of the buffer data volume and the delay budget value;

Optionally, the buffer delay of the data in the logical channel does not meet the delay budget, and the target priority bit rate is greater than or equal to the current priority bit rate; and/or the presence of a gas in the gas,

Fig. 11 is a schematic structural diagram of a communication device according to an embodiment of the present application. As shown in fig. 11, the communication device 110 according to this embodiment may be a terminal device (or a component that can be used for a terminal device) or a network device (or a component that can be used for a network device) mentioned in the foregoing method embodiments. The communication device 110 may be configured to implement the method corresponding to the terminal device or the network device described in the foregoing method embodiment, and refer to the description in the foregoing method embodiment specifically.

The communication device 110 may comprise one or more processors 111, which processors 111 may also be referred to as processing units and may perform certain control or processing functions. The processor 111 may be a general purpose processor or a special purpose processor, etc. For example, a baseband processor, or a central processor. The baseband processor may be used to process communication protocols and communication data, and the central processor may be used to control the communication device, execute software programs, and process data of the software programs.

Optionally, the processor 111 may also be populated with instructions 113 or data (e.g., intermediate data). Alternatively, the instructions 113 may be executed by the processor 111, so that the communication device 110 executes the method corresponding to the terminal device or the network device described in the above method embodiment.

Optionally, the communication device 110 may comprise circuitry that may implement the functionality of transmitting or receiving or communicating in the aforementioned method embodiments.

Optionally, one or more memories 112 may be included in the communication device 110, on which instructions 114 may be stored, which may be executed on the processor 111, to cause the communication device 110 to perform the methods described in the above method embodiments.

Optionally, the memory 112 may also store data. The processor 111 and the memory 112 may be provided separately or may be integrated together.

Optionally, the communication device 110 may also include a transceiver 115 and/or an antenna 116. The processor 111, which may be referred to as a processing unit, controls the communication device 110 (terminal device or core network device or radio access network device). The transceiver 115 may be referred to as a transceiving unit, a transceiver, a transceiving circuit, a transceiver, or the like, for implementing transceiving functions of the communication device 110.

Optionally, the specific implementation processes of the processor 111 and the transceiver 115 may refer to the related descriptions of the above embodiments, and are not described herein again.

The processor 111 and the transceiver 115 described herein may be implemented on an IC (Integrated Circuit), an analog Integrated Circuit, an RFIC (Radio Frequency Integrated Circuit), a mixed signal Integrated Circuit, an ASIC (Application Specific Integrated Circuit), a PCB (Printed Circuit Board), an electronic device, or the like. The processor 111 and transceiver 115 may also be fabricated using various integrated circuit process technologies, such as CMOS (Complementary Metal Oxide Semiconductor), NMOS (N-Metal-Oxide-Semiconductor), PMOS (P-Metal Oxide Semiconductor), BJT (Bipolar Junction Transistor), Bipolar CMOS (bicmos), silicon germanium (SiGe), gallium arsenide (GaAs), and the like.

In this application, the communication device may be a terminal device or a network device (e.g., a base station), and the specific requirement is determined according to the context, and in addition, the terminal device may be implemented in various forms. For example, the terminal devices described in the present application may include mobile terminals such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and fixed terminals such as a Digital TV, a desktop computer, and the like.

Although in the above description of the embodiment, the communication device is described by taking a terminal device or a network device as an example, the scope of the communication device described in the present application is not limited to the above terminal device or network device, and the structure of the communication device may not be limited by fig. 11. The communication device may be a stand-alone device or may be part of a larger device.

An embodiment of the present application further provides a communication system, including: a terminal device as in any one of the above method embodiments; and a network device as in any of the above method embodiments.

An embodiment of the present application further provides a communication device, where the communication device includes: a memory, a processor; wherein the memory has stored thereon a computer program which, when executed by the processor, implements the steps of the processing method in any of the above embodiments.

An embodiment of the present application further provides a terminal device, where the terminal device includes: a memory, a processor; wherein the memory has stored thereon a computer program which, when executed by the processor, implements the steps of the processing method in any of the above embodiments.

An embodiment of the present application further provides a network device, where the network device includes: a memory, a processor; wherein the memory has stored thereon a computer program which, when executed by the processor, implements the steps of the processing method in any of the above embodiments.

The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the processing method in any of the embodiments are implemented.

In the embodiments of the communication device, the terminal device, the network device, and the computer-readable storage medium provided in the embodiments of the present application, all technical features of any one of the embodiments of the processing method may be included, and the expanding and explaining contents of the specification are basically the same as those of the embodiments of the method, and are not described herein again.

Embodiments of the present application further provide a computer program product, which includes computer program code, when the computer program code runs on a computer, the computer is caused to execute the method as in the above various possible embodiments.

Embodiments of the present application further provide a chip, which includes a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device in which the chip is installed executes the method in the above various possible embodiments.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device in the embodiment of the application can be merged, divided and deleted according to actual needs.

In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.

In the present application, each embodiment is described with an emphasis on the description, and reference may be made to the description of other embodiments for parts that are not described or recited in any embodiment.

The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, a controlled terminal, or a network device) to execute the method of each embodiment of the present application.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, storage Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. A processing method is applied to terminal equipment and comprises the following steps:

s2, adjusting the current priority bit rate of the logic channel to be a target priority bit rate according to the delay budget result;

when the delay budget result indicates that the cache delay of the data in the logical channel meets the delay budget, the target priority bit rate is less than or equal to the current priority bit rate, and when the delay budget result indicates that the cache delay of the data in the logical channel does not meet the delay budget, the target priority bit rate is greater than the current priority bit rate.

2. The method according to claim 1, wherein the step of S1 includes:

3. The method of claim 2, wherein the delay budget result comprises at least one of:

the buffering delay of the data in the logical channel does not meet the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is less than or equal to the current priority bit rate, and the cache data volume is greater than or equal to the product of the current priority bit rate and the first duration; the cache data volume is larger than or equal to the product of the actual speed and the delay budget value; the cache data amount is larger than or equal to the product of the actual speed, the delay budget value and a first threshold value;

4. The method of claim 3, wherein the target priority bit rate is at least one of:

a current priority bit rate;

an initial priority bit rate;

the quotient of the buffer data volume and the delay budget value;

5. The method of claim 4, wherein the buffering delay of the data in the logical channel does not satisfy the delay budget, and wherein the buffering delay of the data in the logical channel comprises at least one of:

when the current priority bit rate is greater than or equal to the quotient of the cache data volume and the delay budget value, the target priority bit rate is the current priority bit rate;

6. The method of claim 5, wherein the priority bit rate threshold is a quotient of the buffered data amount and the delay budget; alternatively, the priority bit rate threshold is a third threshold.

7. The method according to claim 5 or 6, wherein the buffering delay of the data in the logical channel satisfies the delay budget, and comprises at least one of:

the target priority bit rate is at least one of: the current priority bit rate, an initial priority bit rate, a product of the current priority bit rate and the second threshold, the second threshold being a positive number less than or equal to 1;

8. A processing method is applied to terminal equipment and comprises the following steps:

s10, responding to the fact that the time delay budget result of the logic channel meets the preset condition, and adjusting the current priority bit rate of the logic channel to be the target priority bit rate;

9. The method according to claim 8, wherein the delay budget result satisfying the predetermined condition comprises at least one of:

the buffer delay of the data in the logical channel does not meet the delay budget, and the actual rate and/or the buffer data amount of the data transmission of the logical channel in the first duration meet at least one of the following conditions: the actual rate is less than or equal to the current priority bit rate, and the cache data volume is greater than or equal to the product of the current priority bit rate and the first duration; the buffer data amount is larger than or equal to the product of the actual speed and the delay budget value; the amount of the buffered data is greater than or equal to the actual rate; the product of the delay budget and a first threshold;

the buffering delay of the data in the logical channel meets the delay budget, and the actual rate and/or the buffering data amount meet at least one of the following conditions: the actual rate is greater than the current priority bit rate; the cache data amount is less than the product of the current priority bit rate and the first duration; the cache data volume is smaller than the product of the actual speed and the delay budget value; the cache data volume is smaller than the product of the actual speed, the delay budget value and the first threshold value;

and the delay budget value is used for calculating or determining a delay budget result of the logic channel.

10. The method of claim 9, wherein the target priority bit rate is at least one of:

a current priority bit rate;

an initial priority bit rate;

the quotient of the buffer data volume and the delay budget value;

11. The method of claim 10, wherein the buffering delay of the data in the logical channel does not satisfy the delay budget, and wherein at least one of:

the target priority bit rate is at least one of: a current priority bit rate; the quotient of the buffer data volume and the delay budget value; the product of the current priority bit rate and the second threshold, the second threshold being a positive number greater than or equal to 1;

12. The method of claim 11, wherein the priority bit rate threshold is a quotient of the amount of buffered data and the delay budget; alternatively, the priority bit rate threshold is a third threshold.

13. The method according to any of claims 11 or 12, wherein the buffering delay of the data in the logical channel satisfies the delay budget, comprising at least one of:

the target priority bit rate is at least one of: the current priority bit rate; an initial priority bit rate; a product of the current priority bit rate and the second threshold, the second threshold being a positive number less than or equal to 1;

14. A communication device, comprising: a memory and a processor;

the memory is to store program instructions;

the processor is for calling program instructions in the memory to perform the processing method of any of claims 1 to 13.

15. A computer-readable storage medium, characterized in that the storage medium has stored thereon a computer program; the computer program, when executed, implements the processing method of any one of claims 1 to 13.