CN114095092A - Optical receiving module and equalization compensation method - Google Patents
Optical receiving module and equalization compensation method Download PDFInfo
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- CN114095092A CN114095092A CN202210069162.5A CN202210069162A CN114095092A CN 114095092 A CN114095092 A CN 114095092A CN 202210069162 A CN202210069162 A CN 202210069162A CN 114095092 A CN114095092 A CN 114095092A
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Abstract
The invention provides an optical receiving module and an equalization compensation method, comprising the following steps: one end of the photoelectric detector receives bias voltage, and the other end of the photoelectric detector is connected with the input end of the passive equalizer; the passive equalizer compensates a signal component with a first preset frequency in the output signal of the photoelectric detector; the balanced transimpedance amplifier is used for compensating a signal component with a second preset frequency in the output signal of the passive equalizer and amplifying the signal component to obtain a single-ended voltage signal; the balanced single-ended differential converter is used for compensating a signal component of a third preset frequency in the single-ended voltage signal and converting the signal component into a differential voltage signal; and the balanced output buffer is used for compensating the signal component of the fourth preset frequency in the differential voltage signal and buffering and outputting the signal component. The invention adopts the mature APD chip with low speed rate to replace the 10G-APD chip with high cost, and meets the sensitivity requirement of the optical receiver by improving the structure of the optical receiving module; the comprehensive cost of the optical receiver is reduced, and the system index requirement is met.
Description
Technical Field
The present invention relates to the field of optical communications, and in particular, to an optical receiving module and an equalization compensation method.
Background
As an important Network for Optical fiber broadband access, a 10G PON (Passive Optical Network) has high performance and low cost, which are still important factors for Network construction. Due to the high requirements of the manufacturing process of the 10G-APD (avalanche photo diode) and the low yield, the cost of the 10G-APD chip is high, and the 10G-APD chip is not suitable for a cost-sensitive network such as a 10G PON.
Therefore, how to replace the 10G-APD with the ordinary APD with a lower cost through the improvement of the architecture, so as to reduce the cost and achieve high performance has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an optical receiving module and an equalization compensation method, which are used to solve the problem of high cost of the prior art 10G PON.
To achieve the above and other related objects, the present invention provides a light receiving module, comprising:
the device comprises a photoelectric detector, a passive equalizer, an equalizing transimpedance amplifier, an equalizing single-ended differential converter and an equalizing output buffer;
one end of the photoelectric detector receives bias voltage, and the other end of the photoelectric detector is connected with the input end of the passive equalizer;
the passive equalizer compensates a signal component with a first preset frequency in the output signal of the photoelectric detector;
the balanced transimpedance amplifier is connected to the output end of the passive equalizer, compensates a signal component of a second preset frequency in an output signal of the passive equalizer, and amplifies the output signal of the passive equalizer to obtain a single-ended voltage signal;
the balanced single-ended differential converter is connected to the output end of the balanced transimpedance amplifier, compensates a signal component of a third preset frequency in the single-ended voltage signal, and converts the single-ended voltage signal into a differential voltage signal;
the balanced output buffer is connected to the output end of the balanced single-ended differential converter, compensates a signal component of a fourth preset frequency in the differential voltage signal, and buffers and outputs the differential voltage signal.
Optionally, the photodetector is a photodiode, a cathode of the photodiode is connected to the bias voltage, and an anode of the photodiode is connected to the input terminal of the passive equalizer.
More optionally, the transmission rate of the photodetector is less than 10 Gbps.
More optionally, the transmission rate of the photodetector is 2.5Gbps or 4 Gbps.
Optionally, the passive equalizer includes a first capacitor and a first inductor; a first end of the first inductor is used as an input end of the passive equalizer, and a second end of the first inductor is used as an output end of the passive equalizer; the upper pole plate of the first capacitor is connected with the first end of the first inductor, and the lower pole plate of the first capacitor is grounded.
Optionally, the balanced transimpedance amplifier includes an amplifying module and a balanced feedback module; the input end of the amplifying module is connected with the output end of the passive equalizer, and the output end of the amplifying module is connected with the input end of the single-ended differential converter; the equalizing feedback module is connected between the input end and the output end of the amplifying module and comprises a first resistor and a second inductor which are connected in series.
Optionally, the balanced single-ended differential converter includes a low-pass filtering unit, a first differential input tube, a second differential input tube, a first current source, a second current source, a first load, a second capacitor, and a second resistor; the input end of the low-pass filtering unit is connected with the output end of the balanced transimpedance amplifier; the control end of the first differential input tube is connected with the output end of the balanced transimpedance amplifier, the first connection end is grounded through the first current source, and the second connection end is connected with power supply voltage through the first load; the control end of the second differential input tube is connected with the output end of the low-pass filtering unit, the first connection end is grounded through the second current source, and the second connection end is connected with the power supply voltage through the second load; the second connecting ends of the first differential input tube and the second differential input tube output the differential voltage signals; one end of the second capacitor is connected with the first connecting end of the first differential input tube, and the other end of the second capacitor is connected with the first connecting end of the second differential input tube; the second resistor is connected in parallel with two ends of the second capacitor.
Optionally, the balanced output buffer includes a third differential input tube, a fourth differential input tube, a third current source, a fourth current source, a third load, a fourth load, a third capacitor, and a third resistor; the control ends of the third differential input tube and the fourth differential input tube are respectively connected with the differential voltage signal; the first connecting end of the third differential input tube is grounded through the third current source, and the second connecting end is connected with a power supply voltage through the third load; the first connection end of the fourth differential input tube is grounded through the fourth current source, and the second connection end of the fourth differential input tube is connected with the power supply voltage through the fourth load; the second connecting ends of the third differential input tube and the fourth differential input tube are used as differential output ends of the balanced output buffer; one end of the third capacitor is connected with the first connecting end of the third differential input tube, and the other end of the third capacitor is connected with the first connecting end of the fourth differential input tube; the third resistor is connected in parallel with two ends of the third capacitor.
To achieve the above and other related objects, the present invention provides an equalization compensation method for an optical receiving module, the equalization compensation method at least comprising:
detecting an optical signal, and converting the optical signal into a first current signal;
compensating a signal component with a first preset frequency in the first current signal to obtain a second current signal;
compensating a signal component of a second preset frequency in the second current signal, and amplifying the second current signal to obtain a single-ended voltage signal;
compensating a signal component of a third preset frequency in the single-ended voltage signal, and converting the single-ended voltage signal into a differential voltage signal;
and compensating a signal component of a fourth preset frequency in the differential voltage signal, and buffering and outputting the differential voltage signal.
Alternatively, the bandwidth of the optical receiving module is widened step by step without changing the signal amplitude based on the four-time compensation.
More optionally, the amplitude of the signals in different frequency regions is adjusted based on the fourth compensation, so as to achieve the equalization compensation.
As described above, the optical receiving module and the equalization compensation method of the present invention have the following advantages:
the optical receiving module and the balance compensation method adopt the mature APD chip with low speed rate to replace the 10G-APD chip with high cost, and meet the sensitivity requirement of the optical receiver through the improvement of the optical receiving module structure; the invention reduces the comprehensive cost of the optical receiver, meets the system index requirement of the 10G PON and has very practical commercial value.
Drawings
Fig. 1 shows a schematic diagram of a TIA signal path architecture for APD applications.
Fig. 2 is a schematic diagram showing frequency characteristics of the system before and after compensation.
Figure 3 is a schematic diagram of a TIA signal path architecture employing equalization compensation.
Fig. 4 shows a schematic diagram of a frequency characteristic curve with overcompensation or undercompensation.
Fig. 5 and 6 are schematic diagrams illustrating frequency characteristic curves for compensating unevenness.
Fig. 7 is a schematic structural diagram of a light receiving module according to the present invention.
Fig. 8 is a schematic diagram of the structure of the passive equalizer of the present invention.
Fig. 9 is a schematic structural diagram of the balanced transimpedance amplifier according to the present invention.
Fig. 10 is a schematic diagram illustrating an architecture of an equalized single-ended-to-differential converter according to the present invention.
FIG. 11 is a schematic diagram of an equalizing output buffer according to the present invention.
Fig. 12 is a schematic diagram illustrating an equalization compensation method according to the present invention.
Fig. 13 is a schematic diagram illustrating another principle of the equalization compensation method of the present invention.
Description of the element reference numerals
1-TIA signal path architecture; 11-a transimpedance amplifier; 12-single-ended differential converter; 13-an output buffer; 2-TIA signal path architecture for equalization compensation; 21-a transimpedance amplifier; 22-single-ended-to-differential converter; 23-an equalizer; 24-an output buffer; 3-a light receiving module; 31-a passive equalizer; 32-balanced transimpedance amplifier; 321-an amplifying module; 322-an equalization feedback module; 33-balanced single-ended differential converter; 331-a low-pass filtering unit; 34-equalizing the output buffer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, a TIA (trans-impedance amplifier) signal path architecture 1 for APD applications is provided, which includes a photo detector APD, a trans-impedance amplifier 11, a single-ended differential converter 12, and an output buffer 13, which are sequentially cascaded. The minimum system bandwidth required by the optical receiver is generally set to be 0.7 times of the transmission rate of the system, and if the APD larger than the system bandwidth is adopted, the bandwidth of the TIA only needs to reach the system bandwidth, so that the cascaded optical receiver can better transmit signals, and the performance can be optimal. If an APD chip is employed that is below the system bandwidth requirements, the TIA circuit must add a frequency compensation network to compensate for the APD chip's bandwidth deficiencies. The frequency characteristic curves of the system before and after compensation are shown in fig. 2, wherein the solid line is before compensation and the dotted line is after compensation.
As shown in fig. 3, a TIA signal path architecture 2 using equalization compensation includes a photo detector APD, a transimpedance amplifier 21, a single-ended differential converter 22, an equalizer 23, and an output buffer 24, which are sequentially cascaded, that is, the equalizer 23 is added between the single-ended differential converter 22 and the output buffer 24, so that the system bandwidth after compensation satisfies signal transmission, where the equalizer 23 is an active equalizer. However, this structure has a number of technical drawbacks: first, an additional equalizer module needs to be added, resulting in increased overall power consumption. Secondly, adding an equalizer 23 after the single-ended-to-differential converter 22 will amplify the noise and signal in the same proportion, thereby degrading the system error rate. Finally, the architecture only adopts one-stage equalizer compensation, which may result in over-compensation or under-compensation within the whole bandwidth, as shown in fig. 4, where a is optimal compensation, B is insufficient high-frequency compensation, and C is excessive high-frequency compensation; even if the compensation bandwidth is appropriate, there may be unevenness of compensation within the bandwidth, which affects the signal quality and makes it difficult to meet the system performance requirements, as shown in fig. 5 and 6.
For the above reasons, the present invention provides a light receiving module 3 that maintains high performance while reducing cost.
As shown in fig. 7, the present invention provides a light receiving module 3, wherein the light receiving module 3 includes:
a photodetector, a passive equalizer 31, an equalizing transimpedance amplifier 32, an equalizing single-ended-to-differential converter 33, and an equalizing output buffer 34.
As shown in fig. 7, one end of the photodetector receives a bias voltage, and the other end is connected to an input terminal of the passive equalizer 31.
Specifically, in this embodiment, the photodetector is a photodiode APD, a cathode of the photodiode APD is connected to the bias voltage, and an anode of the photodiode APD is connected to the input terminal of the passive equalizer 31. Wherein the transmission rate of the photoelectric detector is less than 10 Gbps; by way of example, the transmission rate of the photodetector is 2.5Gbps or 4 Gbps. In practical use, the transmission rate of the photodetector can be set according to needs, and is not limited to the examples listed in this embodiment.
As shown in fig. 7, the passive equalizer 31 compensates a signal component of the first predetermined frequency in the photodetector output signal.
In particular, the passive equalizer 31 is used to adjust the amount of amplification of the first predetermined frequency signal component. As an example, as shown in fig. 8, the passive equalizer 31 includes a first capacitor C1 and a first inductor L1. A first terminal of the first inductor L1 serves as an input terminal IN of the passive equalizer 31, and a second terminal thereof serves as an output terminal OUT of the passive equalizer 31. The upper plate of the first capacitor C1 is connected to the first end of the first inductor L1, and the lower plate is grounded. In practical applications, the passive equalizer 31 may be any passive equalization structure, including but not limited to an LC equalization structure, an RC equalization structure, and an RL equalization structure, which are not described herein in detail.
As shown in fig. 7, the equalizing transimpedance amplifier 32 is connected to the output end of the passive equalizer 31, and is configured to compensate a signal component of a second preset frequency in the output signal of the passive equalizer 31, and amplify the output signal of the passive equalizer 31 to obtain a single-ended voltage signal.
Specifically, the equalizing transimpedance amplifier 32 is a transimpedance amplifier integrated with an equalizing function, wherein the passive device and an original device in the transimpedance amplifier form an equalizing compensation network, so that the equalizing compensation network does not increase extra power consumption, and the equalizing compensation network is used for adjusting the amplification amount of the second preset frequency signal component. As an example, as shown in fig. 9, the equalizing transimpedance amplifier 32 includes an amplifying module 321 and an equalizing feedback module 322. The input end of the amplifying module 321 is connected to the output end of the passive equalizer 31 (as the input end IN of the equalizing transimpedance amplifier 32), and the output end is connected to the input end of the single-ended differential converter 33 (as the output end OUT of the equalizing transimpedance amplifier 32). The equalizing feedback module 322 is connected between the input end and the output end of the amplifying module 321, and includes a first resistor R1 and a second inductor L1 connected in series. In practical use, the equalization compensation network formed by combining any passive equalization device and the device in the amplification module is applicable to the present invention, and is not limited to this embodiment.
As shown in fig. 7, the balanced single-ended-to-differential converter 33 is connected to the output end of the balanced transimpedance amplifier 32, compensates a signal component of a third predetermined frequency in the single-ended voltage signal, and converts the single-ended voltage signal into a differential voltage signal.
Specifically, the balanced single-ended-to-differential converter 33 is a single-ended-to-differential converter integrated with a balancing function, wherein the passive device and the original device in the single-ended-to-differential converter form a balancing compensation network, so that the balancing compensation network does not increase extra power consumption, and the balancing compensation network is used for adjusting the amplification amount of the third preset frequency signal component. As an example, as shown in fig. 10, the balanced single-ended-to-differential converter 33 includes a low-pass filtering unit 331, a first differential input tube NM1, a second differential input tube NM2, a first current source Ibias1, a second current source Ibias2, a first load Rout1, a second load Rout2, a second capacitor C2, and a second resistor R2. The input end of the low-pass filtering unit 331 is connected to the output end of the balanced transimpedance amplifier 32 (as the input end IN of the balanced single-ended differential converter 33); a control end of the first differential input tube NM1 is connected to the output end of the balanced transimpedance amplifier 32, a first connection end is grounded via the first current source Ibias1, and a second connection end is connected to a power supply voltage VDD via the first load Rout 1; a control terminal of the second differential input tube NM2 is connected to the output terminal of the low-pass filtering unit 331, a first connection terminal is grounded via the second current source Ibias2, and a second connection terminal is connected to the power voltage VDD via the second load; the second connection terminals of the first differential input tube NM1 and the second differential input tube NM2 output the differential voltage signals (as the output terminals OUTP and OUTN of the balanced single-ended-to-differential converter 33); one end of the second capacitor C2 is connected to the first connection end of the first differential input tube NM1, and the other end is connected to the first connection end of the second differential input tube NM 2; the second resistor R2 is connected in parallel to two ends of the second capacitor C2. In this embodiment, the first differential input tube NM1 and the second differential input tube NM2 are implemented by NMOS, the first connection end is a source, the second connection end is a drain, and the control end is a gate. The second resistor R2 and the second capacitor C2 form an equalization compensation network; in practical use, the equalization compensation network formed by combining any passive equalization device and the device in the single-ended differential conversion structure is applicable to the present invention, and the single-ended differential conversion structure is not limited to this embodiment.
As shown in fig. 7, the balanced output buffer 34 is connected to the output end of the balanced single-ended-to-differential converter 34, and is configured to compensate a signal component of a fourth preset frequency in the differential voltage signal, and buffer and output the differential voltage signal.
Specifically, the equalization output buffer 34 is an output buffer integrated with an equalization function, wherein the passive device and the original device in the output buffer form an equalization compensation network, so that the equalization compensation network does not increase extra power consumption, and the equalization compensation network is used for adjusting the amplification amount of the fourth preset frequency signal component. As an example, as shown in fig. 11, the balanced output buffer 34 includes a third differential input tube NM3, a fourth differential input tube NM4, a third current source Ibias3, a fourth current source Ibias4, a third load Rout3, a fourth load Rout4, a third capacitor C3, and a third resistor C4. The control terminals of the third differential input tube NM3 and the fourth differential input tube NM4 are respectively connected to the differential voltage signals (as the input terminals INP and INN of the equalizing output buffer 34); a first connection terminal of the third differential input tube NM3 is grounded via the third current source Ibias3, and a second connection terminal is connected to the power supply voltage VDD via the third load Rout 3; a first connection terminal of the fourth differential input tube NM4 is grounded via the fourth current source Ibias4, and a second connection terminal is connected to the power supply voltage VDD via the fourth load Rout 4; second connection terminals of the third differential input tube NM3 and the fourth differential input tube NM4 are used as differential output terminals of the balanced output buffer 34 (as output terminals OUTP and OUTN of the balanced output buffer 34); one end of the third capacitor C3 is connected to the first connection end of the third differential input tube NM3, and the other end of the third capacitor C3 is connected to the first connection end of the fourth differential input tube NM 4; the third resistor R3 is connected in parallel to two ends of the third capacitor C3. In this embodiment, the first third differential input tube NM3 and the fourth differential input tube NM4 are implemented by NMOS, and the first connection end is a source, the second connection end is a drain, and the control end is a gate. The third resistor R3 and the third capacitor C3 form an equalization compensation network; in practical use, the equalization compensation network formed by combining any passive equalization device and the device in the output buffer structure is applicable to the present invention, and the output buffer structure is not limited to this embodiment.
It should be noted that the first preset frequency, the second preset frequency, the third preset frequency, and the fourth preset frequency may be the same, crossed, or completely independent, and are set based on actual needs.
The invention also provides an equalization compensation method of the optical receiving module, which comprises the following steps:
detecting an optical signal, and converting the optical signal into a first current signal;
compensating a signal component with a first preset frequency in the first current signal to obtain a second current signal;
compensating a signal component of a second preset frequency in the second current signal, and amplifying the second current signal to obtain a single-ended voltage signal;
compensating a signal component of a third preset frequency in the single-ended voltage signal, and converting the single-ended voltage signal into a differential voltage signal;
and compensating a signal component of a fourth preset frequency in the differential voltage signal, and buffering and outputting the differential voltage signal.
In this embodiment, the equalization compensation method of the optical receiving module is implemented based on the optical receiving module 3, and in actual use, any hardware structure or software code capable of implementing the method is suitable for the present invention.
Specifically, as an example, the bandwidth of the optical receiving module is widened step by step without changing the signal amplitude based on the four-time compensation. As shown in fig. 12, the bandwidth of the optical receiver module is sequentially expanded to the right by the multiple compensation, and the amplitude corresponding to the frequency characteristic is not changed.
Specifically, as another example, the amplitude adjustment is performed on the signals of different frequency regions based on the four times of compensation, respectively, thereby achieving the equalization compensation. As shown in fig. 13, the bandwidth of the light receiving module is divided into a plurality of regions (Z1, Z2, Z3, and Z4) by frequency, and the amplification amounts of the different regions are adjusted so that the frequency characteristic curve in the solid line portion is adjusted to the frequency characteristic curve in the dotted line portion.
It should be noted that, the above two methods may also be combined to obtain a third compensation scheme, and for a specific low-speed APD, mixed compensation is performed, so that the frequency characteristic after compensation is as flat as possible, the eye diagram quality is clean, and the optimal optical receiver sensitivity is achieved. This is not repeated herein.
The invention realizes four-stage equalization compensation without increasing power consumption, and the equalization stage number increase can better compensate different frequencies to different degrees. The equalizer is passive, extra power consumption and extra noise cannot be introduced, and the signal-to-noise ratio is improved. For a high-speed optical communication system, the system bit error rate is mainly determined by the bandwidth and the signal-to-noise ratio; firstly, the bandwidth of the light receiving system is required to meet the requirement (such as 0.7 times of rate), and secondly, the signal-to-noise ratio is improved. Assuming that the total system bandwidth requirement can be achieved through 4-stage equalization, each stage of equalizer has 1.2 times of signal compensation, the first stage is a passive equalizer, the second to fourth stages are active equalizers, when the first stage equalizer is not added, the later stages are 3 stages of equalizers in total, and the signal-to-noise ratio of the system at this time meets the formula:
After the first-stage passive equalizer is added, the signal-to-noise ratio of the system meets the formula:
it can be seen that the signal-to-noise ratio is improved by 1.2 times after the first-stage passive equalizer is added, which is equivalent to the improvement of the sensitivity by 0.8 dB. Therefore, through the preceding-stage passive equalization and multi-stage equalization technology, the system bandwidth and the signal-to-noise ratio can be effectively improved, and the sensitivity performance of light receiving is further improved. The invention has the advantages that the comprehensive cost of the optical receiving end is greatly reduced under the condition of the sensitivity of the optical receiver system by meticulous optimization design and system consideration and matching with the optical receiving module of the low-speed APD, and the invention has practical value.
In summary, the present invention provides an optical receiving module and an equalization compensation method, including: the device comprises a photoelectric detector, a passive equalizer, an equalizing transimpedance amplifier, an equalizing single-ended differential converter and an equalizing output buffer; one end of the photoelectric detector receives bias voltage, and the other end of the photoelectric detector is connected with the input end of the passive equalizer; the passive equalizer compensates a signal component with a first preset frequency in the output signal of the photoelectric detector; the balanced transimpedance amplifier is connected to the output end of the passive equalizer, compensates a signal component of a second preset frequency in an output signal of the passive equalizer, and amplifies the output signal of the passive equalizer to obtain a single-ended voltage signal; the balanced single-ended differential converter is connected to the output end of the balanced transimpedance amplifier, compensates a signal component of a third preset frequency in the single-ended voltage signal, and converts the single-ended voltage signal into a differential voltage signal; the balanced output buffer is connected to the output end of the balanced single-ended differential converter, compensates a signal component of a fourth preset frequency in the differential voltage signal, and buffers and outputs the differential voltage signal. The optical receiving module and the balance compensation method adopt the mature APD chip with low speed rate to replace the 10G-APD chip with high cost, and meet the sensitivity requirement of the optical receiver through the improvement of the optical receiving module structure; the invention reduces the comprehensive cost of the optical receiver, meets the system index requirement of the 10G PON and has very practical commercial value. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. An optical receiving module, comprising:
the device comprises a photoelectric detector, a passive equalizer, an equalizing transimpedance amplifier, an equalizing single-ended differential converter and an equalizing output buffer;
one end of the photoelectric detector receives bias voltage, and the other end of the photoelectric detector is connected with the input end of the passive equalizer;
the passive equalizer compensates a signal component with a first preset frequency in the output signal of the photoelectric detector;
the balanced transimpedance amplifier is connected to the output end of the passive equalizer, compensates a signal component of a second preset frequency in an output signal of the passive equalizer, and amplifies the output signal of the passive equalizer to obtain a single-ended voltage signal;
the balanced single-ended differential converter is connected to the output end of the balanced transimpedance amplifier, compensates a signal component of a third preset frequency in the single-ended voltage signal, and converts the single-ended voltage signal into a differential voltage signal;
the balanced output buffer is connected to the output end of the balanced single-ended differential converter, compensates a signal component of a fourth preset frequency in the differential voltage signal, and buffers and outputs the differential voltage signal.
2. The light receiving module of claim 1, wherein: the photoelectric detector is a photodiode, the cathode of the photodiode is connected with the bias voltage, and the anode of the photodiode is connected with the input end of the passive equalizer.
3. The light-receiving module according to claim 1 or 2, wherein: the transmission rate of the photoelectric detector is less than 10 Gbps.
4. The light receiving module of claim 3, wherein: the transmission rate of the photoelectric detector is 2.5Gbps or 4 Gbps.
5. The light receiving module of claim 1, wherein: the passive equalizer comprises a first capacitor and a first inductor; a first end of the first inductor is used as an input end of the passive equalizer, and a second end of the first inductor is used as an output end of the passive equalizer; the upper pole plate of the first capacitor is connected with the first end of the first inductor, and the lower pole plate of the first capacitor is grounded.
6. The light receiving module of claim 1, wherein: the balanced transimpedance amplifier comprises an amplifying module and a balanced feedback module; the input end of the amplifying module is connected with the output end of the passive equalizer, and the output end of the amplifying module is connected with the input end of the single-ended differential converter; the equalizing feedback module is connected between the input end and the output end of the amplifying module and comprises a first resistor and a second inductor which are connected in series.
7. The light receiving module of claim 1, wherein: the balanced single-ended differential converter comprises a low-pass filtering unit, a first differential input tube, a second differential input tube, a first current source, a second current source, a first load, a second capacitor and a second resistor; the input end of the low-pass filtering unit is connected with the output end of the balanced transimpedance amplifier; the control end of the first differential input tube is connected with the output end of the balanced transimpedance amplifier, the first connection end is grounded through the first current source, and the second connection end is connected with power supply voltage through the first load; the control end of the second differential input tube is connected with the output end of the low-pass filtering unit, the first connection end is grounded through the second current source, and the second connection end is connected with the power supply voltage through the second load; the second connecting ends of the first differential input tube and the second differential input tube output the differential voltage signals; one end of the second capacitor is connected with the first connecting end of the first differential input tube, and the other end of the second capacitor is connected with the first connecting end of the second differential input tube; the second resistor is connected in parallel with two ends of the second capacitor.
8. The light receiving module of claim 1, wherein: the balanced output buffer comprises a third differential input tube, a fourth differential input tube, a third current source, a fourth current source, a third load, a fourth load, a third capacitor and a third resistor; the control ends of the third differential input tube and the fourth differential input tube are respectively connected with the differential voltage signal; the first connecting end of the third differential input tube is grounded through the third current source, and the second connecting end is connected with a power supply voltage through the third load; the first connection end of the fourth differential input tube is grounded through the fourth current source, and the second connection end of the fourth differential input tube is connected with the power supply voltage through the fourth load; the second connecting ends of the third differential input tube and the fourth differential input tube are used as differential output ends of the balanced output buffer; one end of the third capacitor is connected with the first connecting end of the third differential input tube, and the other end of the third capacitor is connected with the first connecting end of the fourth differential input tube; the third resistor is connected in parallel with two ends of the third capacitor.
9. An equalization compensation method for an optical receiving module, the equalization compensation method at least comprising:
detecting an optical signal, and converting the optical signal into a first current signal;
compensating a signal component with a first preset frequency in the first current signal to obtain a second current signal;
compensating a signal component of a second preset frequency in the second current signal, and amplifying the second current signal to obtain a single-ended voltage signal;
compensating a signal component of a third preset frequency in the single-ended voltage signal, and converting the single-ended voltage signal into a differential voltage signal;
and compensating a signal component of a fourth preset frequency in the differential voltage signal, and buffering and outputting the differential voltage signal.
10. The method of claim 9, wherein: the bandwidth of the optical receiving module is widened step by step based on the quartic compensation without changing the signal amplitude.
11. The equalizing compensation method for an optical receiver module according to claim 9 or 10, wherein: and respectively carrying out amplitude adjustment on the signals in different frequency areas based on the four-time compensation, thereby realizing the balance compensation.
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