CN114064555A - Centralized control method and system for interconnection among multiple FPGA chips - Google Patents
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Abstract
The invention provides a centralized control method for interconnection among a plurality of FPGA chips, and relates to the technical field of communication. The system comprises a main processor and a plurality of slave processors which are controlled by the main processor in a centralized way; initializing a control system of a master processor and control systems of a plurality of slave processors; a control system of a main processor sends a command of management and configuration to a programmable logic device of the main processor through an AXI bus; after receiving the management and configuration command, the programmable logic device of the main processor converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with the programmable logic devices of the plurality of slave processors respectively. The linear speed of transmission can be improved, and the complex control and management of a large-scale antenna technology system can be met.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a centralized control method and system for interconnection among a plurality of FPGA chips.
Background
The 5G NR (New Radio) is a global 5G standard based on a New air interface design of OFDM (Orthogonal Frequency Division Multiplexing ), which is also an important cellular mobile technology of the next generation, and a key technology of 5G is a large-scale antenna technology, that is, Massive MIMO. The number of antennas of a conventional TDD (Time Division duplex) network is usually 2 antennas, 4 antennas or 8 antennas, and the number of channels of Massive MIMO can reach 64 antennas. With the increase of the number of antennas, the system capacity is multiplied, but correspondingly, the system implementation complexity is also multiplied, so that multiple FPGAs are usually required for the logic implementation of the Massive MIMO system. In order to realize configuration, monitoring and management of multiple FPGAs, a reasonable FPGA inter-chip interconnection control mode needs to be designed, and generally, control mainly includes centralized control and distributed control. Distributed control, namely, each FPGA is controlled independently, and the defect is that the control of timing requirements among a plurality of FPGAs is difficult to meet the control timing requirements. Therefore, centralized control is the preferred control method, and the centralized control usually uses a switch chip (ethernet switch chip), as shown in fig. 3, PS (control system/processing system) controls PS of other FPAGs through the switch chip, which has a low rate and is difficult to meet the control requirement of a complex system.
Disclosure of Invention
The invention aims to provide a centralized control method for interconnection among a plurality of FPGA chips, which can improve the linear speed of transmission and meet the complex control and management of a large-scale antenna technology system.
The embodiment of the invention is realized by the following steps:
in a first aspect, an embodiment of the present application provides a centralized control method for interconnection among multiple FPGA chips, including a master processor and multiple slave processors that are centrally controlled by the master processor; initializing a control system of a master processor and control systems of a plurality of slave processors; a control system of a main processor sends a command of management and configuration to a programmable logic device of the main processor through an AXI bus; after receiving the management and configuration command, the programmable logic device of the main processor converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with a plurality of slave processors respectively.
In some embodiments of the present invention, the step of initializing the control system of the master processor and the control systems of the plurality of slave processors comprises: putting the chip2chip protocol of the slave processor into a reset state; resetting an orthogonal phase-locked loop of the high-speed serial deserializer, checking whether the phase-locked loop is locked or not, and canceling a chip2chip protocol reset operation of a slave processor; the chip2chip protocol of the host processor is reset and a check is made as to whether the link establishment was successful.
In some embodiments of the present invention, the step of resetting the high speed serializer comprises: and resetting the orthogonal phase-locked loop, the transmitting data link and the receiving data link of the high-speed serial deserializer in sequence, and sending interactive data to the main processor.
In some embodiments of the invention, the interaction data comprises quadrature phase locked loop reset data and transmit receive channel reset data.
In some embodiments of the present invention, the step of placing the chip2chip protocol of the slave processor in a reset state comprises: the chip2chip protocol of the slave processor is placed in a reset state by the port expander.
In some embodiments of the present invention, the step of resetting the chip2chip protocol of the host processor comprises: the chip2chip protocol of the main processor is reset through the AXI bus direct configuration.
In some embodiments of the invention, the port physical layer data is the port physical layer under the Aurora 64B/66B high-speed serial communication extensible link layer protocol.
In a second aspect, an embodiment of the present application provides a centralized control system for interconnection among multiple FPGA chips, where a processor module of the system is used for a master processor and multiple slave processors that are centrally controlled by the master processor; the initialization module is used for carrying out initialization operation on a control system of the master processor and control systems of the plurality of slave processors; the system comprises a configuration module, a programmable logic device and a control module, wherein the configuration module is used for sending a management and configuration command to the programmable logic device of a main processor through an AXI bus by a control system of the main processor; and the inter-chip interaction module is used for converting the management and configuration commands into port physical layer data through a chip2chip protocol after the programmable logic device of the main processor receives the management and configuration commands, and performing data interaction with the plurality of slave processors respectively.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a master processor, a plurality of slave processors connected to the master processor, at least one memory, and a data bus; wherein: the master processor, the plurality of slave processors and the memory complete mutual communication through a data bus; the memory stores program instructions executable by the processor, and the master processor and the plurality of slave processors invoke the program instructions to perform the method.
In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and the computer program is executed by a processor to implement the method.
Compared with the prior art, the embodiment of the invention has at least the following advantages or beneficial effects:
a high-speed centralized control method based on interconnection among programmable logic devices in a processor is characterized in that the programmable logic devices of a main processor (PL for short) are used for carrying out unified configuration on the programmable logic devices of the auxiliary processor, and an original control system (PS for short) of the auxiliary processor is only used for some initialization configuration during system initialization, so that the linear speed is improved, the complex control and management of a system of a large-scale antenna technology (Massive MIMO system) are met, and the linear speed can reach 4 GHz.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a flow chart of a centralized control method for interconnection among multiple FPGA chips according to the present invention;
FIG. 2 is a schematic structural diagram of a centralized control method for interconnection among multiple FPGA chips according to the present invention;
FIG. 3 is a schematic diagram of a prior art structure of the present invention;
FIG. 4 is a schematic diagram of the structure of centralized control of the interconnection among a plurality of FPGA chips according to the present invention;
fig. 5 is a flowchart of a centralized control system for interconnection among multiple FPGA chips according to the present invention.
Icon: 1. a main processor; 2. a slave processor; 3. a processor module; 4. initializing a module; 5. a configuration module; 6. and an inter-chip interaction module.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the term "connected" is to be interpreted broadly, e.g. as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the individual features of the embodiments can be combined with one another without conflict.
Example 1
Referring to fig. 1, fig. 2 and fig. 4, the present invention provides a centralized control method for interconnection among multiple FPGA chips, which is a high-speed centralized control method based on interconnection among programmable logic devices in a processor, and the principle of the centralized control method is that the programmable logic devices of a master processor 1 (hereinafter referred to as PL) are used to perform unified configuration on the programmable logic devices of a slave processor 2, and an original control system (control system hereinafter referred to as PS) of the slave processor 2 is only used for some initialization configurations during system initialization, so as to improve linear velocity and meet complex control and management of a system of a large-scale antenna technology (Massive MIMO system), and the linear velocity can reach 4 GHz. The specific implementation mode is as follows:
the hardware of the invention is based on Xilinx ZYNQ SOC architecture, and is provided with a main processor 1 and a plurality of slave processors 2 which are controlled by the main processor 1 in a centralized way; the programmable logic array (FPGA) is composed of a control system (PS for short) and a programmable logic device (PL for short). The PS mainly realizes the control of management, configuration, monitoring and the like of the whole system; the PL mainly implements each functional block. Taking five FPGAs as an example, one of them is used as a master processor 1, the other four are used as slave processors 2, and the PS of the master processor 1 performs centralized control on all the other FPGAs.
S101: initializing the control system of the master processor 1 and the control systems of the plurality of slave processors 2;
communication is also possible between the PS of the master processor 1 and the slave processor 2, but only some simple initialization and the like are controlled because of the low communication interface rate. Therefore, the control system of the master processor 1 and the control systems of the plurality of slave processors 2 are initialized at the data processing starting stage, so that the influence of the previous data processing is avoided.
S102: a control system of the main processor 1 sends a command of management and configuration to a programmable logic device of the main processor 1 through an AXI bus;
where the main management and configuration data is interacted with by the PS of the main processor 1 through the AXI bus to the PL of the main processor 1.
S103: after receiving the management and configuration command, the programmable logic device of the main processor 1 converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with the plurality of slave processors 2 respectively.
After the management and configuration commands reach the PL of the master processor 1 through the AXI bus, the AXI commands are converted into port physical layer (PHY) data by adopting a lightweight saint (Xilinx) IP core on the PL of the master processor 1 based on the chip2chip protocol, and the data interaction is performed with the PLs of several slave processors 2 respectively. Therefore, the running speed is improved, and the control requirement of a complex system is met. The chip2chip protocol is an IP core proposed by saint, and the core function of the chip2chip protocol is like a bridge, two processors are seamlessly connected through an AXI interface, and the AXI protocol specification is used. The bridging function allows all AXI channels to operate independently by forwarding data and control information for each channel.
In some embodiments of the invention, the step of performing an initialization operation on the control system of the master processor 1 and the control systems of the plurality of slave processors 2 comprises:
placing the chip2chip protocol of the slave processor 2 in a reset state; resetting an orthogonal phase-locked loop of the high-speed serial deserializer, checking whether the phase-locked loop is locked or not, and canceling a chip2chip protocol reset operation of the slave processor 2; the chip2chip protocol of the host processor 1 is reset and it is checked whether the link establishment is successful.
In some embodiments of the present invention, for a high-speed interface, the reset process is very critical, and an interface is abnormal due to insufficient reset or unreasonable reset process. In an embodiment, it is important to have two reset operations, and the correct reset timing must be guaranteed, otherwise PS hang-up may result. One is that the chip2chip protocol needs to be reset; the other is to reset the high speed serial transceivers (serdes). When the chip2chip protocol of the main processor 1 is reset, the configuration can be directly carried out through the AXI bus, and when the chip2chip protocol on the main processor 2 is reset, the configuration is carried out through a port expander (GPIO), so that the chip2chip protocol of the whole system can be reset only by 4 GPIOs. According to the reset requirement of the serdes, a QPLL (Quadrature phase locked loop), a TX DATAPATH (transmission data link) and a RXDATPATH (reception data link) of the serdes are reset in sequence, and interactive data are provided for the PS, so that corresponding parts of a high-speed port can be reset in time when needed.
In some embodiments of the present invention, the step of resetting the high speed serializer comprises:
and resetting the orthogonal phase-locked loop, the transmitting data link and the receiving data link of the high-speed serial deserializer in sequence, and sending interactive data to the main processor 1.
In some embodiments of the present invention, the resetting of the chip2chip protocol and the serdes needs to ensure that a specific reset timing sequence is satisfied between the chip2chip protocol and the serdes, in addition to the respective reset procedures.
In some embodiments of the invention, the interaction data comprises quadrature phase locked loop reset data and transmit receive channel reset data.
Specific data provided for the PS include QPLL reset (which can reset QPLL of the serdes), GTRESET (which can reset TX and RX datapath of the serdes), and GTTXRESET (which can reset datapath of TX and RX, respectively). Where TX and RX correspond to transmit and receive channels, respectively.
In some embodiments of the present invention, the step of placing the chip2chip protocol of the slave processor 2 in a reset state includes; the chip2chip protocol of the slave processor 2 is put into a reset state through the port expander.
In some embodiments of the present invention, the step of resetting the chip2chip protocol of the host processor 1 includes:
the chip2chip protocol of the main processor 1 is reset by directly configuring the AXI bus.
In some embodiments of the invention, the port physical layer data is the port physical layer under the Aurora 64B/66B high-speed serial communication extensible link layer protocol.
In some embodiments of the present invention, Aurora 64B/66B is selected as the PHY for the chip2 chip. For the selection of a port physical layer (PHY), SelectIO can be directly adopted, but in this way, hardware pins are greatly increased, and because the hardware platform of the design has rich Serdes resources, the Aurora 64B/66B IP of Xilinx is selected to realize the conversion between the data of a chip2chip and the data of a Xilinx serial transceiver (GTH/GTY) in the selection of the PHY. The data line rate can be controlled to reach 4Gsps by chip2chip + Aurora 64B/66B + GTY/GTH.
Example 2
Referring to fig. 5, a centralized control system for interconnection among multiple FPGA chips includes:
the processor module 3 is used for the main processor 1 and a plurality of slave processors 2 which are controlled by the main processor 1 in a centralized way; the initialization module 4 is used for carrying out initialization operation on the control system of the master processor 1 and the control systems of the plurality of slave processors 2; a configuration module 5, configured to send a command for management and configuration to the programmable logic device of the main processor 1 through the AXI bus by the control system of the main processor 1; and the inter-chip interaction module 6 is used for converting the management and configuration commands into port physical layer data through a chip2chip protocol after the programmable logic device of the main processor 1 receives the management and configuration commands, and performing data interaction with the plurality of slave processors 2 respectively.
Example 3
Referring to fig. 4, an electronic device includes a master processor 1, a plurality of slave processors 2 connected to the master processor 1, at least one memory, and a data bus; wherein: the main processor 1, the plurality of slave processors 2 and the memory complete mutual communication through a data bus; the memory stores program instructions which can be executed by the processor, and the main processor 1 and the plurality of secondary processors 2 call the program instructions to execute a centralized control method for interconnection among a plurality of FPGA chips. For example, the following steps are realized:
a master processor 1 and a plurality of slave processors 2 controlled by the master processor 1 in a centralized manner; initializing the control system of the master processor 1 and the control systems of the plurality of slave processors 2; a control system of the main processor 1 sends a command of management and configuration to a programmable logic device of the main processor 1 through an AXI bus; after receiving the management and configuration command, the programmable logic device of the main processor 1 converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with the plurality of slave processors 2 respectively.
Example 4
In some embodiments of the present invention, a computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements a method of centralized control of interconnection among a plurality of FPGA chips. For example, the following steps are realized:
a master processor 1 and a plurality of slave processors 2 controlled by the master processor 1 in a centralized manner; initializing the control system of the master processor 1 and the control systems of the plurality of slave processors 2; a control system of the main processor 1 sends a command of management and configuration to a programmable logic device of the main processor 1 through an AXI bus; after receiving the management and configuration command, the programmable logic device of the main processor 1 converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with the plurality of slave processors 2 respectively.
The Memory may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.
The processor may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), etc.; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A centralized control method for interconnection among a plurality of FPGA chips is characterized by comprising the following steps:
initializing a control system of a master processor and control systems of a plurality of slave processors;
the control system of the main processor sends a command for management and configuration to the programmable logic device of the main processor through an AXI bus;
after receiving the management and configuration command, the programmable logic device of the main processor converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with the programmable logic devices of the plurality of slave processors respectively.
2. The method of claim 1, wherein initializing the control system of the master processor and the control systems of the plurality of slave processors comprises:
putting the chip2chip protocol of the slave processor into a reset state;
resetting an orthogonal phase-locked loop of the high-speed serial deserializer, checking whether the phase-locked loop is locked or not, and canceling a chip2chip protocol reset operation of a slave processor;
the chip2chip protocol of the host processor is reset and a check is made as to whether the link establishment was successful.
3. The method for centralized control of the interconnection among the plurality of FPGA chips as recited in claim 2, wherein the step of resetting the high speed serializer deserializer comprises:
and resetting the orthogonal phase-locked loop, the transmitting data link and the receiving data link of the high-speed serial deserializer in sequence, and sending interactive data to the main processor.
4. The method according to claim 3, wherein the interactive data comprises quadrature phase-locked loop reset data and transceiving channel reset data.
5. The method of claim 2, wherein the step of placing the chip2chip protocol of the slave processor in a reset state comprises; the chip2chip protocol of the slave processor is placed in a reset state by the port expander.
6. The method for centralized control of the interconnection between a plurality of FPGA chips as recited in claim 2, wherein the step of resetting the chip2chip protocol of the main processor comprises:
the chip2chip protocol of the main processor is reset through the AXI bus direct configuration.
7. The method according to claim 1, wherein the data of the port physical layer is a port physical layer under an Aurora 64B/66B high-speed serial communication extensible link layer protocol.
8. The utility model provides a centralized control system of interconnection between a plurality of FPGA chips which characterized in that includes:
the processor module is used for a main processor and a plurality of slave processors which are controlled by the main processor in a centralized way;
the initialization module is used for carrying out initialization operation on the control system of the master processor and the control systems of the plurality of slave processors;
the configuration module is used for sending a command of management and configuration to a programmable logic device of the main processor by a control system of the main processor through an AXI bus;
and the inter-chip interaction module is used for converting the management and configuration commands into port physical layer data through a chip2chip protocol after the programmable logic device of the main processor receives the management and configuration commands, and performing data interaction with the plurality of slave processors respectively.
9. An electronic device comprising a master processor, a plurality of slave processors connected to the master processor, at least one memory and a data bus; wherein: the master processor, the plurality of slave processors and the memory complete mutual communication through the data bus; the memory stores program instructions executable by the processor, the program instructions being invoked by the master processor and the plurality of slave processors to perform the method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-7.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116088927A (en) * | 2023-04-10 | 2023-05-09 | 成都远望科技有限责任公司 | FPGA program circuit and method based on ZYNQ processor configuration |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116088927A (en) * | 2023-04-10 | 2023-05-09 | 成都远望科技有限责任公司 | FPGA program circuit and method based on ZYNQ processor configuration |
| CN116088927B (en) * | 2023-04-10 | 2023-06-20 | 成都远望科技有限责任公司 | FPGA program circuit and method based on ZYNQ processor configuration |
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