CN114064212B

CN114064212B - Access address tracking method and device for PCI device and computer readable storage medium

Info

Publication number: CN114064212B
Application number: CN202111355164.2A
Authority: CN
Inventors: 孙海清
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2022-07-29
Anticipated expiration: 2041-11-16
Also published as: CN114064212A

Abstract

The invention provides an access address tracking method, equipment and a computer readable storage medium of PCI equipment, wherein the method comprises the following steps: the PCI equipment is transmitted to the virtual host machine in a transparent mode, so that the access of the PCI equipment to the host machine memory of the host machine is converted into an access request to the virtual memory of the virtual host machine; configuring a virtual memory into a non-read-write mode, and registering a first callback function and a second callback function in a virtual host; responding to an access request of the PCI equipment to the virtual memory, and generating a first signal by an operating system; the virtual host calls a first callback function to perform, in response to the first signal: recording an access address corresponding to the access request to generate a tracking log, configuring the virtual memory into a read-write mode, and executing access operation on the access address; after the access operation is completed, the virtual host calls a second callback function to reconfigure the virtual memory into a non-read-write-able mode. By the method, the debugging efficiency of the PCI equipment to the access error of the host memory can be improved.

Description

Access address tracking method and device for PCI device and computer readable storage medium

Technical Field

The invention belongs to the field of debugging, and particularly relates to an access address tracking method and device of a PCI device and a computer readable storage medium.

Background

This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

At present, a kernel drive is generally adopted to apply for a host memory (namely, a host physical memory) by a PCI device for accessing the host memory of a host, an obtained memory start address is transmitted to the PCI device, and the PCI device directly accesses the host memory through mechanisms such as an IOMMU (inter-memory management unit), an SMMU and the like. In the access process, generally, the wrong address access does not exist by default, however, when the PCI equipment accesses the invalid host memory address, a kernel error occurs. In other scenarios, when the PCI device access address is not the desired address, although no kernel error is generated, it may cause damage to other valid physical memory contents, causing unpredictable errors. Under the above circumstances, a PCIe protocol analyzer needs to be used to analyze the access to the physical memory of the host, and the analysis process is complicated and the problem location efficiency is low.

Disclosure of Invention

Aiming at the problems in the prior art, the method, the device and the computer readable storage medium for tracking the access address of the PCI device are provided, and the problem of low positioning efficiency when the memory of the host is accessed wrongly can be solved by using the method, the device and the computer readable storage medium.

The present invention provides the following.

In a first aspect, a method for tracking an access address of a PCI device is provided, including: the PCI equipment is transmitted to the virtual host machine in a transparent mode, so that the access of the PCI equipment to the host machine memory of the host machine is converted into an access request to the virtual memory of the virtual host machine; configuring a virtual memory of a virtual host machine into a non-readable and writable mode, and registering a first callback function and a second callback function in the virtual host machine; responding to an access request of the PCI equipment to the virtual memory, and generating a first signal for indicating a memory access error by an operating system; the virtual host calls a first callback function in response to the first signal to perform: recording an access address corresponding to the access request to generate a tracking log, configuring the virtual memory into a read-write mode, and executing an access operation on the access address; after the access operation is completed, the virtual host calls a second callback function to reconfigure the virtual memory into a non-read-write-able mode.

In one embodiment, after the access operation is completed, the virtual host calls a second callback function to reconfigure the virtual memory into the unreadable and writable mode, and further includes: in response to the completion of the execution of the access operation to the access address, the operating system generates a second signal; the virtual host calls a second callback function in response to the second signal.

In one embodiment, performing an access operation to an access address includes: enabling the processor to be in single step mode; performing an access operation to an access address in a single step mode; and, the method further comprises: in response to the completion of the execution of the access operation to the access address in the single step mode, the operating system generates a second signal indicating a trap exception; the virtual host, in response to the second signal, calls a second callback function to perform: reconfiguring the virtual memory into a non-read-write mode; and, exiting the single step mode from the processor.

In one embodiment, the transparently passing the PCI device to the virtual host further comprises: and binding the PCI equipment to the VFIO driver so as to enable the PCI equipment to be transmitted to the virtual host.

In one embodiment, the first signal is a SIGSEGVGV signal.

In one embodiment, the second signal is a sigrap signal.

In one embodiment, the virtual host is a QEMU virtual platform.

In one embodiment, the accessing of the host memory by the PCI device further comprises: the PCI device initiates access to host memory through IOMMU page tables or directly.

In one embodiment, the processor employs the X86 architecture.

In a second aspect, an access address tracking device for a PCI device is provided, including: the host machine comprises a PCI bus, a host memory hung on the PCI bus, a virtual host and a log module; the PCI equipment is hung on the PCI bus and transparently transmitted to the virtual host, so that the access of the PCI equipment to the host memory is converted into an access request to the virtual memory of the virtual host; the virtual memory of the virtual host is configured to be in a non-read-write mode, and a first callback function and a second callback function are registered in the virtual host; the virtual host is configured for: responding to an access request of the PCI equipment to the virtual memory, calling a first callback function to execute: recording an access address corresponding to the access request to generate a tracking log, configuring the virtual memory into a read-write mode, and executing an access operation on the access address; after the access operation is completed, calling a second callback function to reconfigure the virtual memory into a non-read-write mode; the log module is used for receiving the tracking log.

In a third aspect, an apparatus is provided, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform: the method of the first aspect.

In a fourth aspect, there is provided a computer readable storage medium storing a program which, when executed by a multicore processor, causes the multicore processor to perform the method of the first aspect.

The embodiment of the application adopts at least one technical scheme which can achieve the following beneficial effects: in this embodiment, each time the PCI device initiates an access to the host memory, the address of the access is recorded, so that the function of tracking and recording the address of the host memory access by the PCI device is realized.

It should be understood that the above description is only an overview of the technical solutions of the present invention, so as to clearly understand the technical means of the present invention, and thus can be implemented according to the content of the description. In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

The advantages and benefits described herein, as well as other advantages and benefits, will be apparent to those of ordinary skill in the art upon reading the following detailed description of the exemplary embodiments. The drawings are only for purposes of illustrating exemplary embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like elements throughout. In the drawings:

FIG. 1a is a schematic diagram illustrating a PCI device accessing a host memory of a host in the prior art;

FIG. 1b is a schematic diagram of an access address tracking device of a PCI device according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for tracking an access address of a PCI device according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a method for tracking an access address of a PCI device according to another embodiment of the present invention;

fig. 4 is a schematic structural diagram of an access address tracking device of a PCI device according to another embodiment of the present invention.

In the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the description of the embodiments of the present application, it is to be understood that terms such as "including" or "having" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

A "/" indicates an OR meaning, for example, A/B may indicate A or B; "and/or" herein is merely an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless otherwise specified.

All code in this application is exemplary and variations will occur to those skilled in the art based upon the programming language used, the specific needs and personal habits without departing from the spirit of the application.

For clarity of explanation of the embodiments of the present application, some concepts that may appear in subsequent embodiments will first be described.

Description of the concept:

the PCI device refers to a device conforming to the PCI bus standard, and the PCI bus architecture may include a plurality of PCI devices, and the host may access available resources of the PCI device through the PCI bus.

QEMU (Quick simulator) Virtual platform, which is a Virtual operating system simulator that simulates CPU through dynamic binary translation and provides a set of device models that enable it to run multiple unmodified guest OSs (operating systems), can be built into KVM (Kernel-based Virtual Machine)

Open source virtualization techniques in (c) to run the virtual machine close to the local speed.

The SIGSEGV signal, which is a signal commonly found in Linux systems, is generated when an illegal access of a reasonable address or access to unallocated memory or an unauthorized memory area.

The sigrap signal, which is a signal commonly used in debugging, is generated by a breakpoint instruction or other trap (trap) instruction.

And a non-readable and writable mode, i.e. a mode in which the memory address is not readable and writable.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1a is a schematic structural diagram of a PCI device accessing a host memory in the prior art, where the PCI device directly accesses the host memory (i.e., the host physical memory) through mechanisms such as IOMMU and SMMU, and an error address access generally does not exist in the access process by default, but a kernel error occurs when the PCI device accesses an invalid host memory address. At this time, a PCIe protocol analyzer is required to analyze the access to the physical memory of the host, and the analysis process is complicated and inefficient.

Fig. 1b is a schematic structural diagram of a hardware operating environment according to an embodiment of the present invention, where the hardware operating environment includes a host and a PCI device connected to the host, where the host includes a PCI bus, a host memory attached to the PCI bus, a virtual host installed on the host, and a log module, where the virtual host is provided with a virtual memory, and the PCI device is attached to the PCI bus and transparently transmits the PCI device to the virtual host, so that an access of the PCI device to the host memory is converted into an access request to the virtual memory of the virtual host, and the log module is used to obtain a generated tracking log.

It should be noted that fig. 1b may be a schematic structural diagram of a hardware operating environment of an access address tracking device of a PCI device. The access address tracking device of the PCI device of the embodiment of the invention can be a terminal device such as a PC, a portable computer and the like.

Those skilled in the art will appreciate that the access address tracking device architecture of the PCI device shown in fig. 1 is not intended to be limiting and may include more or fewer components than shown, or some components may be combined, or a different arrangement of components.

Fig. 2 is a schematic flowchart of an access address tracking method for a PCI device according to an embodiment of the present application, configured to track and record an access address of the PCI device.

As shown in fig. 2, the method provided by the present embodiment may include the following steps 21 to 25:

step 21, transmitting the PCI device to the virtual host, so that the access of the PCI device to the host memory is converted into an access request to the virtual memory of the virtual host;

the transparent transmission means that the PCI equipment is registered in the virtual host machine in a certain mode, so that an operating system of the virtual host machine can directly access the PCI equipment.

Step 22, configuring the virtual memory of the virtual host machine into a non-readable and writable mode, and registering a first callback function and a second callback function in the virtual host machine;

Step 23, in response to the access request of the PCI device to the virtual memory, the operating system generates a first signal for indicating a memory access error;

it is known that when the virtual memory is configured in the unreadable/writable mode, if an access request to the unreadable/writable virtual memory occurs, a memory access error signal, i.e., a first signal, may occur. The first callback function is the callback function of the first signal.

Step 24, the virtual host calls the first callback function in response to the first signal to execute: recording an access address corresponding to the access request to generate a tracking log, configuring the virtual memory into a read-write mode, and executing an access operation on the access address;

and step 25, after the access operation is completed, the virtual host calls a second callback function to reconfigure the virtual memory into the unreadable and writable mode.

In one example, the PCI device may be bound to the VFIO driver such that the operation of the PCI device is exposed from the kernel mode to the user mode, and the PCI device is further passed through to the virtual host in the user mode, thereby converting the address access of the PCI device to the host memory into an access request to the virtual memory of the virtual host. It is understood that, at this time, the host may map a segment of address space in the host memory to the virtual memory of the virtual host (i.e., virtual machine memory space). After the software driver configures the memory address that the PCI device can access, the address of the virtual memory corresponding to the virtual host is configured to be in the unreadable mode, i.e., the unreadable mode, and the first callback function and the second callback function are registered. When the PCI device initiates an address access to the host memory, it will be converted into an access request to the virtual memory of the virtual host, however, at this time, the virtual memory is in the unreadable/writable mode, and it is known that the operating system will generate a memory access error signal, i.e., the first signal at this time. At this time, the virtual host calls a callback function of the first signal, that is, the first callback function. The first callback function is used for executing: recording an access address corresponding to the access request to generate a tracking log, configuring the address of the virtual memory into a read-write mode, and executing the read-write operation. Optionally, the execution sequence of the first, second and third steps can be changed to the second, third, fourth or fifth step. After the execution of the read-write operation is finished, the virtual host calls a second callback function, and the second callback function is used for executing: and reconfiguring the address read-write mode of the virtual memory into the non-read-write mode. Thus, the configuration of the virtual memory can form a cycle from the non-readable and writable mode, the readable and writable mode and the non-readable and writable mode, and when the PCI equipment initiates access to another memory address of the host memory, the 21-25 steps can be executed again, and the memory address is recorded.

By using the scheme provided by this embodiment, when the PCI device initiates an access to the host memory each time, the address of this access is recorded by calling the first callback function, so that the function of tracking and recording the address of the host memory access by the PCI device is realized.

Optionally, the first signal is a SIGSEGV signal. The SIGSEGV signal is a signal that is commonly found in Linux systems and is generated when an illegal access of a legitimate address or access to unallocated memory or an unauthorized memory area. Therefore, when accessing the virtual memory address in the unreadable/writable mode, the operating system receives the SIGSEGG signal.

Optionally, the virtual host is a QEMU virtual platform. The QEMU (Quick simulator) Virtual platform is a Virtual operating system simulator that simulates the CPU through dynamic binary translation and provides a set of device models that enable it to run multiple unmodified guest OSs (operating systems), which can be built into a KVM (Kernel-based Virtual Machine)

Open source virtualization technology) to run virtual machines near local speed.

In some possible embodiments, in order to improve the call correctness and the call efficiency of the second callback function, the method 25 further includes: in response to the execution of the access operation on the access address being completed, the operating system generates a second signal; the virtual host calls the second callback function in response to the second signal.

Optionally, the second signal is a sigrap signal. The SIGTRAP signal is a signal commonly used in debugging that is generated by a breakpoint instruction or other trap (trap) instruction. For example, after some types of processors enter single step mode and complete a single instruction, the SIGTRAP signal may be received by the operating system to indicate a trap exception.

It is understood that the second signal may of course also be other types of signals. For example, a monitoring device may be configured to monitor an access operation of the PCI device to the access address, and automatically generate the second signal after detecting that the access operation is completed.

Fig. 3 is a flowchart illustrating an access address tracking method for a PCI device according to another exemplary embodiment of the present invention, and this embodiment further details the processes of step 24 and step 25 on the basis of the embodiment illustrated in fig. 2.

In some possible embodiments, the performing, in the step 24, the access operation on the access address includes: enabling the processor to be in single-step mode; performing an access operation to the access address in the single step mode.

Based on this, the step 25 may further specifically include: in response to an access operation to the access address in the single step mode being performed, the operating system generating the second signal indicating a trap exception; the virtual host, in response to the second signal, calls the second callback function to perform: reconfiguring the virtual memory into the non-read-write mode; and, causing the processor to exit the single-step mode.

Referring to fig. 3, wherein step 21, step 22, and step 23 are the same as those in the embodiment shown in fig. 2, and are not repeated herein. In this embodiment, after step 23, the method further includes:

step 241, the virtual host, in response to the first signal, calls a first callback function to execute:

a. recording an access address corresponding to the access request to generate a tracking log; b. configuring the virtual memory into a read-write mode; c. enabling the processor to be in single step mode; d. executing an access operation to the access address;

Step 251, in response to the completion of the access operation on the access address, the operating system generates a second signal for indicating trap exception;

step 252, the virtual host, in response to the second signal, calls a second callback function to execute:

e. reconfiguring the virtual memory into a non-readable and writable mode; f. causing the processor to exit single step mode.

Thus, in step 241, the virtual host calls the first callback function to execute c, enables the processor to be in single step mode, and then executes a single step operation d, executes an access operation to the access address; in step 251, it is known that a trap occurs in the operating system after the single-step operation d is completed, and the operating system generates a trap exception signal, i.e. a second signal; in step 252, the virtual host invokes a callback signal of the second signal, i.e., the second callback signal. The second callback signal is used to reconfigure the virtual memory to a non-read-write mode, and furthermore, to cause the processor to exit the single-step mode to ensure the execution of subsequent tasks.

In this embodiment, the trap exception signal is used as the second signal, and the single-step mode and the single-step operation are set in the first callback function to generate the second signal, so that the loop generation of the second signal can be ensured through the smart logic setting, and the single-step mode is released in the callback function of the second signal, so that the processor can form an ordered loop from the non-single-step mode to the single-step mode, and when the PCI device initiates an access to another memory address of the host memory, the steps shown in fig. 3 can be executed again.

Alternatively, the execution order of a and b may be interchanged, and the execution order of e and f may be interchanged.

Optionally, the processor employs an X86 architecture. It is known that the X86 architecture provides that a trap (trap) signal is automatically generated after the processor is in the single-step mode and performs the single-step operation, so that the trap signal can be used as the second signal in the present embodiment without additionally writing the relevant code of the second signal. Of course, other architectures of the processor may be adopted, and in this case, the generation mechanism of the second signal may be additionally provided.

In some possible embodiments, in order to more conveniently pass through the PCI device to the virtual host, the step 21 may specifically include: the PCI device is transparently passed to the Virtual host by binding the PCI device to a VFIO (Virtual Function I/O) driver. It is known that VFIO drivers are a framework that can safely expose device I/O, interrupts, DMA, etc. to user space, so that device drivers can be completed in user space.

Thus, for the PCI device (FPGA/Chip), the VFIO driver is bound to the PCI device, so that the operation of the PCI device can be exposed to a user mode from a kernel mode, the PCI device can be registered in a virtual host of the user mode at the moment, and an operating system of the virtual host can directly access the PCI device.

Alternatively, other types of drivers may be used as long as they can expose the PCI device from the kernel mode to the user mode, and the present application does not limit this to any specific limitation.

In some possible embodiments, the accessing of the host memory by the PCI device further includes: the PCI device initiates access to the host memory through IOMMU page tables or directly.

In the description of the present specification, reference to the description of the terms "some possible implementations," "some embodiments," "examples," "specific examples," or "some examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

With regard to the method flow diagrams of embodiments of the present application, certain operations are described as different steps performed in a certain order. Such flow diagrams are illustrative and not restrictive. Certain steps described herein may be grouped together and performed in a single operation, certain steps may be separated into sub-steps, and certain steps may be performed in an order different than presented herein. The various steps shown in the flowcharts may be implemented in any way by any circuit structure and/or tangible mechanism (e.g., by software running on a computer device, hardware (e.g., logical functions implemented by a processor or chip), etc., and/or any combination thereof).

Based on the same technical concept, an embodiment of the present invention further provides an access address tracking device for a PCI device, which is used to execute the access address tracking method for the PCI device provided in any of the embodiments. Fig. 1b is a schematic structural diagram of an access address tracking device of a PCI device according to an embodiment of the present invention.

As shown in fig. 1b, the apparatus comprises: the host machine comprises a PCI bus, a host memory hung on the PCI bus and a virtual host; the PCI equipment is hung on the PCI bus and transparently transmitted to the virtual host, so that the access of the PCI equipment to the host memory is converted into an access request to the virtual memory of the virtual host;

the virtual memory of the virtual host is configured to be in a non-read-write mode, and a first callback function and a second callback function are registered in the virtual host; the virtual host is configured to: in response to the access request of the PCI equipment to the virtual memory, calling the first callback function to execute: recording an access address corresponding to the access request, configuring the virtual memory into a read-write mode, and executing an access operation on the access address; and after the access operation is executed, calling the second callback function to reconfigure the virtual memory into the unreadable and writable mode.

It should be noted that, the access address tracking device of the PCI device in the embodiment of the present application may implement each process of the foregoing embodiment of the access address tracking method of the PCI device, and achieve the same effect and function, which is not described herein again.

Fig. 4 is an access address tracking device of a PCI device according to an embodiment of the present application, configured to execute the method shown in fig. 2, where the apparatus includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the above embodiments.

According to some embodiments of the present application, there is provided a non-transitory computer storage medium of an access address tracking method of a PCI device having stored thereon computer-executable instructions configured to, when executed by a processor, perform: the method as described in the above example.

The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, device, and computer-readable storage medium embodiments, the description is simplified because they are substantially similar to the method embodiments, and reference may be made to some descriptions of the method embodiments for their relevance.

The apparatus, the device, and the computer-readable storage medium provided in the embodiment of the present application correspond to the method one to one, and therefore, the apparatus, the device, and the computer-readable storage medium also have advantageous technical effects similar to those of the corresponding method.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. Moreover, while the operations of the method of the invention are depicted in the drawings in a particular order, this does not require or imply that the operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

While the spirit and principles of the invention have been described with reference to several particular embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, nor is the division of aspects, which is for convenience only as the features in such aspects may not be combined to benefit. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An access address tracking method of a PCI device, comprising:

the PCI equipment is transmitted to a virtual host machine in a transparent mode, so that the access of the PCI equipment to a host machine memory of the host machine is converted into an access request to a virtual memory of the virtual host machine;

configuring a virtual memory of the virtual host machine into a non-readable and writable mode, and registering a first callback function and a second callback function in the virtual host machine;

responding to an access request of the PCI equipment to the virtual memory, and generating a first signal for indicating a memory access error by an operating system;

the virtual host, in response to the first signal, calls the first callback function to perform: recording an access address corresponding to the access request to generate a tracking log, configuring the virtual memory into a read-write mode, and executing an access operation on the access address;

After the access operation is completed, the virtual host calls the second callback function to reconfigure the virtual memory into the unreadable and writable mode.

2. The method of claim 1, wherein after the access operation is completed, the virtual host calls the second callback function to reconfigure the virtual memory to the unreadable and writable mode, further comprising:

in response to the execution of the access operation on the access address being completed, the operating system generates a second signal;

the virtual host calls the second callback function in response to the second signal.

3. The method of claim 2,

the executing the access operation to the access address comprises: enabling the processor to be in single step mode; performing an access operation to the access address in the single step mode; and the number of the first and second groups,

the method further comprises the following steps:

in response to an access operation to the access address in the single step mode being performed, the operating system generating the second signal indicating a trap exception;

the virtual host, in response to the second signal, calls the second callback function to perform: reconfiguring the virtual memory into the non-read-write mode; and, causing the processor to exit the single-step mode.

4. The method of claim 1, wherein passing the PCI device through to the virtual host further comprises:

the PCI device is transparently passed to the virtual host by binding the PCI device to a VFIO driver.

5. The method of claim 1, wherein the first signal is a SIGSEGVGV signal.

6. The method of claim 2, wherein the second signal is a sigrap signal.

7. The method of claim 1, wherein the virtual host is a QEMU virtual platform.

8. The method of claim 1, wherein the accessing of the host memory by the PCI device further comprises:

the PCI device initiates access to the host memory through IOMMU page tables or directly.

9. The method of claim 3, wherein the processor employs an X86 architecture.

10. An access address tracking device of a PCI device, the device configured to perform the method of any of claims 1-9, comprising:

the host machine comprises a PCI bus, a host memory hung on the PCI bus, a virtual host and a log module;

The PCI equipment is hung on the PCI bus and is transmitted to the virtual host, so that the access of the PCI equipment to the host memory is converted into an access request to the virtual memory of the virtual host;

the virtual memory of the virtual host is configured to be in a non-read-write mode, and a first callback function and a second callback function are registered in the virtual host; the virtual host is configured to: in response to the access request of the PCI equipment to the virtual memory, calling the first callback function to execute: recording an access address corresponding to the access request to generate a tracking log, configuring the virtual memory into a read-write mode, and executing an access operation on the access address; after the access operation is executed, calling the second callback function to reconfigure the virtual memory into the unreadable and writable mode;

the log module is used for receiving the tracking log.

11. An access address tracking device of a PCI device, comprising:

at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform: the method of any one of claims 1-9.

12. A computer-readable storage medium storing a program that, when executed by a multi-core processor, causes the multi-core processor to perform the method of any of claims 1-9.