CN114064138A - Method for starting system including multi-core processor and system adopting same - Google Patents
Method for starting system including multi-core processor and system adopting same Download PDFInfo
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Abstract
The present disclosure relates to a startup method of a system including a multicore processor and a system employing the method. There is provided a startup method of a system including a multi-core processor, including: initializing a peripheral and a memory by a main core of the multi-core processor; reading a plurality of sub-image files from the peripheral to the memory; respectively executing processing, including decompression, checksum \ or decryption, on the plurality of sub-mirror image files by a master core and at least one slave core of the multi-core processor, or by a plurality of slave cores, so as to obtain a plurality of processed sub-mirror image files, wherein the plurality of processed sub-mirror image files are spliced into one or more image files for starting a system; and awakening the slave core by the master core and loading the one or more image files to enter multi-core scheduling so as to complete the starting of the system.
Description
Technical Field
The present disclosure relates to processor-related technologies, and in particular, to boot techniques for systems including multi-core processors.
Background
With the development of processor technology, the application range of the multi-core processor is wider and wider. The basic characteristic of the multi-core processor is that a plurality of cores run on the same software operating system, share hardware and software resources and receive a uniform task scheduling strategy. The Multi-core processor referred to herein is, for example, SMP (Symmetric Multi-processor), HMP (dual, lightweight model of ARM, termed Heterogeneous Multi-Processing). The "core" may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a single chip Processor (scm), or the like. Based on this, the multi-core processor can not only process a plurality of tasks in parallel to enhance the system performance, but also has lower power consumption than the single-core processor. From the aspect of software, most of the existing programs for the single-core processor can be operated on the multi-core processor without modification, so that the convenience of adopting the multi-core processor is greatly improved.
However, existing boot methods for systems including multi-core processors are typically slow or require the consumption of additional hardware resources to speed up. If the system comprising the multi-core processor has high requirements on real-time performance and hardware cost, the existing starting method cannot meet the requirements.
Accordingly, there is a need for an improved boot method for a system including a multicore processor.
Disclosure of Invention
In order to improve the starting method of a system including a multi-core processor, the inventors of the present application propose the following technical idea: the original image file is divided, then in the starting process of a system comprising a multi-core processor, more cores are enabled to participate in decompression, verification and decryption of the divided image file in parallel by utilizing the processing capacity of a plurality of cores (comprising a main core and a secondary core) and special instructions (such as encryption/decryption instructions, verification algorithm instructions and the like), and finally the starting speed of the whole system is improved.
Specifically, according to one aspect of the present disclosure, there is provided a startup method of a system including a multicore processor, including: initializing a peripheral and a memory by a main core of the multi-core processor; reading a plurality of sub-image files from the peripheral to the memory; respectively executing processing, including decompression, checksum \ or decryption, on the plurality of sub-mirror image files by a master core and at least one slave core of the multi-core processor, or by a plurality of slave cores, so as to obtain a plurality of processed sub-mirror image files, wherein the plurality of processed sub-mirror image files are spliced into one or more image files for starting a system; and awakening the slave core by the master core and loading the one or more image files to enter multi-core scheduling so as to complete the starting of the system.
According to another aspect of the present disclosure, there is provided a system including a multi-core processor that performs a boot method of the system including the multi-core processor according to the present disclosure.
The inventor of the application proposes the improved starting method aiming at the problems of insufficient computing capability and low starting speed caused by only using a single core in the starting process, and the improved starting method fully utilizes the computing capability (decompression capability, verification capability and decryption capability) of a plurality of cores of a multi-core processor to realize parallel operation so as to accelerate the starting speed of a system.
Other features of the present disclosure and advantages thereof will become more apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
FIG. 1 schematically shows a flow diagram of a method of booting a system including a multicore processor, according to an embodiment of the present disclosure;
FIG. 2 schematically illustrates a method of partitioning an image file;
FIG. 3 schematically illustrates another method of splitting an image file;
FIG. 4 schematically illustrates yet another image file splitting method;
FIG. 5 illustrates a flow diagram of one particular example of a boot method of the system including a multicore processor shown in FIG. 1.
Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In some cases, similar reference numbers and letters are used to denote similar items, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.
For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like.
Detailed Description
Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the structures and methods herein are shown by way of example to illustrate different embodiments of the structures and methods of the present disclosure. Those skilled in the art will understand, however, that they are merely illustrative of exemplary ways in which the disclosure may be practiced and not exhaustive. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
In a conventional starting process of a system including a multi-core processor, one core is usually selected as a main core according to an ID number of the core to take charge of loading and starting of the whole system, and then other sleeping slave cores are awakened at an appropriate time of starting, so that the whole system finally enters a normal multi-core state.
However, in some systems with high real-time requirements, especially in the embedded field with strict requirements for the start-up time from power-on to normal operation, the start-up process cannot meet the requirements. The loading of the whole system not only needs to transport the image file from the peripheral to the memory, but also needs to decompress and check the image file, and even needs to decrypt the image file under the application scene with the safe starting requirement. Compared with reading the image file into the memory, the decompression, verification and decryption processing of the image file takes more time, and in the existing starting method of the system including the multi-core processor, the above process is completed by only one core (usually, a main core) among a plurality of cores of the multi-core processor, and the hardware resources of the plurality of cores are not fully utilized. In an existing system-on-chip adopting a multi-core processor architecture, a designer often introduces a hardware acceleration module into the multi-core processor architecture to shorten the starting time in order to accelerate the starting speed, for example, an IP module such as hardware decompression, hardware decryption and the like is added into the chip, which can accelerate the starting speed, but significantly increases the chip design and use cost.
The inventors of the present application have appreciated that the boot process may be accelerated by invoking more cores during the boot process of a system including a multicore processor, while avoiding the introduction of additional hardware resources.
FIG. 1 schematically shows a flow diagram of a method of booting a system including a multicore processor, according to an embodiment of the present disclosure.
As shown in fig. 1, a startup method 100 of a system including a multicore processor according to an embodiment of the present disclosure may include: initializing peripherals and a memory by a main core of the multi-core processor (step 110); reading a plurality of sub-image files from the peripheral to the memory (step 120); respectively executing processing including but not limited to decompression, checksum \ or decryption processing by a master core and at least one slave core of the multi-core processor, or a plurality of slave cores to a plurality of (greater than or equal to 2) sub-mirror files to obtain a plurality of processed sub-mirror files, and splicing the plurality of processed sub-mirror files into one or more mirror files for starting the system (step 130); and awakening the slave core by the master core and loading the one or more image files to enter the multi-core scheduling so as to complete the starting of the system (step 140).
Those skilled in the art will appreciate that in embodiments consistent with the present disclosure, processing of a child image file may be accomplished by a master core and at least one slave core, or may be accomplished by only a plurality of slave cores. The slave cores participating in the processing of the sub-image file may include all the slave cores of the multi-core processor, or may include a part of all the slave cores of the multi-core processor. In some embodiments of the present disclosure, the number of sub-mirror files may be equal to the number of cores (e.g., CPU cores) used to process the sub-mirror files. For example, if the number of cores for processing the sub-image file is N, the number of sub-image files is M, and N and M are positive integers greater than 1, where N = M, then one sub-image file may be processed per core (e.g., CPU core). In still other embodiments of the present disclosure, the number of cores used to process the sub-mirror file may be less than the number of sub-mirror files. For example, the number of the cores for processing the sub-image files is N, the number of the sub-image files is M, both N and M are positive integers greater than 1, where N < M, then a core is set to process more than one sub-image file. Of course, whether to process a plurality of sub-image files is set in relation to the own processing capability of a certain core. For example, each sub-image file is equal or approximately equal in size, and if a core has a processing capacity greater than that of other cores, the core may be configured to process 2 or 3 sub-image files, as the case may be. Alternatively, each of the sub-mirror files may have different sizes, and the size of the combined 2 or 3 files may be equal to or approximately equal to the size of the other files. Here, 2 files or 3 files are for illustration only. In the embodiment of the present disclosure, the setting of the master core and the slave core is also not unique, and may be set and selected as needed, that is, the master core in a certain scene may become the slave core in another scene, and similarly, the slave core may also become the master core.
One typical example of a system including a multicore processor is a system on a chip (SOC). The system on chip is integrated with: a multi-core processor as an operating core, a memory as a peripheral to the multi-core processor, and a bus that communicates the multi-core processor with the memory as the peripheral.
In an embodiment according to the present disclosure, the peripheral is a memory provided independently of the multicore processor. To prevent loss, the sub-image file is typically stored in a peripheral non-volatile storage medium, such as an SD Card, an embedded Multimedia Card (eMMC), Flash memory (Flash), or the like. The memory is part of a multi-core processor that serves as a storage medium to support the operation of multiple cores of the multi-core processor, which may be, for example, a double data rate synchronous dynamic random access memory (DDR).
In embodiments according to the present disclosure, Multi-core processors include, but are not limited to, SMP (Symmetric multiprocessors) and HMP (big-graph model of ARM, termed Heterogeneous multiprocessing mode). The method of booting a system including a multi-core processor according to the present disclosure is applicable to booting a system including an SMP as well as to booting a system including an HMP.
In a multi-core processor, the core may include a processor having an arithmetic capability, such as a CPU, a DSP, a single chip, and the like. The plurality of cores can be divided into a master core and a slave core, wherein the master core can be generally selected and initialized by a boot loader and is responsible for managing the operation of other slave cores. In a symmetric multiprocessor, the master core may be a specifically designated core, or may be any one of the cores.
In embodiments according to the present disclosure, the image file may support many functions, including but not limited to: memory management, peripheral drivers, system scheduling, file systems, and upper complex applications, etc. Common types of image files include, for example, operating system images and file system images. In order to prevent power loss, these image files are generally stored in a non-volatile storage medium of the peripheral device, such as an SD card, eMMC, Flash. The image file is usually large, and can reach 5M bytes, dozens of M bytes to dozens of M bytes, etc. under the uncompressed condition. Because the image file is large but the reading speed of the peripheral interface is limited, the image file is usually compressed and then stored in the peripheral, so that the time spent on reading the image file from the peripheral is saved. However, after the compressed image file is read into the memory, the decompression algorithm needs to spend a lot of processor power, and the existing starting method can spend a lot of time in this step, which slows down the starting speed of the system. According to the starting method of the system comprising the multi-core processor, the compressed image file is processed by adopting the plurality of cores, so that the decompression flow is greatly shortened, and the starting speed of the system is accelerated.
In the implementation of the present disclosure, the checking process of the image file refers to checking the file through a certain checking algorithm (such as checkSum, CRC, etc.) to ensure that the loaded image file is correct. The verification process also consumes startup time. According to the startup method of the system including the multi-core processor of the present disclosure, the time required for verification is shortened by simultaneously verifying each sub-image file using a plurality of cores.
In the implementation of the present disclosure, the decryption process of the image file refers to verifying the security of the file through a certain decryption algorithm, otherwise, the image file is not started. Systems including multi-core processors are increasingly complex in application environments, and for self-security considerations, security of authentication files needs to be considered to prevent interference from malicious third parties. Taking the field of intelligent robots as an example, in order to prevent a user from maliciously destroying original contents, a certain decryption algorithm is required to ensure that codes in a file are original programs of a manufacturer in the starting process, otherwise, the file is not started, which is called as a safe starting environment. In terms of decryption algorithms, whether symmetric decryption or asymmetric decryption, the essence is to use very complex algorithms to secure data, and thus a great deal of computation power and computation time is required. The startup method of a system including a multi-core processor according to the present disclosure shortens the time required for security verification by simultaneously performing a decryption operation on each of the sub-image files using a plurality of cores.
In an embodiment according to the present disclosure, the performing, by the master core and the at least one slave core of the multi-core processor, or the plurality of slave cores, the processing of the plurality of sub-image files, respectively, including decompressing, checking and \ or decrypting, to obtain the plurality of processed sub-image files may include: the method comprises the following steps that a main core and at least one slave core are adopted, or the plurality of slave cores comprise N cores, wherein N is a positive integer larger than 1; each image file in the one or more image files comprises M file segments (for example, the image file can be divided into M file segments), and the M file segments can be processed, including compression, checksum \ or encryption, to obtain M sub image files, wherein the M file segments have the same or different sizes, and M is a positive integer greater than 1; and respectively executing processing on the M sub image files of each image file by the N cores to obtain M processed sub image files.
Fig. 2 schematically shows a method for splitting an IMAGE file, which is used to split an IMAGE file IMAGE _ 1. As shown in fig. 2, IMAGE file IMAGE _1 is divided into M file segments, segment _1, segment _2, segment _3, and … segment _ M, which are the same or different in size. Next, each file segment is compressed, checked and/or encrypted to obtain corresponding SUB-mirror files SUB _1, SUB _2, SUB _3, … SUB _ M.
In the embodiment according to the present disclosure, the sub-image files of corresponding sizes may be prepared according to the strength of the computing power of each core, so as to ensure that the time required by each core to complete the processing of the sub-image files is as close as possible, thereby improving the starting efficiency of the whole system. In some embodiments, the multi-core processor is a symmetric multiprocessor, and the N cores have substantially the same arithmetic capability, in which case the image file may be divided into a plurality of file segments of substantially equal size. In still other embodiments, if a core has a relatively strong computing power, the file segment corresponding to the sub-image file to be processed by the core is divided into relatively large segments; the other core has a weaker computing power, and the file segment corresponding to the sub-image file to be processed by the core is divided into smaller segments. In other embodiments, although the multi-core processor is a symmetric multiprocessor, the computing power of the N cores is substantially the same, but the computing power of the master core that can be used for processing the sub-image file is lower than that of the slave core because the master core additionally performs other operations. In this case, the file section corresponding to the sub-mirror file to be processed by the master core may be divided small, and the file section corresponding to the sub-mirror file to be processed by each slave core may be divided large. Those skilled in the art will appreciate that the size of the file segments can be designed arbitrarily, depending on the application requirements.
Through the process shown in FIG. 2, one IMAGE file IMAGE _1 is split into M sub-IMAGE files that are stored in a peripheral of a system including a multi-core processor. When a system including a multi-core processor is started, the M sub-IMAGE files are loaded into a memory, and the IMAGE file IMAGE _1 is finally obtained by performing decompression, checksum \ or encryption and decryption processing on the M sub-IMAGE files by using N cores, where the N cores include a master core and N-1 slave cores, or include N slave cores. For a system requiring a plurality of image files in the boot process, the above-described process flow may be performed for each of the plurality of image files. Specifically, each image file is divided into M sub-image files, and in the starting process, N checks are firstly used for executing decompression, verification processing and/or decryption processing on the M sub-image files of one image file so as to obtain the image file; and then the N checks are used for performing decompression, verification processing and/or decryption processing on the M sub image files of the next image file so as to obtain the next image file, and the like until all the image files are obtained.
In some example embodiments, the performing, by the master core and the at least one slave core of the multi-core processor, or the plurality of slave cores, the processing of the plurality of sub-image files, respectively, including decompressing, checking and \ or decrypting, to obtain the plurality of processed sub-image files may include: the method comprises the following steps that a main core and at least one slave core are adopted, or the plurality of slave cores comprise N cores, wherein N is a positive integer larger than 1; the one or more image files comprise a total of M file segments (e.g., may be divided into a total of M file segments), which can be processed, including compressed, checksum \ or encrypted, to obtain M sub-image files, wherein the M file segments are the same or different in size, and M is a positive integer greater than 1; the N cores respectively perform processing on the M sub-image files to obtain M processed sub-image files.
Fig. 3 schematically illustrates another IMAGE file splitting method for splitting two IMAGE files IMAGE _1 and IMAGE _ 2. As shown in fig. 3, IMAGE file IMAGE _1 is divided into a file segments separation _1 … separation _ a, where a is a positive integer smaller than M, and each file segment is compressed, checked and/or encrypted to obtain a corresponding a SUB IMAGE file SUB _1 … SUB _ a. The a file segments may be the same size or different sizes. Next, IMAGE file IMAGE _2 is divided into (M-a) file segments, i.e., segment _ a +1 … segment _ M, and each file segment is compressed, checked, and/or encrypted to obtain a corresponding (M-a) SUB-IMAGE file SUB _ a +1 … SUB _ N. The (M-a) file extents are the same size or different sizes. Based on the splitting method shown in fig. 3, the two IMAGE files IMAGE _1 and IMAGE _2 are split into a total of M file segments. In this case, each sub-image file includes at least a portion of the contents of one image file.
For another example, multiple image files may be spliced into a whole file, multiple files may be simply merged together end to end, or after inserting a separating character into the head and/or tail of multiple files. Thereafter, the total file is divided into M file segments. And respectively executing compression, checksum \ or encryption processing on each file section in the M file sections to obtain a corresponding sub-image file. In this case, there may be at least one sub-image file comprising partial contents of two image files, the sub-image file corresponding to a file section at the splice, including both partial contents of the file end of the previous file and partial contents of the file header of the next file.
Fig. 4 schematically illustrates yet another IMAGE file splitting method for splitting two IMAGE files IMAGE _1 and IMAGE _ 2. As shown in fig. 4, the IMAGE files IMAGE _1 and IMAGE _2 are first spliced into one TOTAL file IMAGE _ TOTAL. Next, the TOTAL file IMAGE _ TOTAL is divided into M file segments, i.e., file segments — 1 … file segments — b … file segments — M, wherein b is a positive integer smaller than M, and each file segment is compressed, checked and/or encrypted to obtain a corresponding SUB-IMAGE file SUB _1 … SUB _ b … SUB _ M. The size of the M file sections may be the same or different. As shown in fig. 3, the file segment separation _ b corresponding to the SUB IMAGE file SUB _ b includes both the content of the tail of the IMAGE file IMAGE _1 and the content of the head of the IMAGE file IMAGE _1, that is, includes partial contents of two IMAGE files.
In an embodiment according to the present disclosure, the process of splitting and processing the image file to obtain the sub-image file may be performed by an electronic device (such as, for example, a software tool on a PC side) other than the system including the multi-core processor, and stored in a peripheral of the system including the multi-core processor by the electronic device.
In some embodiments according to the present disclosure, the step of reading the plurality of sub-image files from the peripheral device into the memory may be performed by the primary core. For example, when a unified peripheral interface (such as SPI, Flash, SDIO, etc.) is used to load each sub-image from the peripheral into the memory, the process of reading the sub-image file can be performed using only the master core, because the speed of these interfaces is much slower than the running speed of the core, and using only the master core not only does not delay the speed of reading, but also saves power.
In other embodiments according to the present disclosure, the step of reading the plurality of sub-image files from the peripheral device into the memory may be performed by the master core and the plurality of slave cores. For example, when the peripheral device includes a plurality of peripheral storage devices and a plurality of sub-image files are stored in the plurality of peripheral storage devices, respectively, each of the master core and the plurality of slave cores may read the sub-image file from a corresponding one of the plurality of peripheral storage devices to improve reading efficiency. For example, when the child image file of the kernel image is stored in the embedded eMMC and the child image file of the file system is stored in the Flash memory, the master core and one slave core may be used to read the corresponding child image file from the eMMC and the Flash, respectively.
When a processing flow of a sub-mirror image file is completed by using a master core and at least one slave core, or a plurality of slave cores together, the cores need to be managed reasonably to improve the operating efficiency of the system. In an embodiment consistent with the present disclosure, an IMAGEREADY flag bit may be set in memory, the IMAGEREADY flag bit being set in response to completing reading of a plurality of sub-image files from a peripheral into memory. In this case, the startup method of the system including the multicore processor further includes: polling an IMAGEREADY flag bit in memory by the at least one slave core or the plurality of slave cores; and in response to IMAGEREADY setting the flag bit, the master core and at least one slave core, or multiple slave cores, respectively, start to perform decompression, checksum \ or decryption processing on multiple sub-mirror files.
Furthermore, a plurality of imageone flag bits corresponding to a master core and at least one slave core or a plurality of slave cores for performing processing on the child image file may be set in the memory, and each imageone flag bit is set in response to the completion of the decompression, checksum \ or decryption processor of the corresponding child image file by the corresponding one of the master core and the at least one slave core or the plurality of slave cores. In this case, the startup method of the system including the multicore processor further includes: polling a plurality of IMAGEDONE zone bits in a memory by a main core; and responding to the setting of all the IMAGEDONE zone bits, skipping the main core to the mirror image entry address, awakening each slave core, loading one or more mirror image files, and entering multi-core scheduling to finish the starting of the system.
Aiming at the problem of low starting speed of a system comprising a multi-core processor caused by loading, decompressing, checking and decrypting all image files by using a single core in the starting process, the starting method provided by the disclosure fully utilizes the hardware resources of the existing multiple cores and distributes the work of decompressing, checking and decrypting to all idle cores to do, thereby not only improving the starting speed of the system, but also avoiding introducing extra hardware to accelerate the starting, and improving the starting speed of the system comprising the multi-core processor while not increasing the design and use cost.
FIG. 5 illustrates a flow diagram of one particular example of a boot method of the system including a multicore processor shown in FIG. 1. In this particular example, the system is a system on a chip that includes a multicore processor and a peripheral. The boot method illustrated in FIG. 5 contains many details for a more detailed presentation of the boot method of a system including a multicore processor as set forth in the present disclosure, but those skilled in the art will appreciate that these details are for illustration only and are not intended to be limiting.
As shown in fig. 5, a startup method 200 of a system including a multicore processor according to one specific example of the present disclosure may include the steps of:
step S210: the peripheral stores M sub-image files, and in the embodiment of the present disclosure, the number of the cores participating in the processing of the sub-image files in the multi-core processor is N. It should be understood by those skilled in the art that the number M of the sub-mirror files is not necessarily equal to the number N of the cores participating in the processing of the sub-mirror files, and the specific description may be referred to the description of the foregoing embodiments. The M sub image files are obtained in the following mode: dividing an image file required by system startup into M file sections, and respectively performing compression, verification and encryption processing on each file section to obtain corresponding M sub-image files;
step S220: the system on chip is electrified, a boot loader is executed to start a main core of the multi-core processor, and the main core initializes the peripheral equipment;
step S230: carrying M sub-image files in the peripheral to a memory of a multi-core processor, wherein in the process, a slave core of N cores (including a master core and a slave core) participating in sub-image file processing continuously polls IMAGEREADY flag bits in the memory and waits for entering the next stage;
step S240: when the M sub image files are completely carried, IMAGEREADY is set by the main core. After the flag bit is set in polling to IMAGEREADY, each slave core and the master core respectively perform decompression, check and decryption processing on the corresponding sub-image file, and store the result to the corresponding position in the memory. After each slave core completes corresponding processing, a corresponding flag bit IMAGEDONE which indicates the execution end of the slave core in the memory is set, and then the slave core is restored to a dormant state to wait for further awakening.
Step S250: and when the main core detects that all the zone bits IMAGEDONE are set, jumping to a mirror image entry address to start execution, awakening the slave core in the starting process, and entering multi-core scheduling until the system on the chip is started.
According to the present disclosure, there is also provided a system comprising a multi-core processor for performing the boot method as described in the foregoing.
The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.
As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or element tolerances, environmental influences and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in a practical implementation.
In addition, the foregoing description may refer to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element \ node \ feature is electrically, mechanically, logically, or otherwise directly connected to (or in direct communication with) another element \ node \ feature. Similarly, unless expressly stated otherwise, "coupled" means that one element \ node \ feature may be mechanically, electrically, logically or otherwise coupled to another element \ node \ feature in a direct or indirect manner to allow interaction, even though the two features may not be directly connected. That is, to "couple" is intended to include both direct and indirect joining of elements or other features, including connection with one or more intermediate elements.
In addition, "first," "second," and like terms may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.
It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.
In the present disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing \ manufacturing," "arranging \ setting," "installing \ assembling," and \ or "ordering" the object, and the like.
Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (13)
1. A method of booting a system including a multi-core processor, comprising:
initializing a peripheral and a memory by a main core of the multi-core processor;
reading a plurality of sub-image files from the peripheral to the memory;
respectively executing processing, including decompression, checksum \ or decryption, on the plurality of sub-mirror image files by a master core and at least one slave core of the multi-core processor, or by a plurality of slave cores, so as to obtain a plurality of processed sub-mirror image files, wherein the plurality of processed sub-mirror image files are spliced into one or more image files for starting a system; and
and awakening the slave core by the master core and loading the one or more image files to enter multi-core scheduling so as to complete the starting of the system.
2. The method of claim 1, wherein the step of processing the plurality of child image files by the master core and the at least one slave core or the plurality of slave cores of the multi-core processor, respectively, comprises decompressing, checking and/or decrypting to obtain a plurality of processed child image files, comprises:
the master core and at least one slave core, or the plurality of slave cores comprises N cores, wherein N is a positive integer greater than 1;
each image file in the one or more image files comprises M file sections, wherein the M file sections can be processed, including compression, checksum \ or encryption, to obtain M sub-image files, the M file sections are the same or different in size, and M is a positive integer greater than 1; and
and respectively executing processing on the M sub image files of each image file by the N cores to obtain M processed sub image files.
3. The method of claim 1, wherein the step of processing the plurality of child image files by the master core and the at least one slave core or the plurality of slave cores of the multi-core processor, respectively, comprises decompressing, checking and/or decrypting to obtain a plurality of processed child image files, comprises:
the master core and at least one slave core, or the plurality of slave cores comprises N cores, wherein N is a positive integer greater than 1;
the one or more image files comprise a total of M file sections, wherein the M file sections can be processed, including compression, checksum \ or encryption, to obtain M sub-image files, wherein the M file sections have the same or different sizes, and M is a positive integer greater than 1; and
and respectively executing processing on the M sub-image files by the N cores to obtain M processed sub-image files.
4. The method of claim 3, wherein each of the plurality of sub-image files comprises at least a portion of the contents of one of the image files.
5. The method of claim 3, wherein at least one of the sub-image files comprises a portion of the contents of both image files.
6. The method of starting a system including a multicore processor of any of claims 1-5,
and reading a plurality of sub image files from the peripheral equipment into the memory and executing the sub image files by the main core.
7. The method of starting a system including a multicore processor of any of claims 1-5,
and reading a plurality of sub-image files from the peripheral equipment into the memory and executing the sub-image files by the main core and the plurality of slave cores.
8. The method of starting a system including a multicore processor of claim 7,
the peripheral comprises a plurality of peripheral storage devices, and a plurality of sub-image files are respectively stored in the plurality of peripheral storage devices; and
each of the master core and the number of slave cores reads a sub-image file from a respective one of the plurality of peripheral storage devices.
9. The method of starting a system including a multicore processor of any of claims 1-5,
a first zone bit is arranged in the memory, and the first zone bit is set in response to the fact that the reading of the plurality of sub-image files from the peripheral device into the memory is completed;
the starting method of the system comprising the multi-core processor further comprises the following steps:
polling a first flag bit in the memory by the at least one slave core, or the plurality of slave cores, and
in response to the first flag bit being set, the master core and at least one slave core, or the plurality of slave cores, start to perform decompression, checksum \ or decryption processing on the plurality of sub-mirror files, respectively.
10. The method of starting a system including a multicore processor of any of claims 1-5,
a plurality of second flag bits corresponding to the master core and the at least one slave core, or the plurality of slave cores one to one are arranged in the memory, and each second flag bit is set in response to the master core and the at least one slave core, or a corresponding one of the plurality of slave cores completing decompression, checksum \ or decryption processing on a corresponding sub-mirror image file;
the starting method of the system comprising the multi-core processor further comprises the following steps:
polling, by the primary core, the plurality of second flag bits in the memory, an
And responding to the setting of all the second flag bits, jumping to the entry address of the image file by the main core, waking each auxiliary core, loading one or more image files, and entering multi-core scheduling to finish the starting of the system.
11. The method of starting a system including a multicore processor of any of claims 1 to 5, wherein the multicore processor is a symmetric multiprocessor or an ARM heterogeneous multiprocessing mode.
12. Method for booting a system including a multicore processor according to any of claims 1 to 5, characterized in that the system is a system on chip SOC.
13. A system comprising a multicore processor, characterized in that the startup method according to any one of claims 1-12 is performed.
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