CN114063918B

CN114063918B - Data access method, memory storage device and memory controller

Info

Publication number: CN114063918B
Application number: CN202111340766.0A
Authority: CN
Inventors: 刘梓键
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2023-08-15
Anticipated expiration: 2041-11-12
Also published as: CN114063918A

Abstract

The invention provides a data access method, a memory storage device and a memory controller. The method comprises the following steps: establishing a state bitmap of an entity unit, wherein the state bitmap is used for storing management information of the entity unit; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and establishing an entity window table for managing the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is effected according to the logical-to-entity mapping table. Thus, the speed of access of large files and data from the host system to the memory storage devices and memory modules can be significantly increased; the speed of access of large files from the host system to the memory module can be achieved even though the SRAM capacity in the memory storage device and memory module is small.

Description

Data access method, memory storage device and memory controller

Technical Field

The present invention relates to memory management, and more particularly, to a data access method, a memory storage device and a memory controller.

Background

Nonvolatile memory modules, such as flash memory modules, have the advantages of nonvolatile storage of data, low power consumption, and fast data access. For nonvolatile memory modules such as NAND FLASH, there is a corresponding method for bad block management, since the manufacturing process and storage principle determine that bad blocks are necessarily generated during the production process and the use process. However, the conventional management method manages the blocks in units of blocks, and the blocks are discarded as long as there are bad pages in the blocks or the number of bad pages exceeds a limit value. It is known that this management method using blocks as a unit has a problem of low flash memory utilization. With the development of flash memory, the capacity of each block is continuously increased, and the whole block is discarded to generate great waste, so that the management method taking pages as units is very necessary.

Disclosure of Invention

The invention provides a data access method, a memory storage device and a memory controller, which can improve the speed of accessing data from a host system to the memory storage device.

An embodiment of the present invention provides a data access method for a memory storage device, where the memory storage device includes a memory module, the memory module includes at least one physical unit, the physical unit includes a plurality of physical programming units, and the data access method includes: establishing a state bitmap of the entity units, wherein the state bitmap is used for storing management information of the entity units, and the management information comprises the total number of entity programming units of the entity units, the number of entity programming units with valid states and address values of the valid entity programming units in the entity units; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing an entity window table of the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is effected according to the logical-to-entity mapping table.

Optionally, an embodiment of the present invention further provides a memory storage device, including: a connection interface for connecting to a host system; a memory module comprising at least one physical unit; and a memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to establish a status bitmap of the entity units, the status bitmap being configured to store management information of the entity units, the management information including a total number of entity programming units of the entity units, a number of entity programming units in a valid status, and address values of the valid entity programming units in the entity units; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing an entity window table of the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is effected according to the logical-to-entity mapping table.

Optionally, an embodiment of the present invention further provides a memory controller for controlling a memory module, wherein the memory module includes at least one physical unit, and the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; and a memory control circuit connected to the host interface and the memory interface; the memory control circuit is used for establishing a state bitmap of the entity units, the state bitmap is used for storing management information of the entity units, and the management information comprises the total number of entity programming units of the entity units, the number of entity programming units with valid states and address values of the valid entity programming units in the entity units; dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing an entity window table of the entity windows; establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value; access of data from the host system to the memory storage device is effected according to the logical-to-entity mapping table.

Thereby, the speed of accessing the large files and the large data from the host system to the memory storage device and the memory module can be remarkably improved; the speed of access of large files from the host system to the memory module can be achieved even though the SRAM capacity in the memory storage device and memory module is small.

Drawings

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention;

FIG. 2 is a schematic block diagram of a memory controller according to an example embodiment of the invention;

FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention;

FIG. 4 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention;

FIG. 5 is a flow chart of a data access method according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a status bitmap shown in accordance with an embodiment of the present invention;

FIG. 7 is a flow chart illustrating a method of interval value model building according to an embodiment of the present invention;

FIG. 8 is a flow chart illustrating a method of interval value model building according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an entity window table shown in accordance with one embodiment of the present invention;

FIG. 10 is a flow chart illustrating a method of creating a logical-to-physical mapping table according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating mapping of logical physical programmer to corresponding physical programmer according to an embodiment of the invention;

FIG. 12 is a diagram illustrating mapping of "page-by-page" logical physical programming units to corresponding physical programming units according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the present invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. Host system 11 may be any type of computer system. For example. The host system 11 may be a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera, and other electronic systems. The memory storage 12 is used to store data from the host system 11. For example, memory storage 12 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage. The host system 11 may be electrically connected to the memory storage device 12 via a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) interface, a high speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express), a universal serial bus (Universal Serial Bus, USB), or other type of interconnect interface. Thus, host system 11 may store data to memory storage device 12 and/or read data from memory storage device 12.

Memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. Memory storage 12 may communicate with host system 11 via connection interface 121.

The memory module 122 is used to store data. The memory module 122 may include a rewritable nonvolatile memory module. The memory module 122 includes an array of memory cells. The memory cells in the memory module 122 store data in the form of voltages. For example, the memory module 122 may include a single Level Cell (Single Level Cell, SLC) NAND type flash memory module, a Multi Level Cell (MLC) NAND type flash memory module, a third Level Cell (Triple Level Cell, TLC) NAND type flash memory module, a Quad Level Cell (QLC) NAND type flash memory module, or other memory modules having similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 may be used to control the memory storage device 12. For example, the memory controller 123 may control the connection interface 121 and the memory module 122 for data access and data management. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other programmable general purpose or special purpose microprocessor, digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices.

In one embodiment, memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access the memory unit according to the sequence of instructions.

FIG. 2 is a schematic block diagram of a memory controller according to an example embodiment of the invention. Referring to fig. 2, the memory controller 123 includes a memory control circuit 1233, a host interface 1231, and a memory interface 1232.

The memory control circuit 1233 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 1233 has a plurality of control commands, and these control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 12 is operating. The operation of the memory control circuit 1233 is explained as follows, which is equivalent to the operation of the memory controller 123.

In the present exemplary embodiment, the control instructions of the memory control circuit 1233 are operated in firmware. For example, the memory control circuit 1233 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 12 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory control circuit 1233 may also be stored in program code form in a specific area of the memory module 122 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory control circuit 1233 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has boot code (boot code) that is executed by the microprocessor unit to load control instructions stored in the memory module 122 into the RAM of the memory control circuit 1233 when the memory controller 123 is enabled. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory control circuit 1233 may also be operated in a hardware type. For example, the memory control circuit 1233 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the memory module 122. The memory write circuit is used for issuing a write instruction sequence to the memory module 122 to write data into the memory module 122. The memory read circuit is used to issue a sequence of read instructions to the memory module 122 to read data from the memory module 122. The memory erase circuit is used to issue a sequence of erase instructions to the memory module 122 to erase data from the memory module 122. The data processing circuit is used for processing data to be written into the memory module 122 and data read from the memory module 122. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the memory module 122 to perform corresponding write, read, erase, and other operations. In an example embodiment, memory control circuit 1233 may also issue other types of sequences of instructions to memory module 122 to direct the execution of corresponding operations.

The host interface 1231 is electrically connected to the memory control circuit 1233 and is used for receiving and recognizing the commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 1233 through the host interface 1231. In the present exemplary embodiment, host interface 1231 is compliant with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 1231 may also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transfer standard.

The memory interface 1232 is electrically connected to the memory control circuit 1233 and is used to access the memory module 122. That is, the data to be written into the memory module 122 is converted into a format acceptable to the memory module 122 through the memory interface 1232. Specifically, if the memory control circuit 1233 is to access the memory module 122, the memory interface 1232 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory control circuit 1233 and transferred to memory module 122 through memory interface 1232. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In the present exemplary embodiment, the memory controller 123 may perform single-frame (single-frame) encoding for data stored in the same physical programming unit, or may perform multi-frame (multi-frame) encoding for data stored in a plurality of physical programming units. Depending on the encoding algorithm employed, the memory controller 123 may encode the data to be protected to generate a corresponding error correction code and/or error checking code.

In an example embodiment, memory controller 123 further includes a buffer memory 1235, error checking and correction circuitry 1234 and power management circuitry 1236. The buffer memory 1235 is electrically connected to the memory control circuit 1233 and is used for temporarily storing data and instructions from the host system 11 or data from the memory module 122. The power management circuit 1236 is electrically connected to the memory control circuit 1233 and is used for controlling the power of the memory storage device 12. The error checking and correcting circuit 1234 is electrically connected to the memory control circuit 1233 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory control circuit 1233 receives a write command from the host system 11, the error checking and correcting circuit 1234 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory control circuit 1233 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the memory module 122. Then, when the memory control circuit 1233 reads data from the memory module 122, it reads the error correction code and/or the error check code corresponding to the data at the same time, and the error check and correction circuit 1234 performs the error check and correction operation on the read data according to the error correction code and/or the error check code.

FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 to 4, the memory module 122 includes a plurality of physical units 301 (1) to 301 (a). Each physical unit includes a plurality of memory cells and is used for non-volatile storage of data. For example, a physical unit may include one or more physical blocks. Each physical block may include a plurality of physical programming units. A physical programming unit may include one or more physical pages. Multiple memory cells in a physical programming unit may be programmed simultaneously to store data. In addition, all memory cells in a physical block can be erased simultaneously.

In one embodiment, the physical units 301 (1) -301 (A) in the memory module 122 are divided into the data areas 31. The entity units 301 (0) to 301 (a) in the data area 31 store data from the host system 11.

In one embodiment, memory control circuit 1233 may configure a plurality of logic units 302 (0) -302 (B) to map physical units in data region 31. For example, a logical unit may be composed of one or more logical addresses. The mapping relationship between the logical unit and the physical unit may be recorded in the logical-to-physical mapping table. When an access command is received from the host system 11, the memory control circuit 1233 can access data to the physical units in the data area 31 according to the corresponding logical-to-physical mapping table. Specifically, this mapping manner is block mapping.

In one embodiment, the memory control circuit 1233 can configure the plurality of logical physical Programming units 42 (0) -42 (E) to map the physical Programming units 41 (0) -41 (D) in the physical units 301 in the data area 31. For example, a logical entity programming unit may be comprised of one or more logical entity programming addresses. The mapping relationship between the logical entity programming unit and the physical entity programming unit may be recorded in a logical-to-physical mapping table of the logical entity programming unit and the physical entity programming unit. When receiving an access command from the host system 11, the memory control circuit 1233 can access data to the physical units in the data area 31 according to the corresponding logical-to-physical mapping tables of the logical-to-physical programming units and the physical programming units. Specifically, this mapping manner is page mapping.

Fig. 4 is a schematic diagram of managing physical units in a memory module according to an embodiment of the present invention, which is a schematic diagram of mapping logical physical programming units in the physical units 301 (1) to logical-to-physical mapping of physical programming units. Wherein D is the total number of physical programmed units of the physical unit 301 (1), and includes the value of the valid physical programmed units and the value of the invalid physical programmed units of the physical unit 301 (1); the numerical value of the effective entity programming unit is less than or equal to D; which is a positive integer. E is a positive integer which is less than or equal to D; the value of E represents the value of the active physical programming unit in the physical unit 301 (1).

In one embodiment, the present application provides a data access method for a memory storage device 12, wherein the memory storage device 12 includes a memory module 122, the memory module 122 includes at least one physical unit 301 (E) (E is an address value of the physical unit), the physical unit includes a plurality of physical program units 41 (0) to 41 (C), and in particular, the plurality of physical program units includes a physical program unit 41 (F) with invalid status (F is an address value of the physical program unit), as shown in fig. 5, the data access method includes:

step S501, performing erasing, data writing and reading test operations on the entity units, and establishing a state bitmap of the entity units, wherein the state bitmap is used for storing management information of the entity units, and the management information comprises the total number of entity programming units of the entity units, the number of the entity programming units with valid states and address values of the valid entity programming units in the entity units;

s502, dividing a plurality of entity windows in the entity unit according to a mapping interval value and the state bitmap, and constructing an entity window table of the entity windows;

S503, establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value;

s504, accessing data from the host system to the memory storage device according to the logic-to-entity mapping table.

Specifically, for step S501, in one embodiment, a method for constructing a status bitmap is provided, specifically, by performing erasing, data writing, and data writing/reading test operations on the entity units 301 (1) -301 (a), to construct a status bitmap of the entity units 301 (1) -301 (a), where the status bitmap is used to store management information of the entity units, where the management information includes a total number of entity programming units in the entity units, number of entity programming units with invalid status, number of entity programming units with valid status, and address values of the valid entity programming units in the entity units. For example, taking one of the physical units including 32 physical program units as an example, after performing the erase, data write, and data write/read test operations, a status bitmap diagram as shown in fig. 6 is obtained.

In one embodiment, the physical programmer with invalid status is denoted by "1" and the physical programmer with valid status is denoted by "0", as shown in FIG. 6.

As shown in fig. 6, the entity units include 18 valid entity programming units and 14 invalid entity programming units; the addresses of the 18 effective entity programming units are respectively: p0, P2, P3, P4, P6, P11, P12, P14, P18, P19, P20, P21, P22, P23, P25, P26, P27, P31; the addresses of the 14 invalid entity programming units are respectively: p1, P5, P7, P8, P9, P10, P13, P15, P16, P17, P24, P28, P29, P30.

In an embodiment, the present application further provides a method for constructing a logical-to-physical mapping interval value calculation model, as shown in fig. 7, which includes:

in step S702, according to the total number of entity programming units in the status bitmap of the entity units, the number of entity programming units with valid status, and the address value of the valid entity programming units in the entity units, the sum of the mapping traversal times of each logic entity programming unit in the entity units and the corresponding entity programming units is calculated; each logical physical programming unit can only perform mapping management with a physical programming unit with a valid state (also called a valid physical programming unit).

Specifically, the specific operation method of step S702 is shown in fig. 8, and includes:

Sub-step S7021: determining the address value of each logic entity programming unit according to the number of the effective entity programming units in the state bitmap of the entity unit;

sub-step S7022: determining that the corresponding state of each logic entity programming unit is an effective entity programming unit address when mapping address values are carried out according to the state of each entity programming unit in the state bitmap of the entity unit;

sub-step S7023: the address of the entity programming unit corresponding to each logic entity programming unit is differenced from the address of the logic entity programming unit, so that the traversal times required by mapping management between each logic entity programming unit and the entity programming unit are obtained;

sub-step S7024: and accumulating the traversal times corresponding to all the logic entity programming units to obtain a mapping traversal times sum.

For example, for the calculation of the number of traversals, it can be expressed by the following expression:

s is the number of traversals required for mapping management between all logical entity programming units and entity programming units in the memory module 122; nvp the number of logical physical programming units, which is also the number of active physical programming units; a represents the address of a logical entity programming unit; f (a) represents that the logical physical programming unit is mapped to the physical programming unit.

As shown in fig. 6, the entity units include 18 valid entity programming units and 14 invalid entity programming units; the address values of the 18 effective entity programming units are respectively as follows: p0, P2, P3, P4, P6, P11, P12, P14, P18, P19, P20, P21, P22, P23, P25, P26, P27, P31; the address values of the 14 invalid entity programming units are respectively as follows: p1, P5, P7, P8, P9, P10, P13, P15, P16, P17, P24, P28, P29, P30.

Thus, for the number of traversals S required for the physical unit, since the physical unit has 18 valid physical programming units, 18 mapping management is required, i.e. the address of the logical physical programming unit takes a value of 0 to 17.

For logical entity Programming Unit 0, there is S ₀ =f (0) -0=1, wherein the S ₀ =f (0) -0=1 means that the logical physical programming unit with address 0 requires 1 traversal of the physical programming unit with address 0 to establish the mapping management.

For a logical entity programming unit with address 1, there is S ₁ Because the status of the physical programming unit with address 2 is invalid, =f (1) -1=3-1=2, mapping to the valid physical programming unit, i.e. the physical programming unit with address 3, is required to implement mapping management. For the following mapping traversal times, the same is calculated, and then:

S ₂ ＝4-2＝2；S ₃ ＝5-3＝2；S ₄ ＝7-4＝3；S ₅ ＝12-5＝7；

S ₆ ＝12-6＝6；S ₇ ＝14-7＝7；S ₈ ＝18-8＝10；S ₉ ＝19-9＝10；

S ₁₀ ＝20-10＝10；S ₁₁ ＝21-11＝10；S ₁₂ ＝22-12＝10；S ₁₃ ＝23-13＝10；

S ₁₄ ＝25-14＝11；S ₁₅ ＝26-15＝11；S ₁₆ ＝27-16＝11；S ₁₇ ＝31-17＝14；

Then, the sum of these 18 passes of f (0) -f (17), S, equals 133.

Further, as shown in fig. 7, after step S702 is performed, step S704 is performed.

Step S704, multiplying the sum of the mapping traversal times by 2, and performing a ratio operation on the total number of the physical program units to obtain a ratio result, and performing a square root operation on the ratio result to obtain a square root result. Further, after the square root result is processed correspondingly, a preferred mapping interval value for mapping the logic physical programming unit and the physical programming unit in the memory block can be calculated.

For example, for the logical entity programming unit and entity programming unit mapping interval value model constructed as described above, the following is expressed:

where S represents the sum of the number of traversals required by each logical physical programming unit in the calculated memory module 122 to establish mapping management with the corresponding physical programming unit, nvp represents the number of valid physical programming units stored in the state bitmap, and X represents the square root result to be solved.

Further, after the square root result is calculated, step S706 may be further included:

s706, rounding up or rounding down the square root result to obtain an integer, and taking the integer as the mapping interval value between the logic entity programming unit and the entity programming unit.

By way of example only, and in an illustrative,the logical physical programming unit and the physical programming unit mapping interval value model are utilized, namelyApproximately equal to 3.8, the mapping interval value x=3 (or alternatively, may be rounded up to 4) is obtained by rounding down. It will be appreciated that the required mapping interval value may be calculated by the logical physical programming unit and physical programming unit mapping interval value model described above.

The application provides a logic-to-entity mapping interval value calculation model construction method, which calculates the mapping interval value from a logic entity programming unit to an entity programming unit of an entity unit according to the actual conditions of the entity unit, such as the total number of the entity programming units, the number of the entity programming units with effective states and the address value of the effective entity programming units in the entity unit; the method can establish state bitmaps of different entity units according to the different entity units, calculate different interval values of the entity units and calculate mapping interval values of the entity units; constructing a logical-to-physical mapping table of the memory module 122 based on the interval value, and accessing data from the host system 11 to the memory storage device 12 based on the constructed logical-to-physical mapping table; has the effect of increasing the speed at which data is accessed from host system 11 to memory storage device 12.

Specifically, for the above step S502, a plurality of entity windows are divided among the entity units according to a mapping interval value and the status bitmap, and an entity window table of the plurality of entity windows is constructed, where in an embodiment, the entity window includes a plurality of entity programming units, and the plurality of entity programming units include valid entity programming units and/or invalid entity programming units.

And establishing an entity window table for managing the entity windows, wherein the entity window table is used for storing the distribution situation of each entity window, the number of effective entity programming units in each entity window and the number of effective entity programming units from the initial entity window to the current entity window.

As shown in fig. 9, fig. 9 is a table of entity windows including 11 entity windows, which is established according to a mapping interval value of 3. The entity window table includes the following information: distribution of individual entity windows: the system comprises 11 entity windows, wherein the A0-A9 entity window comprises 3 entity programming units, the A10 entity window comprises 2 entity programming units, and two entity programming units in the A10 entity window are used for storing the state bitmap and entity window table (specific entity programming unit address values stored in the state bitmap and entity window table are omitted in the following description); the number of active physical programming units in the physical windows A0-A10 (i.e., the number of "0" s, hereinafter abbreviated) are: a0 =2, a1=2, a2=1, a3=1, a4=2, a5=0, a6=3, a7=3, a8=2, a9=1, a10=1; the number of "0" s from the start entity window to the A0-a10 entity window is: 0. 4, 5, 6, 8, 11, 14, 16, 17, 18.

In one embodiment, each physical window may include a different number of physical programming units. For example, as shown in FIG. 9, 3 physical Programming units are included in the A0-A9 physical window, and 2 physical Programming units are included in the A10 physical window.

In an embodiment, each physical programming unit state included in the physical window may be different. Specifically, all the physical programming unit states in the physical window are valid, such as the A6 and A7 physical windows in fig. 9; all of the physical programmer's unit states in the physical window are invalid, such as the A5 physical window in FIG. 9; the entity window includes an active entity programming unit and an inactive entity programming unit, such as the entity windows A0, A1, A2, A3, A4, A8, A9, and a10 in fig. 9.

Specifically, for step S503 described above, a logical-to-physical mapping table is established based on the physical window table and the mapping interval values, and in one embodiment, the specific operation for step S503 is to establish a logical-to-physical mapping table based on the distribution of the individual physical windows and the number of valid physical programming units from the starting physical window to the current physical window.

The logic-to-entity mapping table is established according to the distribution condition of each entity window and the number of the effective entity programming units from the initial entity window to the current entity window; further operations thereof are shown in fig. 10, including substep S5031 and substep S5032.

In step S5031, the address value of the target logical entity programming unit is compared with the number of the valid entity programming units from the initial entity window to the current entity window, and the minimum value of the number is taken out from all the numbers greater than or equal to the number so as to determine the target entity window to which the entity programming unit corresponding to the target logical entity programming unit belongs.

For example, taking the above-mentioned entity unit including 32 entity programming units as an example, it is necessary to establish the mapping table of the entity programming unit P20, and the results of L10-P20 shown in fig. 11 are implemented on the premise that 10 invalid entity programming units P20 are preceded by P1, P5, P7, P8, P9, P10, P13, P15, P16, and P17. It specifically operates to find entity windows with a number of "0" s of > 11 (because Logical10 is actually the 11 th valid entity programming unit) in the entity windows according to the entity window table shown in fig. 9, and as shown in fig. 9, the number of "0" s in the 5 entity windows with A6, A7, A8, A9, a10 is greater than 11, 14, 16, 17, 18 respectively; the entity window A6 with the number of the smallest value, namely "0", of all the values equal to 11 is taken to determine the target entity window to which the Logica10 belongs.

For example, to implement L8- - -P18 as shown in FIG. 11, find entity windows with number of "0" being greater than or equal to 9 in entity windows (Logical 8 is actually the 9 th valid entity programming unit), as shown in FIG. 9, the number of "0" in 5 entity windows, A6, A7, A8, A9, A10, is greater than 9, 11, 14, 16, 17, 18 respectively; the entity window A6 with the minimum value of all the values, namely, the number of 0's being equal to 11 is taken to determine the target entity window to which the Logical8 belongs.

For example, to implement L9-P19 as shown in fig. 11, the number of "0" in the lookup entity window is equal to or greater than 10 (Logical 9 is actually the 10 th valid entity programming unit), as shown in fig. 9, the number of "0" in the 5 entity windows of A6, A7, A8, A9, a10 is greater than 10, 11, 14, 16, 17, 18; the entity window A6 with the minimum value of all the values, namely, the number of 0's, equal to 11 is taken to determine the target entity window to which the Logical9 belongs.

For example, to implement L4-P6 as shown in fig. 11, the number of "0" in the lookup entity window is greater than or equal to 5 (Logical 4 is actually the 5 th valid entity programming unit), as shown in fig. 9, the number of "0" in the 5 entity windows in the 3 entity windows of A0, A1, A2 is greater than 5, and is 2, 4, 5 respectively; namely, the entity window A2 with the minimum value of all the values, namely, the number of 0's, equal to 5 is taken to determine the target entity window to which the Logical4 belongs.

For example, to implement L14- - -P25 as shown in FIG. 11, the number of "0" in the entity windows is greater than or equal to 15 (Logical 4 is actually the 15 th effective entity programming unit), as shown in FIG. 9, the number of "0" in the 5 entity windows of A8, A9 and A10 is greater than 9, and is 16, 17 and 18 respectively; i.e. taking the entity window A8 with the number of the smallest value, i.e. "0", of all the values equal to 16, to determine the target entity window to which the Logical14 belongs.

Sub-step S5032, calculating the address value of the initial entity programming unit in the target entity window according to the sequence number of the entity window and the mapping interval value, determining the address of the entity programming unit corresponding to the target logic entity programming unit, establishing the mapping relation of mapping the target logic entity programming unit to the corresponding entity programming unit, and establishing a logic-to-entity mapping table of mapping the logic entity programming unit in the entity unit to the entity programming unit according to the mapping relation.

Exemplary, as described above, entity window A6 has a sequence number of 6 and a mapping interval value of 3;6*3 =18, where 18 is the initial physical program unit address value 18 in the physical window A6, i.e. the physical program unit address in the physical window A6 is P18; further, since the mapping interval value is 3, it means that there are three physical programming units P18, P19, P20 in the physical window A6, and their address values are 18, 19, 20, respectively. Still further, according to the number of "0" s in the entity window A6 in fig. 9 being 3, it indicates that all of the 3 entity programming units P18, P19, P20 in the entity window A6 are valid entity programming units, and to implement L10-P20, the mapping query starts from P18, and after 3 traversals, L10-P20 can be established when traversing to P20, and the mapping relationship is loaded into the logical-to-entity mapping table, so that when the subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logical-to-entity mapping table.

Exemplary, as described above, entity window A6 has a sequence number of 6 and a mapping interval value of 3;6*3 =18, where 18 is the initial physical program unit address value 18 in the physical window A6, i.e. the physical program unit address in the physical window A6 is P18; further, since the mapping interval value is 3, it means that there are three physical programming units P18, P19, P20 in the physical window A6, and their address values are 18, 19, 20, respectively. Still further, according to the number of "0" s in the entity window A6 in fig. 9 being 3, it indicates that all of the 3 entity programming units P18, P19, P20 in the entity window A6 are valid entity programming units, and to implement L8-P18, the mapping query starts from P18, and after 1 traversal, L8-P18 is established, and the mapping relationship is loaded into the logical-to-entity mapping table, so that when the subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logical-to-entity mapping table.

Exemplary, as described above, entity window A6 has a sequence number of 6 and a mapping interval value of 3;6*3 =18, where 18 is the initial physical program unit address value 18 in the physical window A6, i.e. the physical program unit address in the physical window A6 is P18; further, since the mapping interval value is 3, it means that there are three physical programming units P18, P19, P20 in the physical window A6, and their address values are 18, 19, 20, respectively. Still further, according to the number of "0" s in the entity window A6 in fig. 9 being 3, it indicates that all of the 3 entity programming units P18, P19, P20 in the entity window A6 are valid entity programming units, and to implement L9-P19, the mapping query starts from P18, and after 2 passes, when traversing to P19, L9-P19 can be established, and the mapping relationship is loaded into the logical-to-entity mapping table, so that when the subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logical-to-entity mapping table.

Illustratively, as described above, entity window A2 has a sequence number of 2 and a mapping interval value of 3;2*3 =6, where 6 is the initial physical programming unit address value 6 in the physical window A2, i.e. the physical programming unit address in the physical window A2 is P6; further, since the mapping interval value is 3, it means that there are three physical programming units P6, P7, and P8 in the physical window A2, and their address values are 6, 7, and 8, respectively. Still further, according to the number of "0" s in the entity window A2 in fig. 9 being 1, it means that only 1 valid entity programming units are 3 entity programming units P6, P7, P8 in the entity window A2, to implement L4-P6, the mapping query starts from P6, and after 1 traversal, when traversing to P6, L4-P6 can be established, and the mapping relationship is loaded into the logical-to-entity mapping table, so that when the subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logical-to-entity mapping table.

Exemplary, as described above, entity window A8 has a sequence number of 8 and a mapping interval value of 3;8*3 =24, where 24 is the initial physical programming unit address value 24 in the physical window A8, i.e. the physical programming unit address in the physical window A6 is P24; further, since the mapping interval value is 3, it means that there are three physical programming units P24, P25, and P26 in the physical window A8, and their address values are 24, 25, and 26, respectively. Still further, according to the number of "0" s in the entity window A8 in fig. 9 being 2, it means that there are 2 valid entity programming units P24, P25, P26 in the entity window A8, and to implement L14-P25, the mapping query starts from P24, and traverses 2 times, when traversing to P25, L14-P25 can be established, and the mapping relationship is loaded into the logical-to-entity mapping table, so that when the subsequent data is accessed from the host system to the memory module, the data can be accessed from the host system to the memory module through the logical-to-entity mapping table.

In one embodiment, in the logical-to-physical mapping table, the address value of the physical programming unit is 1 bit.

For example, in the data reading and writing process, the prior art solution is to store the physical address value of each physical programming unit into the buffer memory 1235 to realize reading and writing of data. The physical address value of the physical programming unit comprises a physical unit address where the physical programming unit is located and a physical programming unit address, and the physical address value of each physical programming unit is 5 bytes (40 bits); illustratively, to implement L10-P20 in the prior art, the size required to be stored in the buffer memory 1235 is 5 bytes by 32=160 bytes; to implement the data read/write operation in this page mapping mode, the space occupied by the buffer memory 1235 is 160 bytes.

In one embodiment, if the buffer Memory 1235 is an SRAM (Static Random-Access Memory), the size of the SRAM is typically 4K-8K bytes, and the number of physical programming units required for the data reading and writing process of the Memory module 122 is much larger than 32, so the data reading and writing speed of the Memory module 122 in the page mapping management mode is very slow.

As shown in fig. 6 and 9, in the status bitmap and the entity window table of the entity unit, the entity programming unit whose status is invalid is denoted by "1", and the entity programming unit whose status is valid is denoted by "0". Further, in the mapping management method of mapping the logical entity programming unit to the entity programming unit in the logical-to-entity mapping table, the physical address of the entity programming unit corresponding to the logical entity programming unit is determined by calculating the number of '0's and searching the address value corresponding to the '0'; and "0" has a size of 1 bit in the mapping table, so that the address value of the physical programming unit in the logical-to-physical mapping table has a size of 1 bit; this reduces the size of the logical-to-physical mapping table.

In an embodiment, the method for determining the address of the physical programming unit corresponding to the target logical physical programming unit further includes calculating an address value of the initial physical programming unit in the target physical window according to the sequence number of the physical window and the mapping interval value:

after determining the target entity window to which the entity programming unit corresponding to the target logic entity programming unit belongs, determining the address of the entity programming unit corresponding to the target logic entity programming unit through the traversal times smaller than or equal to the mapping interval value.

Illustratively, the number of times of traversing or querying the corresponding physical program units of the L10- - -P20, L8- - -P18, L9- - -P19, L4- - -P6, L14- - -P25 is 3 times, 1 time, 2 times, respectively; are 3 or less (mapping interval value).

Specifically, for the step S504, the data is accessed from the host system to the memory storage device according to the logical-to-entity mapping table, and in one embodiment, the data is accessed from the host system to the memory storage device according to the logical-to-entity mapping table according to the present application.

In the data reading and writing process, the state bitmap and the mapping interval value are stored in the buffer memory 1235, and in the embodiment of the application, the size stored in the buffer memory 1235 is the number of 0, and the size of the occupied capacity required by one 0 storage is 1 bit; in one embodiment, the buffer Memory 1235 is an SRAM (Static Random-Access Memory) with a size of about 4K-8K bytes, which can store 32-64K "0" s at a time; i.e., 32-64K active physical programming units. When the physical addresses of the physical programming units are calculated by using the size of 1 physical programming unit being 16KB, if 500MB data (16 KB is 32K) is stored in the memory storage device 12 from the host system 11, even if the size of the SRAM is 4K bytes, the physical addresses of the physical programming units can be loaded into the SRAM at one time, and the 500MB data can be quickly stored in the memory storage device 12 from the host system 11; similarly, the reading of data from the memory storage device 12 into the host system 11 may also be accomplished at once. Thus, applying the logical-to-entity mapping table constructed by the above method to the memory storage device 12 and the memory module 122 can significantly increase the speed of accessing large files and large data from the host system to the memory storage device 12 and the memory module 122.

The logic-to-entity mapping management method enables the mapping management speed from the logic programming unit to the entity programming unit to be very high, and when the mapping management from the target logic to the entity programming unit is carried out, the address of the entity programming unit corresponding to the target logic entity programming unit can be determined only through traversing for a limited number of times through the target entity window which the entity programming unit corresponding to the target logic entity programming unit belongs to; the entity programming unit corresponding to the logic entity programming unit can be quickly determined, and a logical-to-entity mapping table is not required to be established by adopting a page-type traversal page mapping method.

FIG. 12 is a schematic diagram of a page-wise traversal page mapping method, as shown in FIG. 12, in the mapping management process, when the physical programming units 0-3 are all valid physical programming units, the mapping between the logical physical programming units 0-3 and the physical programming units 0-3 can be very fast, but when the physical programming units 4 are invalid physical programming units, the logical physical programming units 4 need to skip the invalid physical programming units 4 and the next valid physical programming units, i.e. the physical programming units 5, if the physical programming units 5 are also invalid physical programming units, the next valid physical programming units continue to be skipped until the state is skipped to the valid physical programming units, if the total number proportion of the invalid physical programming units in the physical units is not large, the data read-write speed of the memory storage device 12 containing the physical units is not greatly influenced; however, if the memory storage device 12 includes a relatively large number of such physical units, the data read/write speed of the memory storage device 12 is greatly affected.

Further, according to the logic-to-entity mapping interval value calculating method provided by the application, the mapping interval value of the entity units is calculated according to the actual situation of the entity units, such as the total number of entity programming units; it will be appreciated that the total number of entity units is different, and that the mapping interval values of the entity units are different. Based on the mapping interval value, a logical-to-physical mapping table of the memory module 122 is constructed, thereby increasing the speed at which data is accessed from the host system 11 to the memory storage device 12.

In one embodiment, the present application also proposes a memory storage device 12, said memory storage device 12 comprising: a connection interface 121 for connection to the host system 11; a memory module 122 comprising at least one physical unit; and a memory controller 123 connected to the connection interface 121 and the memory module 122; wherein the data access method of fig. 5, 7, 8 and 10 can be applied on the memory controller 123. The steps in fig. 5, 7, 8 and 10 are described in detail above, and will not be repeated here. It should be noted that each step in fig. 5, fig. 7, fig. 8, and fig. 10 may be implemented as a plurality of program codes or circuits, which is not limited by the present application. In addition, the methods of fig. 5, 7, 8 and 10 may be used with the above exemplary embodiments, or may be used alone, and the present application is not limited thereto.

In an embodiment, the present application also proposes a memory controller 123 for controlling a memory module 122, wherein the memory module 122 comprises at least one physical unit, and the memory controller 123 comprises: a host interface 1231 for connecting to the host system 11; a memory interface 1232 for connecting to the memory module 122; and memory control circuitry 1233 connected to said host interface 1231 and said memory interface 1232; wherein the data access method of fig. 5, 7, 8 and 10 may be applied on the memory control circuit 1233. The steps in fig. 5, 7, 8 and 10 are described in detail above, and will not be repeated here. It should be noted that each step in fig. 5, fig. 7, fig. 8, and fig. 10 may be implemented as a plurality of program codes or circuits, which is not limited by the present application. In addition, the methods of fig. 5 and 8 may be used with the above exemplary embodiments, or may be used alone, and the present application is not limited thereto.

In summary, the present application provides a data access method and a method for constructing a logical-to-physical mapping table; applying the above-described method to memory storage device 12 and memory module 122 may significantly increase the speed at which large files and large data are accessed from the host system to memory storage device 12 and memory module 122.

Further, the application also provides a logic-to-entity mapping interval value calculation model construction method, which calculates the logic entity programming unit-to-entity programming unit mapping interval value of the entity unit according to the actual conditions of the entity unit, such as the total number of entity programming units, the number of entity programming units with valid states and the address value of the valid entity programming units in the entity unit; the method can establish state bitmaps of different entity units according to the different entity units, calculate different interval values of the entity units and calculate mapping interval values of the entity units; constructing a logical-to-physical mapping table of the memory module 122 based on the interval value, thereby increasing the speed of data access from the host system 11 to the memory storage device 12; the memory storage device 12 and the memory module 122 which are applied to the data access method, the logic-to-entity mapping table construction method and the logic-to-entity mapping interval value calculation model construction method are realized, so that the speed of accessing large files and large data from a host system to the memory storage device 12 and the memory module 122 can be remarkably improved; even though the SRAM capacity in the memory storage 12 and memory module 122 is small, large file embodiments of the present application may be implemented to increase the speed at which data is accessed from the host system to the memory module.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A data access method for a memory storage device, wherein the memory storage device comprises a memory module, the memory module comprising at least one physical unit, the physical unit comprising a plurality of physical programming units, and the data access method comprising:

establishing a state bitmap of the entity units, wherein the state bitmap is used for storing management information of the entity units, and the management information comprises the total number of entity programming units of the entity units, the number of entity programming units with valid states and address values of the valid entity programming units in the entity units;

Dividing a plurality of entity windows in the entity units according to a mapping interval value and the state bitmap, and constructing an entity window table of the entity windows, wherein the entity windows comprise a plurality of entity programming units, the entity programming units comprise valid entity programming units and/or invalid entity programming units, and the entity window table stores the distribution condition of each entity window and the number of valid entity programming units from a starting entity window to a current entity window;

establishing a logic-to-entity mapping table according to the entity window table and the mapping interval value, wherein the method for establishing the logic-to-entity mapping table according to the entity window table and the mapping interval value comprises the following steps:

comparing the address value of the target logic entity programming unit with the number of the effective entity programming units from the initial entity window to the current entity window, and taking the minimum value of the number from all the number more than or equal to the number to determine the target entity window to which the entity programming unit corresponding to the target logic entity programming unit belongs;

calculating an address value of an initial entity programming unit in the target entity window according to the sequence number of the entity window and the mapping interval value, determining an address of an entity programming unit corresponding to the target logic entity programming unit, establishing a mapping relation of mapping the target logic entity programming unit to the corresponding entity programming unit, and establishing a logic-to-entity mapping table of mapping the logic entity programming unit in the entity unit to the entity programming unit according to the mapping relation;

Access of data from the host system to the memory storage device is effected according to the logical-to-entity mapping table.

2. The method of claim 1, wherein the method of dividing a plurality of entity windows in the entity unit according to a mapping interval value and the status bitmap comprises: dividing the entity unit into a plurality of areas according to the mapping interval value of mapping the logic entity programming unit to the entity programming unit in the entity unit, wherein each area comprises a plurality of entity programming units, and the areas are the entity windows.

3. The data access method of claim 1, wherein the mapping interval value is calculated by a logical-to-physical mapping interval value calculation model.

4. The data access method according to claim 3, wherein the method for constructing the logical-to-physical mapping interval value calculation model includes:

calculating the sum of mapping traversal times of each logic entity programming unit and corresponding entity programming units in the entity units according to the total number of entity programming units in the state bitmap of the entity units, the number of entity programming units with valid states and the address value of the valid entity programming units in the entity units;

And multiplying the sum of the mapping traversal times by 2, then carrying out ratio operation on the total number of the effective physical programming units to obtain a ratio result, and carrying out square root processing on the ratio result to obtain a square root result, wherein the square root result is used as a mapping interval value between the logic physical programming units and the physical programming units.

5. The method of claim 4, wherein the method of constructing the logical-to-physical mapping interval value calculation model further comprises:

and after the square root result is obtained, carrying out upward rounding or downward rounding on the square root result to obtain an integer, and taking the integer as a mapping interval value between the logic entity programming unit and the entity programming unit.

6. The method according to claim 4, wherein the sum of the mapping traversal times of each logical entity programming unit and the corresponding entity programming unit in the entity units is calculated according to the total number of entity programming units in the status bitmap of the entity units, the number of entity programming units whose status is valid, and the address value of the valid entity programming units in the entity units; comprising the following steps:

Determining the address value of each logic entity programming unit according to the number of the effective entity programming units in the state bitmap of the entity unit;

determining that the corresponding state of each logic entity programming unit is an effective entity programming unit address when mapping address values are carried out according to the state of each entity programming unit in the state bitmap of the entity unit;

the address of the entity programming unit corresponding to each logic entity programming unit is differenced from the address of the logic entity programming unit, so that the traversal times required by mapping management between each logic entity programming unit and the entity programming unit are obtained;

and accumulating the traversal times corresponding to all the logic entity programming units to obtain a mapping traversal times sum.

7. The method according to claim 1, wherein the operation method for calculating the address value of the initial physical programming unit in the target physical window according to the sequence number of the physical window and the mapping interval value, and determining the address of the physical programming unit corresponding to the target logical physical programming unit specifically further comprises:

8. The method of claim 1, wherein the address value of the physical programming unit in the logical-to-physical mapping table is 1 bit.

9. The method of claim 1, wherein the status bitmap of the physical unit indicates that the physical programming unit is invalid, and the status bitmap of the physical unit indicates that the physical programming unit is valid.

10. The method according to claim 1, wherein the physical window comprises a plurality of physical programming units including active physical programming units and/or inactive physical programming units.

11. The method for accessing data according to claim 1, wherein the constructing the status bitmap of the entity unit comprises:

and performing erasing, data writing and data reading test operations on the entity units to obtain a state bitmap of the entity units.

12. A memory storage device, comprising:

a connection interface for connecting to a host system;

a memory module comprising at least one physical unit;

and a memory controller connected to the connection interface and the memory module;

characterized in that the memory controller is adapted to perform the data access method of any of claims 1-11.

13. A memory controller for controlling a memory module, wherein the memory module comprises at least one physical unit, and the memory controller comprises:

a host interface for connecting to a host system;

a memory interface for connecting to the memory module; and

a memory control circuit connected to the host interface and the memory interface; the memory control circuit being adapted to perform the data access method of any of claims 1-11.