CN114038425A

CN114038425A - Pixel driving circuit, method and display panel

Info

Publication number: CN114038425A
Application number: CN202111441188.XA
Authority: CN
Inventors: 卢昭阳; 李荣荣
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-02-11

Abstract

The application discloses a pixel driving circuit, a pixel driving method and a display panel, and belongs to the technical field of display. The pixel driving circuit includes a first transistor, a driving transistor, a second transistor, and a third transistor. The second transistor is coupled between the second pole of the driving transistor and the first subpixel, and the third transistor is coupled between the second pole of the driving transistor and the second subpixel. The pixel driving circuit can drive two sub-pixels, and under the condition that the number of the pixel driving circuits on the display panel is the same, the pixel driving circuit can improve the number of the sub-pixels on the display panel, so that the resolution of the display panel is improved.

Description

Pixel driving circuit, method and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a pixel driving method, and a display panel.

Background

The OLED (Organic Light-Emitting Diode) display panel includes an AMOLED (Active-Matrix Organic Light-Emitting Diode) display panel and a PMOLED (Passive-Matrix Organic Light-Emitting Diode) display panel. The AMOLED display panel refers to that each sub-pixel in the display panel is connected with a pixel driving circuit. The pixel driving circuit is used for outputting driving signals to the sub-pixels so as to drive the sub-pixels to emit light.

In the related art, each pixel driving circuit generally includes a plurality of transistors, such as 7 or 8. Since the number of transistors included in the pixel driving circuit is large, the number of pixel driving circuits that can be formed on the display panel is small, and the number of sub-pixels on the display panel is small, which affects the improvement of the resolution of the display panel.

Disclosure of Invention

The application provides a pixel driving circuit, a pixel driving method and a display panel, which can solve the problem that the number of sub-pixels on the display panel is small due to the fact that the number of transistors included in the pixel driving circuit is large in the related art, and therefore the resolution of the display panel is improved. The technical scheme is as follows:

in a first aspect, a pixel driving circuit is provided, which includes: a first transistor, a driving transistor, a second transistor, and a third transistor;

a first pole of the first transistor is used for inputting a data voltage, and a second pole of the first transistor and the control pole of the driving transistor are connected to a first node;

a first pole of the driving transistor is used for inputting a first power supply voltage, and a second pole of the driving transistor, a first pole of the second transistor and a first pole of the third transistor are connected to a second node;

the second pole of the second transistor is used for being connected with the first sub-pixel so as to output a driving signal to the first sub-pixel when the second transistor is conducted; the second pole of the third transistor is used for being connected with a second sub-pixel except the first sub-pixel so as to output a driving signal to the second sub-pixel when the third transistor is turned on.

In the present application, the pixel driving circuit includes a first transistor, a driving transistor, a second transistor, and a third transistor. When the first transistor is turned on, a data voltage may be input to the gate of the driving transistor through the first transistor. The data voltage is used for controlling the conduction of the driving transistor and controlling the magnitude of the electric signal output by the driving transistor. The second transistor is connected between the second pole of the driving transistor and the first sub-pixel, and the third transistor is connected between the second pole of the driving transistor and the second sub-pixel, so that under the condition that the control pole of the driving transistor inputs data voltage, if the second transistor is conducted, the second transistor outputs a driving signal to the first sub-pixel; if the third transistor is turned on, the third transistor outputs a driving signal to the second subpixel. That is, the pixel driving circuit may drive two sub-pixels. In this case, under the condition that the number of the pixel driving circuits on the display panel is the same, the pixel driving circuit provided by the application can increase the number of the sub-pixels on the display panel, so that the resolution of the display panel is increased.

Optionally, the pixel driving circuit further includes: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor;

a first pole of the fourth transistor is used for inputting the first power supply voltage, a second pole of the fourth transistor and the first pole of the driving transistor are connected to a third node, so that when the fourth transistor is conducted, the first pole of the driving transistor inputs the first power supply voltage;

a first pole of the fifth transistor is connected to the first node, and a second pole of the fifth transistor is connected to the third node;

a first pole of the sixth transistor is connected to the first node, a second pole of the sixth transistor is connected to the first plate of the capacitor, and the second plate of the capacitor is connected to the second node;

the first pole of the seventh transistor is used for inputting a first voltage, and the second pole of the seventh transistor is connected with the first pole plate of the capacitor.

Optionally, the pixel driving circuit further includes: an eighth transistor;

a first pole of the eighth transistor is used for inputting a second voltage, and a second pole of the eighth transistor is connected to the second node.

Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the driving transistor are all amorphous silicon thin film transistors, low temperature polysilicon thin film transistors, indium gallium zinc oxide thin film transistors, or metal oxide semiconductor thin film transistors.

Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the driving transistor are all N-type thin film transistors.

In a second aspect, there is provided a pixel driving method applied to the pixel driving circuit according to any one of the first aspect, the pixel driving method comprising:

in a first time period, outputting a first scanning signal to a control electrode of the first transistor so as to control the first transistor to be switched on and then outputting the data voltage to the control electrode of the driving transistor;

in a second time period, outputting a first power supply voltage to the first electrode of the driving transistor to control the driving transistor to output an electric signal, and outputting a second scanning signal to the control electrode of the second transistor to control the second transistor to be turned on and then outputting a driving signal to the first sub-pixel;

and in a third time period, outputting a first power supply voltage to the first pole of the driving transistor to control the driving transistor to output an electric signal, and outputting a third scanning signal to the control pole of the third transistor to control the third transistor to be turned on and then outputting a driving signal to the second sub-pixel.

the pixel driving method further includes:

in the first time period, outputting a first scanning signal to a control electrode of the seventh transistor to control the seventh transistor to be turned on and then outputting the first voltage to a first plate of the capacitor, and outputting a fourth scanning signal to a control electrode of the fifth transistor to control the fifth transistor to be turned on and then outputting the data voltage to a first electrode of the driving transistor;

in the second time period and the third time period, stopping outputting the first scan signal to control the first transistor and the seventh transistor to be turned off, stopping outputting the fourth scan signal to control the fifth transistor to be turned off, and outputting a fifth scan signal to control the control electrodes of the fourth transistor and the sixth transistor to control the fourth transistor and then outputting the first power supply voltage to the first electrode of the driving transistor and to turn on the sixth transistor.

Optionally, the pixel driving circuit further includes: an eighth transistor;

the pixel driving method further includes:

in a reset time period, outputting a first scanning signal to control electrodes of the first transistor and the seventh transistor to control the first transistor to be turned on and then outputting the data voltage to a control electrode of the driving transistor, outputting the first voltage to a first plate of the capacitor after the seventh transistor is turned on, and outputting a sixth scanning signal to a control electrode of the eighth transistor to control the eighth transistor to be turned on and then outputting the second voltage to a second plate of the capacitor; the reset time period precedes the first time period.

In a third aspect, a display panel is provided, comprising a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of pixel driving circuits as described in any one of the first aspect;

first poles of the plurality of first sub-pixels are connected with second poles of second transistors in the plurality of pixel driving circuits one by one, and first poles of the plurality of second sub-pixels are connected with second poles of third transistors in the plurality of pixel driving circuits one by one;

the second poles of the first sub-pixels and the second poles of the second sub-pixels are used for inputting a second power voltage, and the second power voltage is smaller than the first power voltage.

Optionally, the first sub-pixel is a red sub-pixel, and the second sub-pixel is a green sub-pixel.

It is understood that, the beneficial effects of the second and third aspects may be referred to the relevant description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 2 is a timing diagram of a pixel driving method according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a pixel driving circuit according to a second embodiment of the present application;

fig. 4 is a timing diagram of a pixel driving method according to a second embodiment of the present application;

fig. 5 is a schematic structural diagram of a pixel driving circuit according to a third embodiment of the present application;

fig. 6 is a timing diagram of a pixel driving method according to a third embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that reference to "a plurality" in this application means two or more. In the description of the present application, "/" means "or" unless otherwise stated, for example, a/B may mean a or B; "and/or" herein is only an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, for the convenience of clearly describing the technical solutions of the present application, the terms "first", "second", and the like are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

The following explains the pixel driving circuit and the pixel driving method provided in the embodiments of the present application in detail from the first embodiment to the fourth embodiment.

The first embodiment is as follows:

fig. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 1, the pixel driving circuit includes a first transistor T1, a driving transistor T0, a second transistor T2, and a third transistor T3.

Specifically, the first transistor T1, the driving transistor T0, the second transistor T2, and the third transistor T3 are all amorphous silicon thin-film transistors (a-Si TFTs), low-temperature polysilicon thin-film transistors (p-Si TFTs), indium gallium zinc oxide thin-film transistors (IGZO TFTs), or metal oxide semiconductor thin-film transistors (MOS TFTs). In some specific embodiments, since the indium gallium zinc oxide thin film transistor has advantages of high precision, low power consumption, and the like, the first transistor T1, the driving transistor T0, the second transistor T2, and the third transistor T3 may be indium gallium zinc oxide thin film transistors.

The first transistor T1 has a first pole, a second pole, and a control pole. A first pole of the first transistor T1 is for inputting an electric signal, and a second pole of the first transistor T1 is for outputting an electric signal. The control electrode of the first transistor T1 is used to control the on and off between the first and second electrodes of the first transistor T1. When the first transistor T1 is turned on between the first and second poles, the first transistor T1 is said to be turned on; when the first transistor T1 is turned off between the first and second poles, the first transistor T1 is said to be turned off. A first pole of the first transistor T1 is used for inputting the DATA voltage DATA. The second pole of the first transistor T1 is connected to the first node a. A control electrode of the first transistor T1 is used to input the first SCAN signal SCAN 1. When the first SCAN signal SCAN1 is inputted to the gate of the first transistor T1, the first transistor T1 is turned on, and the first transistor T1 outputs the DATA voltage DATA to the first node a. When the first SCAN signal SCAN1 is not input to the gate of the first transistor T1, the first transistor T1 is turned off, and the first transistor T1 does not output the DATA voltage DATA to the first node a.

The driving transistor T0 has a first pole, a second pole and a control pole. The first pole of the driving transistor T0 is for inputting an electric signal, and the second pole of the driving transistor T0 is for outputting an electric signal. The control electrode of the driving transistor T0 is used to control the on and off between the first and second electrodes of the driving transistor T0. When the first pole and the second pole of the driving transistor T0 are conducted, the driving transistor T0 is called to be conducted; when the driving transistor T0 is turned off between the first and second poles, the driving transistor T0 is said to be turned off. A control electrode of the driving transistor T0 is connected to the first node a, a first electrode of the driving transistor T0 is used to input the first power voltage VDD, and a second electrode of the driving transistor T0 is connected to the second node b. Thus, when the DATA voltage DATA is inputted to the first node a, the driving transistor T0 is turned on, and outputs an electrical signal to the second node b under the action of the first power voltage VDD. When the DATA voltage DATA is not input to the first node a, the driving transistor T0 is turned off, and no electrical signal is output to the second node b. The magnitude of the electric signal output to the second node b by the driving transistor T0 depends on the magnitude of the DATA voltage DATA.

The second transistor T2 has a first pole, a second pole, and a control pole. A first pole of the second transistor T2 is used for inputting an electric signal, and a second pole of the second transistor T2 is used for outputting an electric signal. The control electrode of the second transistor T2 is used to control the on and off between the first and second electrodes of the second transistor T2. When the first pole and the second pole of the second transistor T2 are turned on, the second transistor T2 is said to be turned on; when the second transistor T2 is turned off between the first and second poles, the second transistor T2 is said to be turned off. A first pole of the second transistor T2 is connected to the second node b to input an electric signal of the second node b, and a second pole of the second transistor T2 is connected to the first sub-pixel OLED 1. The control electrode of the second transistor T2 is used for inputting the second SCAN signal SCAN2, when the control electrode of the second transistor T2 inputs the second SCAN signal SCAN2, the second transistor T2 is turned on, and at this time, the second transistor T2 outputs an electrical signal to the first sub-pixel OLED1 according to the electrical signal of the second node b, thereby driving the first sub-pixel OLED1 to emit light. When the second SCAN signal SCAN2 is not input to the control electrode of the second transistor T2, the second transistor T2 is turned off, and the second transistor T2 does not output an electrical signal to the first sub-pixel OLED 1. For convenience of description, an electric signal output from the second transistor T2 to the first sub-pixel OLED1 is referred to as a driving signal.

The third transistor T3 has a first pole, a second pole, and a control pole. A first pole of the third transistor T3 is for inputting an electric signal, and a second pole of the third transistor T3 is for outputting an electric signal. The control electrode of the third transistor T3 is used to control on and off between the first and second electrodes of the third transistor T3. When the first pole and the second pole of the third transistor T3 are turned on, the third transistor T3 is said to be turned on; when the third transistor T3 is turned off between the first and second poles, the third transistor T3 is said to be turned off. A first pole of the third transistor T3 is connected to the second node b to input an electric signal of the second node b, and a second pole of the third transistor T3 is connected to the second sub-pixel OLED 2. The control electrode of the third transistor T3 is used for inputting the third SCAN signal SCAN3, and when the control electrode of the third transistor T3 inputs the third SCAN signal SCAN3, the third transistor T3 is turned on, and at this time, the third transistor T3 outputs an electrical signal to the second sub-pixel OLED2 according to the electrical signal of the second node b, thereby driving the second sub-pixel OLED2 to emit light. When the third SCAN signal SCAN3 is not input to the control electrode of the third transistor T3, the third transistor T3 is turned off, and the third transistor T3 does not output an electrical signal to the second sub-pixel OLED 2. For convenience of description, the electric signal output from the third transistor T3 to the second sub-pixel OLED2 is also referred to as a driving signal.

In the embodiment of the present application, when the first transistor T1 is turned on, the DATA voltage DATA may be input to the gate of the driving transistor T0 through the first transistor T1. The DATA voltage DATA is used to control the driving transistor T0 to be turned on and to control the magnitude of the output electrical signal of the driving transistor T0. The second transistor T2 is connected between the second pole of the driving transistor T0 and the first sub-pixel OLED1, and the third transistor T3 is connected between the second pole of the driving transistor T0 and the second sub-pixel OLED2, so that, when the DATA voltage DATA is input to the control electrode of the driving transistor T0, if the second transistor T2 is turned on, the second transistor T2 outputs a driving signal to the first sub-pixel OLED 1; if the third transistor T3 is turned on, the third transistor T3 outputs a driving signal to the second sub-pixel OLED 2. That is, the pixel driving circuit may drive two sub-pixels, a first sub-pixel OLED1 and a second sub-pixel OLED 2. In this case, under the condition that the number of the pixel driving circuits on the display panel is the same, the pixel driving circuit provided by the application can increase the number of the sub-pixels on the display panel, so that the resolution of the display panel is increased.

In some embodiments, in the pixel driving circuit shown in fig. 1, the first transistor T1, the second transistor T2, the third transistor T3 and the driving transistor T0 are all N-type thin film transistors. The N-type thin film transistor is switched on at a high level and switched off at a low level. When the transistors (including the first transistor T1, the second transistor T2, the third transistor T3, and the driving transistor T0) are all N-type thin film transistors, the control electrodes of the transistors are the gates of the N-type thin film transistors, the first electrodes of the transistors are the drains of the N-type thin film transistors, and the second electrodes of the transistors are the sources of the N-type thin film transistors. In other embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the driving transistor T0 are all P-type thin film transistors. The P-type thin film transistor is turned off at a high level and turned on at a low level. When all the transistors are P-type thin film transistors, the control electrodes of all the transistors are the grid electrodes of the P-type thin film transistors, the first electrodes of all the transistors are the source electrodes of the P-type thin film transistors, and the second electrodes of all the transistors are the drain electrodes of the P-type thin film transistors.

The embodiment of the application also provides a pixel driving method which is applied to the pixel driving circuit of the embodiment of the application. Fig. 2 is a timing diagram of a pixel driving method according to an embodiment of the present application. The operation of the pixel driving circuit shown in fig. 1 will be described in detail with reference to fig. 2.

The timing chart shown in fig. 2 exemplifies that each transistor is an N-type thin film transistor. In the embodiment shown in fig. 2, each of the SCAN signals (including the first SCAN signal SCAN1, the second SCAN signal SCAN2, and the third SCAN signal SCAN3) indicates that the SCAN signal is output when it is high, and indicates that the SCAN signal is not output when it is low. As shown in fig. 2, the pixel driving method includes:

s110, during the first time period T1, the first SCAN signal SCAN1 is outputted to the gate of the first transistor T1 to control the first transistor T1 to turn on and then output the DATA voltage DATA to the gate of the driving transistor T0.

At the first period T1, the control electrode of the first transistor T1 inputs the first SCAN signal SCAN 1. That is, the first SCAN signal SCAN1 is at a high level during the first period t 1. At this time, the first transistor T1 is turned on, and the DATA voltage DATA is written into the first node a. When the DATA voltage DATA is inputted to the first node a, the driving transistor T0 is turned on.

S120, in the second period T2, the first power voltage VDD is output to the first pole of the driving transistor T0 to control the driving transistor T0 to output the electric signal, and the second SCAN signal SCAN2 is output to the control pole of the second transistor T2 to control the second transistor T2 to turn on to output the driving signal to the first sub-pixel OLED 1.

The second period t2 is a period located after the first period t1, and the second period t2 is contiguous with the first period t 1. In other words, the ending time of the first time period t1 is the starting time of the second time period t 2. In the second period T2, the first power voltage VDD is output to the first pole of the driving transistor T0, and in this case, the driving transistor T0 outputs an electric signal to the second node b by the first power voltage VDD. Meanwhile, in the second period T2, the control electrode of the second transistor T2 inputs the second SCAN signal SCAN 2. That is, the second SCAN signal SCAN2 is at a high level for the second period t 2. At this time, the second transistor T2 is turned on, and the second transistor T2 outputs a driving signal to the first sub-pixel OLED1 according to the electrical signal of the second node b, thereby driving the first sub-pixel OLED1 to emit light.

S130, in the third period T3, the first power voltage VDD is output to the first pole of the driving transistor T0 to control the driving transistor T0 to output the electric signal, and the third SCAN signal SCAN3 is output to the control pole of the third transistor T3 to control the third transistor T3 to be turned on to output the driving signal to the second sub-pixel OLED 2.

In the third period T3, the first power voltage VDD is output to the first pole of the driving transistor T0, and in this case, the driving transistor T0 outputs an electric signal to the second node b by the first power voltage VDD. Meanwhile, in the third period T3, the control electrode of the third transistor T3 inputs the third SCAN signal SCAN 3. That is, the third SCAN signal SCAN3 is at a high level for the third period t 3. At this time, the third transistor T3 is turned on, and the third transistor T3 outputs a driving signal to the second sub-pixel OLED2 according to the electrical signal of the second node b, thereby driving the second sub-pixel OLED2 to emit light.

In the embodiment shown in fig. 2, the third period t3 is a period located after the second period t2, and the third period t3 is contiguous with the second period t 2. In other words, the ending time of the second time period t2 is the starting time of the third time period t 3. In other embodiments, the third time period t3 may also start simultaneously with the second time period t2, in which case the third time period t3 and the second time period t2 are the same time period. Alternatively, the third time period t3 precedes the second time period t2 and the second time period t2 is contiguous with the third time period t 3. In the embodiment shown in fig. 2, the DATA voltages DATA corresponding to the first sub-pixel OLED1 and the second sub-pixel OLED2 are the same.

In other embodiments, the DATA voltages DATA of the first sub-pixel OLED1 and the second sub-pixel OLED2 are different, and in this case, the step S110 needs to be performed first, and then one of the steps S120 and S130 needs to be performed; thereafter, step S110 is re-executed, and the other of steps S120 and S130 is re-executed. For example, when the DATA voltage DATA corresponding to the first sub-pixel OLED1 is the first DATA voltage DATA1, and the DATA voltage DATA corresponding to the second sub-pixel OLED2 is the second DATA voltage DATA2, the pixel driving method may sequentially include the following steps: outputting a first SCAN signal SCAN1 to a control electrode of the first transistor T1 to control the first transistor T1 to turn on and then outputting a first DATA voltage DATA1 to a control electrode of the driving transistor T0; the first power voltage VDD is output to the first electrode of the driving transistor T0 to control the driving transistor T0 to output an electrical signal, and the second SCAN signal SCAN2 is output to the control electrode of the second transistor T2 to control the second transistor T2 to turn on and output a driving signal to the first sub-pixel OLED 1. Then, the first SCAN signal SCAN1 is outputted to the gate of the first transistor T1 again to control the first transistor T1 to turn on and then output the second DATA voltage DATA2 to the gate of the driving transistor T0; the first power voltage VDD is output to the first pole of the driving transistor T0 to control the driving transistor T0 to output an electrical signal, and the third SCAN signal SCAN3 is output to the control pole of the third transistor T3 to control the third transistor T3 to turn on and output a driving signal to the second sub-pixel OLED 2.

Example two:

fig. 3 is a schematic structural diagram of a pixel driving circuit according to a second embodiment of the present application. As shown in fig. 3, the pixel driving circuit includes a first transistor T1, a driving transistor T0, a second transistor T2, and a third transistor T3, and further includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.

Specifically, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all amorphous silicon thin film transistors, low temperature polysilicon thin film transistors, indium gallium zinc oxide thin film transistors, or metal oxide semiconductor thin film transistors. In some specific embodiments, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be indium gallium zinc oxide thin film transistors.

The fourth transistor T4 has a first pole, a second pole and a control pole. A first pole of the fourth transistor T4 is for inputting an electric signal, and a second pole of the fourth transistor T4 is for outputting an electric signal. The control electrode of the fourth transistor T4 is used to control the on and off between the first and second electrodes of the fourth transistor T4. When the first pole and the second pole of the fourth transistor T4 are turned on, the fourth transistor T4 is said to be turned on; when the fourth transistor T4 is turned off between the first and second poles, the fourth transistor T4 is said to be turned off. A first pole of the fourth transistor T4 is used to input the first power voltage VDD. The second pole of the fourth transistor T4 and the first pole of the driving transistor T0 are connected to the third node d. A control electrode of the fourth transistor T4 is for inputting the fifth SCAN signal SCAN 5. When the fifth SCAN signal SCAN5 is input to the control electrode of the fourth transistor T4, the fourth transistor T4 is turned on, and at this time, the fourth transistor T4 outputs the first power voltage VDD to the third node d. When the fifth SCAN signal SCAN5 is not input to the control electrode of the fourth transistor T4, the fourth transistor T4 is turned off, and the fourth transistor T4 does not output the first power voltage VDD to the third node d.

The fifth transistor T5 has a first pole, a second pole and a control pole. A first pole of the fifth transistor T5 is for inputting an electric signal, and a second pole of the fifth transistor T5 is for outputting an electric signal. The control electrode of the fifth transistor T5 is used to control the on and off between the first and second electrodes of the fifth transistor T5. When the first pole and the second pole of the fifth transistor T5 are turned on, the fifth transistor T5 is said to be turned on; when the fifth transistor T5 is turned off between the first and second poles, the fifth transistor T5 is said to be turned off. A first pole of the fifth transistor T5 is connected to the first node a, and a second pole of the fifth transistor T5 is connected to the third node d. A control electrode of the fifth transistor T5 is for inputting the fourth SCAN signal SCAN 4. When the fourth SCAN signal SCAN4 is inputted to the control electrode of the fifth transistor T5, the fifth transistor T5 is turned on, and at this time, the third node d is connected to the first node a, i.e., the first electrode of the driving transistor T0 is connected to the control electrode. When the fourth SCAN signal SCAN4 is not input to the control electrode of the fifth transistor T5, the fifth transistor T5 is turned off, and at this time, the third node d is disconnected from the first node a, i.e., the first electrode of the driving transistor T0 is disconnected from the control electrode.

The sixth transistor T6 has a first pole, a second pole and a control pole. A first pole of the sixth transistor T6 is for inputting an electric signal, and a second pole of the sixth transistor T6 is for outputting an electric signal. The control electrode of the sixth transistor T6 is used to control the turn-on and turn-off between the first electrode and the second electrode of the sixth transistor T6. When the first pole and the second pole of the sixth transistor T6 are turned on, the sixth transistor T6 is said to be turned on; when the sixth transistor T6 is turned off between the first and second poles, the sixth transistor T6 is said to be turned off. A first pole of the sixth transistor T6 is connected to the first node a, a second pole of the sixth transistor T6 is connected to a first plate of the capacitor C, and a second plate of the capacitor C is connected to the second node b. The control electrode of the sixth transistor T6 is also used to input the fifth SCAN signal SCAN 5. When the fifth SCAN signal SCAN5 is inputted to the control electrode of the sixth transistor T6, the sixth transistor T6 is turned on, and the first node a is connected to the first plate of the capacitor C. When the fifth SCAN signal SCAN5 is not input to the control electrode of the sixth transistor T6, the sixth transistor T6 is turned off, and the first node a is disconnected from the first plate of the capacitor C.

The seventh transistor T7 has a first pole, a second pole and a control pole. A first pole of the seventh transistor T7 is for inputting an electric signal, and a second pole of the seventh transistor T7 is for outputting an electric signal. The control electrode of the seventh transistor T7 is used to control the turn-on and turn-off between the first electrode and the second electrode of the seventh transistor T7. When the first pole and the second pole of the seventh transistor T7 are turned on, the seventh transistor T7 is said to be turned on; when the seventh transistor T7 is turned off between the first and second poles, the seventh transistor T7 is said to be turned off. A first pole of the seventh transistor T7 is used to input the first voltage V1. The second pole of the seventh transistor T7 is connected to the first plate of the capacitor C. The control electrode of the seventh transistor T7 is also used to input the first SCAN signal SCAN 1. When the first SCAN signal SCAN1 is input to the control electrode of the seventh transistor T7, the seventh transistor T7 is turned on, and the seventh transistor T7 outputs the first voltage V1 to the first plate of the capacitor C. When the first SCAN signal SCAN1 is not input to the control electrode of the seventh transistor T7, the seventh transistor T7 is turned off, and the seventh transistor T7 does not output the first voltage V1 to the first plate of the capacitor C.

In some embodiments, in the pixel driving circuit shown in fig. 3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all N-type thin film transistors. When the transistors (including the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) are all N-type thin film transistors, the control electrodes of the transistors are the gates of the N-type thin film transistors, the first electrodes of the transistors are the drains of the N-type thin film transistors, and the second electrodes of the transistors are the sources of the N-type thin film transistors. In other embodiments, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type thin film transistors. When all the transistors are P-type thin film transistors, the control electrodes of all the transistors are the grid electrodes of the P-type thin film transistors, the first electrodes of all the transistors are the source electrodes of the P-type thin film transistors, and the second electrodes of all the transistors are the drain electrodes of the P-type thin film transistors.

The embodiment of the application also provides a pixel driving method which is applied to the pixel driving circuit of the embodiment of the application. Fig. 4 is a timing diagram of a pixel driving method according to a second embodiment of the present application. The operation of the pixel driving circuit shown in fig. 3 will be described in detail with reference to fig. 4.

The timing chart shown in fig. 4 exemplifies that each transistor is an N-type thin film transistor. In the embodiment shown in fig. 4, each of the SCAN signals (including the first SCAN signal SCAN1, the second SCAN signal SCAN2, the third SCAN signal SCAN3, the fourth SCAN signal SCAN4, and the fifth SCAN signal SCAN5) indicates that the SCAN signal is output when it is high, and each of the SCAN signals indicates that the SCAN signal is not output when it is low. As shown in fig. 4, the pixel driving method further includes, in addition to the first embodiment:

s210, in the first period T1, the first SCAN signal SCAN1 is output to the control electrode of the seventh transistor T7 to control the seventh transistor T7 to be turned on to output the first voltage V1 to the first plate of the capacitor C, and the fourth SCAN signal SCAN4 is output to the control electrode of the fifth transistor T5 to control the fifth transistor T5 to be turned on to output the DATA voltage DATA to the first electrode of the driving transistor T0.

In the first period T1, the control electrode of the first transistor T1 and the control electrode of the seventh transistor T7 are both input with the first SCAN signal SCAN 1. A control electrode of the fifth transistor T5 inputs the fourth SCAN signal SCAN 4. That is, the first and fourth SCAN signals SCAN1 and 4 are at a high level for the first period t 1. At this time, the first transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned on. When the first transistor T1 is turned on, the DATA voltage DATA is inputted to the first node a, and the driving transistor T0 is turned on. Also, since the fifth transistor T5 is turned on, the first node a charges the second node b. When the voltage difference of the first node a and the second node b is equal to the threshold voltage of the driving transistor T0, the driving transistor T0 is turned off, and the voltage difference of the gate source of the driving transistor T0 is equal to the threshold voltage. When the seventh transistor T7 is turned on, the first voltage V1 is input to the first plate of the capacitor C.

S220, in the second and third periods T2 and T3, the output of the first SCAN signal SCAN1 is stopped to control the first and seventh transistors T1 and T7 to be turned off, and the output of the fourth SCAN signal SCAN4 is stopped to control the fifth transistor T5 to be turned off, and the fifth SCAN signal SCAN5 is output to the control electrodes of the fourth and sixth transistors T4 and T6 to control the first and sixth transistors T6 to be turned on after the fourth transistor T4 is controlled to output the first power voltage VDD to the first electrode of the driving transistor T0.

In the second and third periods T2 and T3, it is necessary to control the first, fifth, and seventh transistors T1, T5, and T7 to be turned off and the fourth transistor T4 to be turned on so that the first power voltage VDD may be output to the first pole of the driving transistor T0. Thus, in conjunction with step S120, the first sub-pixel OLED1 can be driven to emit light; in conjunction with step S130, the second sub-pixel OLED2 can be driven to emit light.

In the embodiment of the present application, in the step S210, the first transistor T1, the fifth transistor T5, and the seventh transistor T7 are turned on, so that the first node a is charged to the second node b. After the first node a is charged to the second node b, the gate-source voltage difference of the driving transistor T0 is equal to the threshold voltage. In this manner, the threshold voltage of the driving transistor T0 may be compensated, thereby canceling out the threshold voltage of the driving transistor T0.

Example three:

fig. 5 is a schematic structural diagram of a pixel driving circuit according to a third embodiment of the present application. As shown in fig. 5, the pixel driving circuit includes a first transistor T1, a driving transistor T0, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C, and further includes: and an eighth transistor T8.

Specifically, the eighth transistor T8 is an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an indium gallium zinc oxide thin film transistor, or a metal oxide semiconductor thin film transistor. In some specific embodiments, the eighth transistor T8 may be an indium gallium zinc oxide thin film transistor.

The eighth transistor T8 has a first pole, a second pole and a control pole. A first pole of the eighth transistor T8 is for inputting an electric signal, and a second pole of the eighth transistor T8 is for outputting an electric signal. The control electrode of the eighth transistor T8 is used to control the on and off between the first and second electrodes of the eighth transistor T8. When the first pole and the second pole of the eighth transistor T8 are turned on, the eighth transistor T8 is said to be turned on; when the eighth transistor T8 is turned off between the first and second poles, the eighth transistor T8 is said to be turned off. A first pole of the eighth transistor T8 is for inputting the second voltage V2. The second pole of the eighth transistor T8 is connected to the second node b. A control electrode of the eighth transistor T8 is for inputting the sixth SCAN signal SCAN 6. When the sixth SCAN signal SCAN6 is input to the control electrode of the eighth transistor T8, the eighth transistor T8 is turned on, and at this time, the eighth transistor T8 outputs the second voltage V2 to the second node b. When the sixth SCAN signal SCAN6 is not input to the control electrode of the eighth transistor T8, the eighth transistor T8 is turned off, and the eighth transistor T8 does not output the second voltage V2 to the second node b.

In some embodiments, in the pixel driving circuit shown in fig. 5, the eighth transistor T8 is an N-type thin film transistor. When the eighth transistor T8 is an N-type tft, the control electrode of the eighth transistor T8 is the gate electrode of the N-type tft, the first electrode of the eighth transistor T8 is the drain electrode of the N-type tft, and the second electrode of the eighth transistor T8 is the source electrode of the N-type tft. In other embodiments, the eighth transistor T8 is a P-type thin film transistor. When the eighth transistor T8 is a P-type tft, the control electrode of the eighth transistor T8 is the gate electrode of the P-type tft, the first electrode of the eighth transistor T8 is the source electrode of the P-type tft, and the second electrode of the eighth transistor T8 is the drain electrode of the P-type tft.

The embodiment of the application also provides a pixel driving method which is applied to the pixel driving circuit of the embodiment of the application. Fig. 6 is a timing diagram of a pixel driving method according to a third embodiment of the present application. The operation of the pixel driving circuit shown in fig. 5 will be described in detail with reference to fig. 6.

The timing chart shown in fig. 6 exemplifies that each transistor is an N-type thin film transistor. In the embodiment shown in fig. 6, each of the SCAN signals (including the first SCAN signal SCAN1, the second SCAN signal SCAN2, the third SCAN signal SCAN3, the fourth SCAN signal SCAN4, the fifth SCAN signal SCAN5, and the sixth SCAN signal SCAN6) indicates that the SCAN signal is output when it is high, and indicates that the SCAN signal is not output when it is low. As shown in fig. 6, the pixel driving method further includes, on the basis of the second embodiment:

s310, in the reset period T0, outputting a first SCAN signal SCAN1 to control gates of the first transistor T1 and the seventh transistor T7 to output the DATA voltage DATA to a control gate of the driving transistor T0 after the first transistor T1 is turned on, and outputting a first voltage V1 to a first plate of the capacitor C after the seventh transistor T7 is turned on, and outputting a sixth SCAN signal SCAN6 to a control gate of the eighth transistor T8 to output a second voltage V2 to a second plate of the capacitor C after the eighth transistor T8 is turned on; the reset time period t0 precedes the first time period t 1.

In the reset period T0 before the first period T1, the control electrode of the first transistor T1 and the control electrode of the seventh transistor T7 both input the first SCAN signal SCAN1, and the control electrode of the eighth transistor T8 inputs the sixth SCAN signal SCAN 6. That is, in the reset period t0, the first and sixth SCAN signals SCAN1 and SCAN6 are at a high level. At this time, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on. When the first transistor T1 is turned on, the DATA voltage DATA is input to the first node a. When the seventh transistor T7 is turned on, the first voltage V1 is inputted to the first plate of the capacitor C. When the eighth transistor T8 is turned on, the second voltage V2 is inputted to the second node b. When the pixel driving circuit works, the voltage of the first node a in the pixel driving circuit and the voltages of the two polar plates of the capacitor C can be reset in the reset time period t0, so that the DATA voltage DATA residue in one-time working on the pixel driving circuit is avoided, and the display effect of the display panel using the pixel driving circuit is further improved.

The operation of the pixel driving circuit provided in the present application will be explained in detail with reference to fig. 5 and 6, taking the DATA voltage DATA corresponding to the first sub-pixel OLED1 and the second sub-pixel OLED2 as an example, from a specific embodiment.

Example four:

in the embodiment of the present application, the first sub-pixel OLED1 has a first pole and a second pole. The first sub-pixel OLED1 may be an organic light-emitting diode (OLED) or a light-emitting diode (LED). The first pole of the first sub-pixel OLED1 may be an anode of an organic light emitting diode or an anode of a light emitting diode. The second pole of the first sub-pixel OLED1 may be a cathode of an organic light emitting diode or a cathode of a light emitting diode. Likewise, the second sub-pixel OLED2 also has a first pole and a second pole. The second sub-pixel OLED2 may also be an organic light emitting diode or a light emitting diode. The first pole of the second sub-pixel OLED2 may be an anode of an organic light emitting diode or an anode of a light emitting diode. The second pole of the second sub-pixel OLED2 may be a cathode of an organic light emitting diode or a cathode of a light emitting diode. The first and second sub-pixel OLEDs 1 and 2 are different in color. In a specific embodiment, the first and second sub-pixel OLEDs 1 and 2 are both organic light emitting diodes. The first sub-pixel OLED1 is a red sub-pixel, and the second sub-pixel OLED2 is a green sub-pixel.

A first pole of the first sub-pixel OLED1 is connected with a second pole of the second transistor T2. A first pole of the second subpixel OLED2 is connected to a second pole of the third transistor T3. The second pole of the first sub-pixel OLED1 and the second pole of the second sub-pixel OLED2 are both used to input the second power supply voltage VSS. The second power supply voltage VSS is less than.

In the reset period T0, the second, third, fourth and fifth SCAN signals SCAN2, SCAN3, SCAN4 and SCAN5 are low level, the second, third, fifth and fourth transistors T2, T3, T5 are turned off, and the fourth and sixth transistors T4 and T6 are turned off. The first and sixth SCAN signals SCAN1 and SCAN6 are high. Under the first SCAN signal SCAN1, the first transistor T1 and the seventh transistor T7 are turned on. The eighth transistor T8 is turned on by the sixth SCAN signal SCAN 6. When the first transistor T1 is turned on, the DATA voltage DATA is input to the first node a. When the seventh transistor T7 is turned on, the first voltage V1 is inputted to the first plate of the capacitor C. When the eighth transistor T8 is turned on, the second voltage V2 is inputted to the second node b.

The sixth SCAN signal SCAN6 stops being output for the first time period t1, and the sixth SCAN signal SCAN6 is low. Meanwhile, the second, third, and fifth SCAN signals SCAN2, SCAN3, and SCAN5 remain low. In this case, the eighth transistor T8, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off. The first and fourth SCAN signals SCAN1 and SCAN4 are at a high level. Under the first SCAN signal SCAN1, the first transistor T1 and the seventh transistor T7 are turned on. The fifth transistor T5 is turned on by the fourth SCAN signal SCAN 4. When the seventh transistor T7 is turned on, the first voltage V1 is inputted to the first plate of the capacitor C. When the first transistor T1 is turned on, the DATA voltage DATA is input to the first node a. Also, since the fifth transistor T5 is turned on, the first node a charges the second node b. When the voltage difference of the first node a and the second node b is equal to the threshold voltage of the driving transistor T0, the driving transistor T0 is turned off, and the voltage difference of the gate source of the driving transistor T0 is equal to the threshold voltage. That is, at the expiration of the first time period t1, there are:

V_GS1＝V_th(ii) a Wherein, V_GS1A gate-source voltage difference, V, of the driving transistor T0 when the first period T1 is turned off_thIs the threshold voltage of the driving transistor T0.

V_a1＝V_data(ii) a Wherein, V_a1Is the voltage, V, of the first node a at the expiration of the first time period t1_dataIs the voltage of the DATA voltage DATA.

V_C1＝V₁(ii) a Wherein, V_C1Is the voltage, V, of the first plate of the capacitor C at the time of the first time period t1 being off₁Is the voltage of the first voltage V1.

V_b1＝V_data-V_th(ii) a Wherein, V_b1Is the voltage of the second node b at the time when the first period t1 expires.

In the second period t2, the output of the first and fourth SCAN signals SCAN1 and SCAN4 is stopped, and the first and fourth SCAN signals SCAN1 and SCAN4 are at a low level. Meanwhile, the third and sixth SCAN signals SCAN3 and SCAN6 remain at a low level. In this case, the first transistor T1, the seventh transistor T7, the fifth transistor T5, the third transistor T3, and the eighth transistor T8 are turned off. The second SCAN signal SCAN2 and the fifth SCAN signal SCAN5 are high. The fourth transistor T4 and the sixth transistor T6 are turned on by the fifth SCAN signal SCAN 5. The second transistor T2 is turned on by the second SCAN signal SCAN 2. When the fourth transistor T4 is turned on, the first power voltage VDD is output to the first electrode of the driving transistor T0 through the fourth transistor T4, so that the driving transistor T0 outputs an electrical signal, and the first sub-pixel OLED1 is driven to emit light through the second transistor T2.

At this time, since the second polarity of the first subpixel OLED1 inputs the second power voltage VSS, during the second period t2, there are:

V_b2＝Vss+V_OLED1(ii) a Wherein, V_b2Is the voltage of the second node b during the second period t2, Vss is the voltage of the second supply voltage VSS, V_OLED1Is the voltage of the first sub-pixel OLED1 during the second period t 2. Compared with the first timeFor the period t1, the voltage variation of the second node b is:

V_b2-V_b1＝Vss+V_OLED1-(V_data-V_th)。

under the coupling effect of the capacitor C, the voltage variation of the first plate of the capacitor C is equal to the voltage variation of the second node b, so that it can be obtained that in the second time period t2, there are:

V_C2＝V_C1+V_b2-V_b1＝V₁+Vss+V_OLED1-(V_data-V_th) (ii) a Wherein, V_C2Is the voltage of the first plate of the capacitor C during the second time period t 2.

Also, since the sixth transistor T6 is turned on, the voltage of the first node a during the second period T2 is equal to the voltage of the first plate of the capacitor C, that is:

V_a2＝V₁+Vss+V_OLED1-(V_data-V_th) (ii) a Wherein, V_a2Is the voltage of the first node a during the second time period t 2.

According to the above formula and the current calculation formula of the driving transistor T0, during the second time period T2, the current outputted from the driving transistor T0 to the first sub-pixel OLED1 is:

wherein, V_GS2Is the gate-source voltage difference of the driving transistor T0 in the second time period T2, μ is the electron mobility rate, C_oxThe capacitance C per unit area of the gate oxide layer of the driving transistor T0, W is the channel width of the driving transistor T0, and L is the channel length of the driving transistor T0. It can be seen that the magnitude of the current outputted from the driving transistor T0 to the first sub-pixel OLED1 is determined by the first voltage V1 and the DATA voltage DATA, and the threshold voltage of the driving transistor T0 is eliminated. In this case, when the first sub-pixel OLED1 is driven to emit light, the threshold voltage of the driving transistor T0 does not affect the light emission luminance of the first sub-pixel OLED1, so that the use can be improvedThe pixel driving circuit has the display effect of a display panel. The first voltage V1 may be a fixed voltage. Meanwhile, the influence of the required voltage increase when the first sub-pixel OLED1 emits light caused by aging of the first sub-pixel OLED1 on the light emission brightness can be eliminated.

In the third time period t3, the output of the second SCAN signal SCAN2 is stopped, and the second SCAN signal SCAN2 is low. The first, fourth, and sixth SCAN signals SCAN1, SCAN4, and SCAN6 are still low. In this case, the first transistor T1, the seventh transistor T7, the fifth transistor T5, the second transistor T2, and the eighth transistor T8 are turned off. The third and fifth SCAN signals SCAN3 and SCAN5 are high. The fourth transistor T4 and the sixth transistor T6 are turned on by the fifth SCAN signal SCAN 5. The third transistor T3 is turned on by the third SCAN signal SCAN 3. When the fourth transistor T4 is turned on, the first power voltage VDD is output to the first electrode of the driving transistor T0 through the fourth transistor T4, so that the driving transistor T0 outputs an electrical signal to drive the second sub-pixel OLED2 to emit light through the third transistor T3.

At this time, since the second power voltage VSS is input to the second pole of the second sub-pixel OLED2, during the third period t3, there are:

V_b3＝Vss+V_OLED2(ii) a Wherein, V_b3Is the voltage of the second node b during the third period t3, Vss is the voltage of the second power supply voltage VSS, V_OLED2Is the voltage of the second sub-pixel OLED2 during the third period t 3. Compared to the first time period t1, the voltage variation of the second node b is:

V_b3-V_b1＝Vss+V_OLED2-(V_data-V_th)。

under the coupling effect of the capacitor C, the voltage variation of the first plate of the capacitor C is equal to the voltage variation of the second node b, so that it can be obtained that in the third time period t3, there are:

V_C3＝V_C1+V_b3-V_b1＝V₁+Vss+V_OLED2-(V_data-V_th) (ii) a Wherein, V_C3For a third period of time t3 the voltage of the first plate of the internal capacitor C.

Also, since the sixth transistor T6 is turned on, the voltage of the first node a during the third period T3 is equal to the voltage of the first plate of the capacitor C, that is:

V_a3＝V₁+Vss+V_OLED2-(V_data-V_th) (ii) a Wherein, V_a3Is the voltage of the first node a during the third time period t 3.

According to the above formula and the current calculation formula of the driving transistor T0, during the third time period T3, the current outputted from the driving transistor T0 to the second sub-pixel OLED2 is:

wherein, V_GS3Is the gate-source voltage difference of the driving transistor T0 in the third time period T3, μ is the electron mobility rate, C_oxThe capacitance C per unit area of the gate oxide layer of the driving transistor T0, W is the channel width of the driving transistor T0, and L is the channel length of the driving transistor T0. It can be seen that the magnitude of the current outputted from the driving transistor T0 to the second sub-pixel OLED2 is determined by the first voltage V1 and the DATA voltage DATA, and the threshold voltage of the driving transistor T0 is eliminated. In this case, when the second sub-pixel OLED2 is driven to emit light, the light emission luminance of the second sub-pixel OLED2 is not affected by the threshold voltage of the driving transistor T0, so that the display effect of the display panel using the pixel driving circuit can be improved. Meanwhile, the influence of the required voltage increase of the second sub-pixel OLED2 on the light emitting brightness caused by the aging of the second sub-pixel OLED2 can be eliminated. The first voltage V1 may be a fixed voltage.

The pixel driving circuit can drive two sub-pixels. That is, two subpixels may share one DATA line for outputting the DATA voltage DATA. Therefore, one third of data lines can be saved for the display panel using the pixel driving circuit, which is beneficial to realizing the narrow lower frame of the display panel, thereby increasing the screen occupation ratio of the display panel and improving the display effect of the display panel.

The following explains the display panel provided in the embodiments of the present application in detail.

Example five:

the embodiment of the present application further provides a display panel, which includes a plurality of first sub-pixel OLEDs 1, a plurality of second sub-pixel OLEDs 2, and a pixel driving circuit as described in any of the above embodiments.

Wherein the pixel driving circuit is used for outputting a driving signal to the sub-pixel, and the pixel driving circuit comprises: a first transistor T1, a driving transistor T0, a second transistor T2, and a third transistor T3. A first electrode of the first transistor T1 is for inputting the DATA voltage DATA, and a second electrode of the first transistor T1 and a control electrode of the driving transistor T0 are connected to the first node a. A first pole of the driving transistor T0 is for inputting the first power voltage VDD, and a second pole of the driving transistor T0, a first pole of the second transistor T2, and a first pole of the third transistor T3 are connected to the second node b. The second pole of the second transistor T2 is for connection with the first sub-pixel OLED1 to output a driving signal to the first sub-pixel OLED1 when the second transistor T2 is turned on. The second pole of the third transistor T3 is used to connect with the second sub-pixel OLED2 except for the first sub-pixel OLED1 to output a driving signal to the second sub-pixel OLED2 when the third transistor T3 is turned on.

First poles of the plurality of first sub-pixels OLED1 are connected one to the second pole of the second transistor T2 of the plurality of pixel driving circuits, and first poles of the plurality of second sub-pixels OLED2 are connected one to the second pole of the third transistor T3 of the plurality of pixel driving circuits. The second pole of the plurality of first sub-pixels OLED1 and the second pole of the plurality of second sub-pixels OLED2 are used to input a second power voltage VSS, which is less than the first power voltage VDD.

In some embodiments, the first sub-pixel OLED1 is a red sub-pixel, and the second sub-pixel OLED2 is a green sub-pixel.

In some embodiments, the pixel driving circuit further comprises: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.

A first pole of the fourth transistor T4 is for inputting the first power voltage VDD, and a second pole of the fourth transistor T4 and the first pole of the driving transistor T0 are connected to the third node d, so that when the fourth transistor T4 is turned on, the first pole of the driving transistor T0 inputs the first power voltage VDD. A first pole of the fifth transistor T5 is connected to the first node a, and a second pole of the fifth transistor T5 is connected to the third node d. A first pole of the sixth transistor T6 is connected to the first node a, a second pole of the sixth transistor T6 is connected to a first plate of the capacitor C, and a second plate of the capacitor C is connected to the second node b. A first pole of the seventh transistor T7 is used for inputting the first voltage V1, and a second pole of the seventh transistor T7 is connected to the first plate of the capacitor C.

In some embodiments, the pixel driving circuit further comprises: and an eighth transistor T8.

A first pole of the eighth transistor T8 is for inputting the second voltage V2, and a second pole of the eighth transistor T8 is connected to the second node b.

In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the driving transistor T0 are all amorphous silicon thin film transistors, low temperature polysilicon thin film transistors, indium gallium zinc oxide thin film transistors, or metal oxide semiconductor thin film transistors.

In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the driving transistor T0 are all N-type thin film transistors.

In the embodiments of the present application, the display panel includes the pixel driving circuit as in any one of the embodiments described above. The pixel driving circuit includes a first transistor T1, a driving transistor T0, a second transistor T2, and a third transistor T3. When the first transistor T1 is turned on, the DATA voltage DATA may be input to the gate of the driving transistor T0 through the first transistor T1. The DATA voltage DATA is used to control the driving transistor T0 to be turned on and to control the magnitude of the output electrical signal of the driving transistor T0. The second transistor T2 is connected between the second pole of the driving transistor T0 and the first sub-pixel OLED1, and the third transistor T3 is connected between the second pole of the driving transistor T0 and the second sub-pixel OLED2, so that, when the DATA voltage DATA is input to the control electrode of the driving transistor T0, if the second transistor T2 is turned on, the second transistor T2 outputs a driving signal to the first sub-pixel OLED 1; if the third transistor T3 is turned on, the third transistor T3 outputs a driving signal to the second sub-pixel OLED 2. That is, the pixel driving circuit may drive two sub-pixels. In this case, under the condition that the number of the pixel driving circuits on the display panel is the same, the pixel driving circuit provided by the application can increase the number of the sub-pixels on the display panel, so that the resolution of the display panel is increased. For the display panel applying the pixel driving circuit, one third of data lines can be saved, which is beneficial to realizing the narrow lower frame of the display panel, thereby increasing the screen occupation ratio of the display panel and improving the display effect of the display panel.

The pixel driving circuit operates to remove the threshold voltage of the driving transistor T0. In this case, when the sub-pixel is driven to emit light, the threshold voltage of the driving transistor T0 does not affect the emission luminance of the sub-pixel, so that the display effect of the display panel using the pixel driving circuit can be improved.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A pixel driving circuit, comprising: a first transistor, a driving transistor, a second transistor, and a third transistor;

2. The pixel driving circuit according to claim 1, wherein the pixel driving circuit further comprises: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor;

3. The pixel driving circuit according to claim 2, wherein the pixel driving circuit further comprises: an eighth transistor;

4. The pixel driving circuit according to claim 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the driving transistor are each an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an indium gallium zinc oxide thin film transistor, or a metal oxide semiconductor thin film transistor.

5. The pixel driving circuit according to claim 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the driving transistor are all N-type thin film transistors.

6. A pixel driving method applied to the pixel driving circuit according to any one of claims 1 to 5, the pixel driving method comprising:

7. The pixel driving method according to claim 6, wherein the pixel driving circuit further comprises: a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor;

the pixel driving method further includes:

in the first time period, outputting a first scanning signal to a control electrode of the seventh transistor to control the seventh transistor to be turned on and then outputting a first voltage to a first plate of the capacitor, and outputting a fourth scanning signal to a control electrode of the fifth transistor to control the fifth transistor to be turned on and then outputting the data voltage to a first electrode of the driving transistor;

8. The pixel driving method according to claim 7, wherein the pixel driving circuit further comprises: an eighth transistor;

the pixel driving method further includes:

in a reset time period, outputting a first scanning signal to control electrodes of the first transistor and the seventh transistor to control the first transistor to be turned on and then outputting the data voltage to a control electrode of the driving transistor, outputting the first voltage to a first plate of the capacitor after the seventh transistor is turned on, and outputting a sixth scanning signal to a control electrode of the eighth transistor to control the eighth transistor to be turned on and then outputting a second voltage to a second plate of the capacitor; the reset time period precedes the first time period.

9. A display panel comprising a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of pixel driving circuits according to any one of claims 1 to 5;

10. The display panel of claim 9, wherein the first sub-pixel is a red sub-pixel and the second sub-pixel is a green sub-pixel.