CN114023365A - Method, apparatus and system for configuring NAND die - Google Patents

Abstract

Embodiments of the present application provide methods for configuring a NAND die, NAND dies, NAND memory devices, host devices, and memory systems. The method comprises the following steps: receiving trimming option information from a host device, wherein the trimming option information comprises a trimming command, and the trimming command is used for indicating a desired trimming option in a plurality of preset trimming options; selecting a target trim profile from a plurality of trim profiles based on trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile comprising a set of operating parameters associated with the NAND die; the NAND die is configured with a target trim profile.

Description

Method, apparatus and system for configuring NAND die

Technical Field

The present application relates generally to memory technology, and in particular, to a method for configuring a NAND die, a NAND memory device, a host device, and a memory system.

Background

In recent years, rapid progress has been made due to the superior memory performance of NAND memory devices. Generally, NAND memory devices are capable of retaining stored data for a very long period of time without the application of a voltage. In addition, the read rate of the NAND memory device is very high, and it is easy to erase stored data and rewrite data into the NAND memory device. Accordingly, NAND memory devices have been widely used in various types of devices, such as mobile computing devices, servers, and the like.

Disclosure of Invention

In view of the above-identified problems of the prior art, embodiments of the present application provide a method for configuring a NAND die, a NAND memory device, a host apparatus, and a memory system.

In one aspect, embodiments of the present application provide a method for configuring a NAND die, comprising: receiving trimming option information from a host device, wherein the trimming option information includes a trimming command indicating a desired trimming option of a preset plurality of trimming options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die; configuring the NAND die with the target trim profile.

In another aspect, embodiments of the present application provide a method for configuring a NAND die, comprising: generating trimming option information, wherein the trimming option information comprises a trimming command, and the trimming command is used for indicating a desired trimming option in a plurality of preset trimming options; sending the trim option information to a NAND die for the NAND die to select a target trim profile for configuration from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die.

In another aspect, embodiments of the present application provide a NAND die comprising: an array of memory cells; at least one peripheral circuit coupled to the memory cell array, wherein the at least one peripheral circuit is configured to: receiving trimming option information from a host device, wherein the trimming option information includes a trimming command indicating a desired trimming option of a preset plurality of trimming options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die; configuring the NAND die with the target trim profile.

In another aspect, an embodiment of the present application provides a NAND memory device, including: at least one NAND die, wherein: each NAND die includes an array of memory cells and at least one peripheral circuit coupled to the array of memory cells; for a first NAND die of any of the at least one NAND die, at least one peripheral circuit in the first NAND die is configured to: receiving trimming option information from a host device, wherein the trimming option information includes a trimming command indicating a desired trimming option of a preset plurality of trimming options; selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the first NAND die; configuring the first NAND die with the target trim profile.

In another aspect, an embodiment of the present application provides a host device, including: a processor; a memory configured to store executable code that, when executed by the processor, causes the processor to: generating trimming option information, wherein the trimming option information comprises a trimming command, and the trimming command is used for indicating a desired trimming option in a plurality of preset trimming options; sending the trim option information to a NAND die for the NAND die to select a target trim profile for configuration from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die.

In another aspect, an embodiment of the present application provides a storage system, including: a NAND memory device comprising at least one NAND die; a host device coupled with the at least one NAND die, wherein: the host device is configured to: generating trimming option information for a first NAND die of the at least one NAND die, wherein the trimming option information comprises a trimming command indicating a desired trimming option of a preset plurality of trimming options; sending the trim option information to the first NAND die; the first NAND die is configured to: selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the first NAND die; configuring the first NAND die with the target trim profile.

Drawings

The foregoing and other objects, features and advantages of embodiments of the present application will become more apparent from the following more particular description of embodiments of the present application, as illustrated in the accompanying drawings in which like reference characters refer to the same elements in general.

FIG. 1A is a schematic illustration of an application environment in which some embodiments of the present application may be applied.

FIG. 1B further illustrates a schematic block diagram of a NAND die, in accordance with some embodiments.

Fig. 2 is a schematic flow diagram of a method for configuring a NAND die, in accordance with some embodiments.

FIG. 3 illustrates an example of a storage format of trim commands and verification codes in a NAND die, according to some embodiments.

FIG. 4 is a method for configuring a NAND die, according to some embodiments.

Fig. 5A and 5B are flow diagrams of examples of methods for configuring a NAND die.

Fig. 6 is a schematic block diagram of a host device according to some embodiments.

Detailed Description

The subject matter described herein will now be discussed with reference to various embodiments. It should be understood that these examples are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and are not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the claims. Various embodiments may omit, replace, or add various procedures or components as desired.

As used herein, the term "include" and its variants mean open-ended terms in the sense of "including, but not limited to. The term "based on" means "based at least in part on". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first," "second," and the like may refer to different or the same object. Other definitions, whether explicit or implicit, may be included below, and a definition of a term is consistent throughout the specification unless the context clearly dictates otherwise.

NAND memory devices may typically include one or more NAND dies (die) to implement memory functions. In general, NAND dies can be classified into different grades depending on their performance, and the different grades can correspond to different application scenarios. For example, current NAND dies can be generally classified as enterprise (enterprise), mobile (mobile), and client (client). For example, enterprise-level NAND dies may be generally applied to enterprise-level servers and the like, mobile-level NAND dies may be applied to mobile phones, tablet devices and the like, client-level NAND dies may be applied to laptops and the like. The NAND dies of the various levels may differ in performance emphasis. For example, enterprise-level NAND dies may be primarily responsive and reliable, mobile-level NAND dies may be primarily responsive, and customer-level NAND dies may be focused on low cost in meeting demand. Of course, as technology evolves, market demands, etc., NAND dies may be further ranked.

It is common to have different trim settings for different levels of NAND die. That is, different levels may correspond to different trim settings. A trim setting may be understood as a set of operating parameter settings of the NAND die such as voltage, current, temperature compensation, power, etc. The NAND die can be configured to achieve performance corresponding to that level by trimming the settings. Currently, after determining the rank of a NAND die, the corresponding trim settings will typically be preconfigured in the NAND die. However, in some cases, the rank of the NAND die may need to be adjusted, and then the corresponding trim settings need to be reconfigured or tested for the NAND die, and such a process may be time consuming and complex.

In view of this, embodiments of the present application provide a solution for configuring a NAND die. The following detailed description will be given in conjunction with various embodiments.

FIG. 1A is a schematic illustration of an application environment in which some embodiments of the present application may be applied.

In the example of FIG. 1A, application environment 100 may include a host device 110 and a NAND memory device 120. It should be understood that the application environment 100 may also include other devices, which are not shown here for clarity of illustration, and are not limited herein, depending on the particular implementation.

The host device 110 may generally be any device configured to interact with the NAND memory device, such as a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), a microcontroller, and so forth.

NAND memory device 120 may include one or more NAND dies 130. For example, NAND memory device 120 may be packaged with one NAND die, or may be packaged with multiple NAND dies, although this is not a limitation herein.

Generally, the NAND storage device 120 can be applied in various scenarios, for example, the NAND storage device 120 can be applied to a Solid State Disk (SSD), an Embedded multimedia Card (eMMC), a smart phone, a tablet device, and the like. When NAND memory device 120 is in different scenarios, host device 110 may be implemented by different devices accordingly.

For example, in the case where the NAND storage 120 is applied to an SSD, the host apparatus 110 may be implemented by a controller in the SSD. In this case, the application environment 100 of fig. 1A may represent a schematic structure of an SSD. Of course, the examples herein are merely for ease of understanding, and in actual implementation, the SSD may also include other modules or units, which are not limited herein.

For example, where the NAND storage 120 is applied to an eMMC, the host device 110 may be implemented by an eMMC controller in the eMMC. In this case, the application environment 100 of fig. 1A may represent a schematic structure of eMMC. Of course, the eMMC may also have other modules or units, which are not limited herein.

As another example, host device 110 may be implemented by a test platform in the case of NAND memory device 120 under test. In this case, the application environment of fig. 1A may represent a test environment for a NAND memory device.

Typically, NAND dies may be cut from a processed wafer, each NAND die having its own memory cell array and peripheral circuitry. In some cases, a NAND die may be referred to as a NAND die or other name. FIG. 1B further illustrates a schematic block diagram of a NAND die, in accordance with some embodiments. As shown in fig. 1B, the NAND die 130 may include a memory cell array 131 and various suitable peripheral circuits coupled to the memory cell array 131. In some implementations, the memory cell array 131 can be an array of 3D NAND memory cells, which can have the form of vertically extending NAND memory strings.

In addition, the peripheral circuits may include various appropriate circuits such as a control logic unit 132, a page buffer/sense amplifier 133, a column decoder/bit line driver 134, an I/O circuit 135, a row decoder/word line driver 136, a register 137, an Interface (I/F) 138, a data bus 139, and the like, which are shown in fig. 1B. It should be understood that the various circuits shown in FIG. 1B are for illustration only, and that in different implementation scenarios, a NAND die may include fewer or more peripheral circuits, and are not limited herein.

In addition, the functions of these circuits are known in the art and will not be described in detail here. For example, the control logic 132 may be coupled to various other peripheral circuits to perform control or management functions on the NAND die, such as controlling the peripheral circuits in the NAND die to control the memory cell array 131. In different implementations, the control logic unit 132 may also have other names, such as a microcontroller unit (MCU), a state machine, and so on.

As previously described, host device 110 may interact with NAND die 130. For example, referring to fig. 1B, host device 110 may communicate with control logic 132 via interface 138, such as to send commands, information, and so forth relating to embodiments herein to control logic 132 via interface 138. The control logic 132 may then control or manage the NAND die 130 according to commands, information, etc., of the host device.

Additionally, as previously described, NAND memory device 120 may include multiple NAND dies. In this case, host device 110 may interact with each NAND die separately, e.g., to change its trim settings, etc. The process by which the host device interacts with a certain NAND die will be described in detail below. In the case of multiple NAND dies, the interaction process of the host device with the individual NAND dies is similar.

Fig. 2 is a schematic flow diagram of a method for configuring a NAND die, in accordance with some embodiments. For example, the NAND die may be the NAND die 130 in fig. 1A and 1B, and the method 200 of fig. 2 may be performed by the control logic unit 132 in fig. 1B.

As shown in fig. 2, in step 202, trimming option information may be received from a host device. The trimming option information may include at least a trimming command. The trim command may be used to indicate a desired trim option of a preset plurality of trim options.

In step 204, a target trim profile may be selected from a plurality of trim profiles based on the trim option information.

In some embodiments, a plurality of trim options may be respectively associated with a plurality of trim profiles. In particular, each trimming option may be associated with a trimming profile. The trim profile may include trim settings. In particular, the trim profile may include a set of operating parameters associated with the NAND die, such as current, voltage, power, temperature compensation, and so forth. For example, the trim profile may include specific values, ranges of values, functions used to determine the parameters, and so on for each parameter. Multiple trim profiles may be stored in the NAND die in advance. For example, multiple trim profiles may be pre-stored in a configuration block of a NAND die. In addition, the correspondence of the trimming options and trimming profiles may also be stored in advance in the NAND die, such as in a configuration block of each NAND die.

In step 206, the NAND die may be configured with the target trim profile.

As can be seen from the above, in the embodiment of the present application, a plurality of trimming options may be set in advance and a plurality of trimming profiles respectively associated with the plurality of trimming options may be stored in advance in the NAND die. In this way, trim settings for the NAND die can be easily and efficiently readjusted. For example, when the level of the NAND die needs to be adjusted, the NAND die can be configured by directly selecting an appropriate trimming profile from a plurality of trimming profiles stored in the NAND die in advance without temporarily loading the trimming profile to be used in the NAND die, so that trimming of the NAND die can be efficiently achieved.

In some embodiments, the plurality of trimming options may be divided into default trimming options and non-default trimming options. For example, among the plurality of trimming options, one trimming option is a default trimming option, and the remaining trimming options may be non-default trimming options. For example, in one implementation, four trimming options, namely trimming option 0, trimming option 1, trimming option 2, and trimming option 3, may be preset. Trim option 0 may be designated as a default trim option while the remaining trim options are non-default trim options. In some cases, different trim options may correspond to different levels of NAND dies.

In this case, in step 204, it may be determined whether the intended trimming option is a default trimming option or a non-default trimming option. A target trim profile may then be selected from the plurality of trim profiles based on the determination for the desired trim options.

In some embodiments, where it is determined that the intended trimming option is the default trimming option, a trimming profile corresponding to the intended trimming option may be selected from the plurality of trimming profiles as the target trimming profile.

In some embodiments, the intended trimming option may be a non-default trimming option. In this case, to prevent the host device from arbitrarily changing the trim settings of the NAND die, security verification may be performed. For example, in some implementations, the host device may also send a passcode associated with the desired trimming option. In one implementation, the host device may send the trim command along with the authentication code. For example, the trimming option information may include a verification code in addition to the trimming command. In step 204, a first preset security code of the plurality of preset security codes associated with the intended trimming option may be obtained if it is determined that the intended trimming option is a non-default trimming option. A plurality of preset security codes may be pre-stored in the NAND die. Each trimming option may be associated with a preset security code.

It may then be determined whether the received verification code matches a first preset security code. The target trim profile may be selected based on a result of a match of the verification code with the first preset security code.

For example, the host device may be considered authorized to adjust trim settings of the NAND die in the event that it is determined that the received verification code matches a first preset security code. Accordingly, a trim profile associated with a desired trim option may be selected from the plurality of trim profiles as the target trim profile.

In the event that it is determined that the received verification code does not match the first preset security code, it may be assumed that the host device may not be authorized to adjust trim settings of the NAND die. Accordingly, a trim profile associated with the default trim option may be selected from the plurality of trim profiles as the target trim profile.

In this way, it can be ensured that the trim settings of the NAND die are changed in the event that the host device is authorized, thereby effectively preventing potential problems with randomly changing trim settings of the NAND die.

In different embodiments, the verification code may be implemented in different ways.

For example, the authentication code may be represented by a single value (e.g., a size of 8 bits), which may reduce signaling overhead.

As another example, to further increase security, the passcode may be represented by a combination of values, each of which may have the same or different size. For example, each value may be 8 bits in size. In this case, the host device may send multiple values to the NAND die at once, or may develop multiple values to the NAND die. The NAND die, upon receiving the plurality of values, may combine the plurality of values to form the verification code to be used.

In some implementations, the control logic, upon receiving the trimming option information from the host device, may store the trimming option information as a parameter at a specified location for subsequent command execution, recording, querying, or the like.

For example, the trim command may be represented by 2 bits. In the case where the authentication code is present and is represented by a single value, the authentication code may be represented by 8 bits. To prevent writing errors or loss of information, the authentication code may be stored in a backup manner. For example, the authentication code may be stored as three copies, each of which takes 8 bits.

As another example, the trim command may be represented by 2 bits. In the case where the authentication code exists and is represented by a combination of a plurality of values, each value may be represented by 8 bits. Thus, the entire authentication code may occupy 3 bytes.

FIG. 3 illustrates an example of a storage format of trim commands and verification codes in a NAND die, according to some embodiments.

The example of fig. 3 will be described below in connection with the application scenarios of fig. 1A and 1B. For example, after control logic 132 receives the trim command and the authentication code of host device 110, control logic 132 may write this information at the specified location.

In the example of fig. 3, it is assumed that there are four trimming options: trimming option 0 as a default option, trimming options 1, 2 and 3 as non-default options.

Additionally, in the example of FIG. 3, bits 0-1 of parameter P1 may be used to store trim commands, and in particular, trim options. Bits 2-7 of parameter P1 may be reserved. The parameters P2, P3, and P4 may store the passcode received from the host device.

As previously described, the authentication code may be represented by a single value or a combination of values. For ease of understanding, the following will be exemplified separately.

(1) For implementations where the authentication code is represented by a single value:

the parameters P2, P3, and P4 may store the same values to serve as backups.

If the trim command indicates trim option 0, then no verification code is needed. In this case, bits 0-1 of parameter P1 may store a value representing trim option 0, such as 00. Since the verification code is not received, the parameters P2, P3, and P4 may be null.

If the trim command indicates trim option 1, and assume that the verification code associated therewith is a value of X. In this case, bits 0-1 of parameter P1 may store a value representing trim option 1, such as 01. The 8 bits of each of the parameters P2, P3, and P4 may all be used to store a value X.

If the trim command indicates trim option 2, and assume that the verification code associated therewith is the value Y.

In this case, bits 0-1 of parameter P1 may store a value representing trim option 2, such as 10. The 8 bits of each of the parameters P2, P3, and P4 may all be used to store the value Y.

If the trim command indicates trim option 3, and assume that the verification code associated therewith is the value Z.

In this case, bits 0-1 of parameter P1 may store a value representing trim option 3, such as 11. The 8 bits of each of the parameters P2, P3, and P4 may all be used to store the value Z.

(2) For implementations in which the captcha is represented by a combination of multiple values:

here, it is assumed that the authentication code is represented by a combination of three values.

If the trim command indicates trim option 0, then no verification code is needed. In this case, bits 0-1 of parameter P1 may store a value representing trim option 0, such as 00. Since the verification code is not received, the parameters P2, P3, and P4 may be null.

If the trim command indicates trim option 1, and assume that the verification code associated therewith is the value ABC. That is, the verification code associated with trimming option 1 consists of three values, A, B and C. Combining these three values may then form the verification code associated with trim option 1, where ABC is used to denote the combination of these three values. In this case, bits 0-1 of parameter P1 may store a value representing trim option 1, such as 01. The 8 bits of each of the parameters P2, P3, and P4 may be used to store the value A, B, C, respectively. For example, ABC may be 24' h 77696E.

If the trim command indicates trim option 2, and assume that the verification code associated therewith is the value DEF. That is, the verification code associated with trimming option 1 consists of three values, namely D, F and F. Combining these three values may then form the verification code associated with trim option 2, where DEF is used to represent the combination of these three values. In this case, bits 0-1 of parameter P1 may store a value representing trim option 2, such as 10. The 8 bits of each of the parameters P2, P3, and P4 may be used to store the value D, E, F, respectively. For example, DEF may be 24' h676F 64.

If the trim command indicates trim option 3, and assume that the authentication code associated therewith is the value GHI. That is, the passcode associated with trim option 3 consists of three values, G, H and I. Combining these three values may then form the authentication code associated with trim option 3, where GHI is used to denote the combination of these three values. In this case, bits 0-1 of parameter P1 may store a value representing trim option 3, such as 11. The 8 bits of each of the parameters P2, P3, and P4 may be used to store the value G, H, I, respectively. For example, the GHI may be 24' h796D 74.

Additionally, multiple preset security codes may be pre-programmed in the configuration blocks of the NAND die. As can be seen from the above, the verification code and the preset security code may correspond. That is, the authentication code and the preset security code are the same size. For example, for the previous example with four trimming options (one of which is the default option), three preset security codes are required. If each preset security code is represented by a combination of three values, the preset security codes may occupy a total of 3 × 3 bytes. If each preset security code is represented by a single value, the preset security codes may occupy a total of 3 × 1 bytes. In actual operation, after the NAND die is powered on, these preset security codes may be loaded into Static Random Access Memory (SRAM) in the NAND die. Therefore, when the trimming option needs to be verified, the corresponding preset security code can be directly read from the SRAM.

FIG. 4 is a method for configuring a NAND die, according to some embodiments. The method 400 of FIG. 4 may be performed by a host device in communication with a NAND die, such as the host device 110 shown in FIG. 1A. The method 400 of fig. 4 corresponds to the method 300 of fig. 3, and thus some repetitive description will be omitted here.

As shown in fig. 4, in step 402, trimming option information may be generated.

The trimming option information may include a trimming command. The trim command may be used to indicate a desired trim option of a preset plurality of trim options.

In step 404, trim option information may be sent to the NAND die for the NDNA die to select a target trim profile from a plurality of trim profiles for configuration based on the trim option information.

Multiple trim profiles may be pre-stored in the NAND die. Each trim option may be associated with a trim profile. Each trim profile may include a set of operating parameters associated with the NAND die.

In some embodiments, the plurality of trimming options may be divided into default trimming options and non-default trimming options.

In the case where the intended trimming option is a non-default trimming option, the trimming option information may also include a verification code associated with the intended trimming option.

In some embodiments, the trimming option information may include a plurality of values that collectively make up the verification code.

For ease of understanding, the following description will be made in conjunction with specific examples. It should be understood that the following examples do not limit the scope of the present application.

Fig. 5A and 5B are flow diagrams of examples of methods for configuring a NAND die. Fig. 5A and 5B are still described below in conjunction with fig. 1.

In step 501, the host device 110 may send a power-on command sequence to the control logic 132 of the NAND die 130.

In step 502, the control logic 132 may control the NAND die 130 to power up according to a power up command sequence of the host device 110.

In step 503, host device 110 may send a device initialization command to control logic 132.

In step 504, the control logic 132 may control the initialization of the NAND die 130 according to the device initialization command.

These operations are known in the art and therefore will not be described in detail herein.

In step 505, host device 110 may send trimming option information to control logic unit 132. As previously described, the trim option information may include trim commands indicating desired trim options. Additionally, if the expected trimming option is a non-default trimming option, the trimming option information may also include an associated verification code. The specific implementation of the trim command may depend on the specific application scenario. For example, in the case where the NAND memory device 120 includes only a single NAND die, the trim command may be a set feature command, such as may be represented by EFh (16 m). In the case where NAND storage device 120 includes multiple NAND dies, the trim command may be a set trim by LUN, such as may be represented by D5h (16M), thereby indicating the trim option and the associated NAND die. It can be seen that in embodiments herein, the trim settings can be flexibly changed for individual NAND dies of a NAND memory device, thereby enabling various application requirements to be met.

In step 506, host device 110 may send a hard reset command to control logic unit 132. For example, a hard reset command may be denoted as FDh, which is used to initiate the process of modifying trim settings.

In step 507, the control logic unit 132 may select a trim profile based on the trim option information.

In step 508, control logic 132 may load the selected trim profile. For example, the control logic 132 may configure the NAND die 130 with the selected trim profile.

It should be understood that the steps described above are not necessarily performed in the order shown in fig. 5A, and the order of performing the steps is mainly determined by the specific implementation.

For further understanding, the specific process of step 507 is described below in conjunction with the example of fig. 5B. In the example of fig. 5B, it is assumed that there are 4 trim options, trim options 0-3, and trim option 0 is assumed to be the default trim option. Additionally, assume that trim options 0-3 are associated with trim profiles 0-3, respectively. Further, assume that trimming option 1 is associated with preset security code ABC, trimming option 2 is associated with preset security code DEF, and trimming option 3 is associated with preset security code GHI.

In step 507, the control logic 132 may determine whether the desired trim option is trim option 0. If so, control logic 132 may select trim profile 0.

If not trim option 0, control logic 132 may determine whether the desired trim option is trim option 1. If so, control logic 132 may determine whether the verification code in the trim options information matches ABC. If there is a match, control logic 132 may select trim profile 1. If there is no match, control logic 132 may select default trim profile 0.

If not, control logic 132 may determine whether the desired trim option is trim option 2. If so, the control logic 132 may determine whether the verification code in the trim option information matches the DEF. If there is a match, control logic 132 may select trim profile 2. If there is no match, control logic 132 may select default trim profile 0.

If not trim option 2, control logic 132 may determine whether the desired trim option is trim option 3. If so, control logic 132 may determine whether the verification code in the trim options information matches the GHI. If there is a match, control logic 132 may choose to trim profile 3. If there is no match, control logic 132 may select default trim profile 0.

It can be seen that in this way, the trimming settings of the NAND die can be modified with assurance that the host device is authorized, thereby avoiding potential hazards associated with modifying the trimming settings of the NAND die at will.

Fig. 6 is a schematic block diagram of a host device according to some embodiments. For example, host device 600 of fig. 6 may correspond to host device 110 of fig. 1.

As shown in fig. 6, host device 600 may include a processor 602 and memory 604. The processor 602 and the memory 604 may be connected together via a bus.

The memory 604 may store executable code that, when executed by the processor 602, may cause the processor 602 to implement the specific processes described above with respect to the host device.

From the above description, it can be seen that embodiments of the present application may provide a NAND die that may include an array of memory cells and peripheral circuitry coupled thereto. For example, the peripheral circuitry may include control logic. For example, one example of a NAND die may be the NAND die 130 shown in FIG. 1B.

In addition, embodiments of the present application may provide a storage system, which may include a host apparatus and a NAND storage device. For example, one example of a storage system may be the application scenario 100 of FIG. 1A. One example of a host device may be host device 110 and one example of a NAND memory device may be NAND memory device 120. For example, the storage system may be an SSD, eMMC, or other similar storage system, etc.

Embodiments of the present application also provide a machine-readable storage medium. The machine-readable storage medium may store executable code. The executable code, when executed, may cause a machine to implement the specific processes described above with respect to the control logic of the NAND die.

Embodiments of the present application also provide a machine-readable storage medium. The machine-readable storage medium may store executable code. The executable code, when executed, may cause a machine to perform the specific processes described above with respect to a host device.

It should be noted that not all steps and units in the above flows and system structure diagrams are necessary, and some steps or units may be omitted according to actual needs. The execution order of the steps is not fixed, and can be determined as required. The apparatus structures described in the above embodiments may be physical structures or logical structures, that is, some units may be implemented by the same physical entity, or some units may be implemented by a plurality of physical entities respectively, or some units may be implemented by some components in a plurality of independent devices together.

The various elements have been described in connection with various apparatus and methods. The various units may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and overall design constraints imposed on the system. As an example, each unit, any portion of each unit, or any combination of units given in this disclosure may be implemented as a microprocessor, a microcontroller, a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a state machine, gate logic, discrete hardware circuits, and other suitable processing components configured to perform the various functions described in this disclosure.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (13)

1. A method for configuring a NAND die, comprising:

receiving trimming option information from a host device, wherein the trimming option information includes a trimming command indicating a desired trimming option of a preset plurality of trimming options;

selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die;

configuring the NAND die with the target trim profile.

2. The method of claim 1, wherein the plurality of trimming options are divided into default trimming options and non-default trimming options;

selecting a target trim profile from a plurality of trim profiles based on the trim option information, comprising:

determining whether the intended trimming option is a default trimming option or a non-default trimming option;

selecting the target trim profile from the plurality of trim profiles based on the determination for the desired trim option.

3. The method of claim 2, wherein selecting the target trim profile based on the determination for the intended trim option comprises:

selecting a trim profile associated with the intended trim option from the plurality of trim profiles as the target trim profile if it is determined that the intended trim option is a default trim option.

4. The method of claim 2, wherein the intended trimming option is a non-default trimming option, the trimming option information further comprising a validation code associated with the intended trimming option;

selecting the target trim profile based on the determination for the intended trim option comprises:

in an instance in which it is determined that the intended trimming option is a non-default trimming option, obtaining a first preset security code of a plurality of preset security codes associated with the intended trimming option, wherein the plurality of preset security codes are pre-stored in the NAND die, each trimming option being associated with one preset security code;

determining whether the verification code matches the first preset security code;

and selecting the target trimming configuration file based on the matching result of the verification code and the first preset safety code.

5. The method of claim 4, wherein selecting the target trim profile based on the matching of the verification code to the first preset security code comprises:

selecting a trim profile from the plurality of trim profiles associated with the intended trim option as the target trim profile if it is determined that the verification code matches the first preset security code;

selecting a trim profile from the plurality of trim profiles associated with the default trim option as the target trim profile if it is determined that the verification code does not match the first preset security code.

6. The method of claim 4 or 5, wherein the trimming option information comprises a plurality of values that collectively constitute the verification code;

prior to determining whether the verification code matches the first preset security code, the method further comprises:

combining the plurality of values to obtain the verification code.

7. A method for configuring a NAND die, comprising:

generating trimming option information, wherein the trimming option information comprises a trimming command, and the trimming command is used for indicating a desired trimming option in a plurality of preset trimming options;

sending the trim option information to a NAND die for the NAND die to select a target trim profile for configuration from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die.

8. The method of claim 7, wherein the plurality of trimming options are divided into default trimming options and non-default trimming options;

in the event that the intended trimming option is a non-default trimming option, the trimming option information further includes a verification code associated with the intended trimming option.

9. The method of claim 8, wherein the trimming option information includes a plurality of values that collectively make up the validation code.

10. A NAND die, comprising:

an array of memory cells;

at least one peripheral circuit coupled to the memory cell array, wherein the at least one peripheral circuit is configured to:

receiving trimming option information from a host device, wherein the trimming option information includes a trimming command indicating a desired trimming option of a preset plurality of trimming options;

selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die;

configuring the NAND die with the target trim profile.

11. A NAND memory device, comprising:

at least one NAND die, wherein:

each NAND die includes an array of memory cells and at least one peripheral circuit coupled to the array of memory cells;

for a first NAND die of any of the at least one NAND die, at least one peripheral circuit in the first NAND die is configured to:

receiving trimming option information from a host device, wherein the trimming option information includes a trimming command indicating a desired trimming option of a preset plurality of trimming options;

selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the first NAND die;

configuring the first NAND die with the target trim profile.

12. A host device, comprising:

a processor;

a memory configured to store executable code that, when executed by the processor, causes the processor to:

generating trimming option information, wherein the trimming option information comprises a trimming command, and the trimming command is used for indicating a desired trimming option in a plurality of preset trimming options;

sending the trim option information to a NAND die for the NAND die to select a target trim profile for configuration from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the NAND die.

13. A storage system, comprising:

a NAND memory device comprising at least one NAND die;

a host device coupled with the at least one NAND die, wherein:

the host device is configured to:

generating trimming option information for a first NAND die of the at least one NAND die, wherein the trimming option information comprises a trimming command indicating a desired trimming option of a preset plurality of trimming options;

sending the trim option information to the first NAND die;

the first NAND die is configured to:

selecting a target trim profile from a plurality of trim profiles based on the trim option information, the plurality of trim profiles being pre-stored in the first NAND die, each trim option being associated with a trim profile, each trim profile including a set of operating parameters associated with the first NAND die;

configuring the first NAND die with the target trim profile.

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