CN114014259A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
- Publication number
- CN114014259A CN114014259A CN202111296963.7A CN202111296963A CN114014259A CN 114014259 A CN114014259 A CN 114014259A CN 202111296963 A CN202111296963 A CN 202111296963A CN 114014259 A CN114014259 A CN 114014259A
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- China
- Prior art keywords
- layer
- barrier layer
- substrate
- forming
- cavity
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 80
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000002346 layers by function Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 6
- 239000002131 composite material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/00182—Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00539—Wet etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
- H10N30/082—Shaping or machining of piezoelectric or electrostrictive bodies by etching, e.g. lithography
Abstract
The application discloses a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate with a ring-shaped groove; forming a barrier layer on the upper surface of the substrate, wherein the barrier layer fills the annular groove; forming a functional layer over the barrier layer; and etching the lower surface of the substrate to form a cavity, and stopping etching until the functional layer is reached. The upper vertex angle of the cavity obtained based on the method is close to 90 degrees, thereby being beneficial to keeping the consistency of the functional layer above the cavity. In addition, the sizes of the cavities in the middle area and the edge area of the wafer are relatively consistent, and therefore the consistency of all semiconductor structures of the wafer is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor structure.
Background
The basic structure of the piezoelectric microphone comprises a vibration composite film layer and a cavity below the vibration composite film layer. The size of the cavity affects the sensitivity and resonant frequency of the piezoelectric microphone. In the actual process, due to the difference in the process uniformity in the wafer surface, the sizes of cavities in the middle area and the edge area of the wafer are different, which seriously affects the uniformity of the whole device of the wafer, and thus, the detection cost of the device of the wafer is greatly increased in the later period.
Disclosure of Invention
In view of the problems in the related art, the present application provides a method for manufacturing a semiconductor structure, which can obtain a cavity with a uniform size, and is beneficial to improving the uniformity of the entire device of a wafer.
The technical scheme of the application is realized as follows:
according to an aspect of the present application, there is provided a method of manufacturing a semiconductor structure, comprising:
providing a substrate with a ring-shaped groove;
forming a barrier layer on the upper surface of the substrate, wherein the barrier layer fills the annular groove;
forming a functional layer over the barrier layer;
and etching the lower surface of the substrate to form a cavity, and stopping etching until the functional layer is reached.
Wherein the method of forming the barrier layer comprises: thermally oxidizing the substrate to form the barrier layer.
The substrate is made of silicon, and the barrier layer is formed by thermal oxidation of silicon oxide.
Wherein the thickness of the silicon oxide is 0.1um to 3 um.
Wherein the step of forming the barrier layer comprises: and forming a metal layer on the upper surface of the substrate, wherein the metal layer fills the annular groove.
Wherein, the material of the metal layer comprises aluminum, tungsten, copper and gold.
Wherein forming a functional layer over the barrier layer comprises:
and sequentially forming a supporting layer, a first electrode layer, a piezoelectric layer and a second electrode layer above the barrier layer.
Wherein etching the lower surface of the substrate to form a cavity comprises:
photoetching and deep silicon etching until the lower surface of the exposed barrier layer is flush with the upper surface of the substrate;
and further wet etching until the functional layer is exposed, thereby forming the cavity.
Wherein sidewalls of the barrier layer are exposed within the cavity.
The upper vertex angle of the cavity obtained after photoetching, deep silicon etching and wet etching are close to 90 degrees by utilizing different etching selection ratios of the materials of the barrier layer and the substrate, so that the functional layer above the cavity is kept consistent. In addition, the sizes of the cavities in the middle area and the edge area of the wafer are relatively consistent, and therefore the consistency of all semiconductor structures of the wafer is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1-5 illustrate schematic diagrams of intermediate stages of a method of fabricating a semiconductor structure provided in accordance with some embodiments.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived from the embodiments given herein by a person of ordinary skill in the art are intended to be within the scope of the present disclosure.
Referring to fig. 1, according to an embodiment of the present application, a method for fabricating a semiconductor structure is provided, which may form regularly shaped cavities 12, and in particular, the top angles of the cavities 12 are close to 90 degrees, thereby facilitating the functional layer above the cavities 12 to maintain uniformity. The semiconductor structure comprises a MEMS (Micro-Electro-Mechanical System) structure having a cavity 12, such as a piezoelectric MEMS microphone, a piezoelectric MEMS speaker, or other MEMS sensor or actuator. The method of fabricating the semiconductor structure will be described in detail below.
Referring to fig. 1, step S101, a substrate 10 having an annular groove 11 is provided. The substrate 10 comprises silicon or any suitable silicon-based compound or derivative (e.g., silicon wafer, SOI, polysilicon on SiO 2/Si). The annular groove 11 may be formed by an etching step.
Referring to fig. 2, step S102, a barrier layer 20 is formed on the upper surface of the substrate 10, and the barrier layer 20 fills the annular groove 11. In some embodiments, silicon oxide, which serves as the barrier layer 20, may be formed by thermally oxidizing the silicon material of the substrate 10. The thickness of the silicon oxide is 0.1um to 3 um. Preferably, the thickness of the silicon oxide is 0.5um to 2 um. In some embodiments, a metal layer may be formed on the upper surface of the substrate 10, and the metal layer fills the annular groove 11. The metal layer serves as a barrier layer 20. The metal layer is made of aluminum, tungsten, copper and gold. Methods of forming the metal layer include deposition, sputtering, or other suitable methods.
Referring to fig. 3, step S103, a functional layer is formed over the barrier layer 20. The functional layer includes a support layer 30, a first electrode layer 40, a piezoelectric layer 50, and a second electrode layer 60. The specific method for forming the functional layer is as follows:
a support layer 30 is formed over the substrate 10. The support layer 30 comprises a single or multi-layer composite film structure of silicon nitride (Si3N4), silicon oxide, single crystal silicon, polycrystalline silicon, or other suitable support material. Preferably, the thickness of the support layer 30 is 0.4um to 3 um.
A first electrode layer 40 is formed over the support layer 30.
A piezoelectric layer 50 is formed over the first electrode layer 40.
A second electrode layer 60 is formed over the piezoelectric layer 50. The piezoelectric layer 50 can convert the applied pressure into a voltage, and the first electrode layer 40 and the second electrode layer 60 can transmit the generated voltage to other integrated circuit devices. In some embodiments, the piezoelectric layer 50 comprises zinc oxide, aluminum nitride, an organic piezoelectric film, lead zirconate titanate (PZT), a perovskite-type piezoelectric film, or other suitable material. The first electrode layer 40 and the second electrode layer 60 include aluminum, gold, platinum, molybdenum, titanium, chromium, and composite films composed thereof or other suitable materials. Preferably, the thickness of the first electrode layer 40 is 0.05um to 0.5um, the thickness of the piezoelectric layer 50 is 0.4um to 3um, and the thickness of the second electrode layer 60 is 0.05um to 0.5 um.
Referring to fig. 4, in step S104, the lower surface of the substrate 10 is etched to form the cavity 12, and the etching is stopped until the functional layer is reached. Specifically, the step S104 includes:
photoetching and deep silicon etching until the lower surface of the exposed barrier layer 20 is flush with the upper surface of the substrate 10; referring to fig. 5, wet etching is further performed until the functional layer, specifically, the support layer 30 is exposed, thereby forming the cavity 12.
Notably, the sidewall of the annular barrier layer 20 is exposed within the cavity 12. When the barrier layer 20 is not used in the manufacturing method of the semiconductor structure, the upper vertex angle of the cavity 12 obtained after the deep silicon etching (i.e., the joint between the cavity 12 and the functional layer) generally forms an acute angle or an obtuse angle, which is not favorable for obtaining a functional layer with good consistency. In addition, the cavities 12 at the middle area and the edge area of the wafer are also liable to cause non-uniformity in the sizes of the cavities 12 at the middle area and the edge area due to the difference in etching rate. The present application utilizes different etching selectivity ratios of the materials of the barrier layer 20 and the substrate, and the upper vertex angle of the cavity 12 obtained after photolithography, deep silicon etching and wet etching is close to 90 degrees, thereby being beneficial to keeping consistency of the functional layer above the cavity 12. Moreover, the sizes of the cavities 12 in the middle region and the edge region of the wafer are relatively consistent, which is favorable for improving the consistency of each semiconductor structure of the wafer.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate with a ring-shaped groove;
forming a barrier layer on the upper surface of the substrate, wherein the barrier layer fills the annular groove;
forming a functional layer over the barrier layer;
and etching the lower surface of the substrate to form a cavity, and stopping etching until the functional layer is reached.
2. The method of claim 1, wherein the step of forming the barrier layer comprises: thermally oxidizing the substrate to form the barrier layer.
3. The method of claim 2, wherein the substrate comprises silicon and the thermal oxidation barrier layer comprises silicon oxide.
4. The method of claim 3, wherein the silicon oxide has a thickness of 0.1um to 3 um.
5. The method of claim 1, wherein the step of forming the barrier layer comprises: and forming a metal layer on the upper surface of the substrate, wherein the metal layer fills the annular groove.
6. The method of claim 5, wherein the metal layer comprises aluminum, tungsten, copper, or gold.
7. The method of claim 1, wherein forming a functional layer over the barrier layer comprises:
and sequentially forming a supporting layer, a first electrode layer, a piezoelectric layer and a second electrode layer above the barrier layer.
8. The method of claim 1, wherein etching the lower surface of the substrate to form the cavity comprises:
photoetching and deep silicon etching until the lower surface of the exposed barrier layer is flush with the upper surface of the substrate;
and further wet etching until the functional layer is exposed, thereby forming the cavity.
9. The method of claim 8, wherein sidewalls of the barrier layer are exposed within the cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111296963.7A CN114014259A (en) | 2021-10-29 | 2021-10-29 | Method for manufacturing semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111296963.7A CN114014259A (en) | 2021-10-29 | 2021-10-29 | Method for manufacturing semiconductor structure |
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| Publication Number | Publication Date |
|---|---|
| CN114014259A true CN114014259A (en) | 2022-02-08 |
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| CN202111296963.7A Pending CN114014259A (en) | 2021-10-29 | 2021-10-29 | Method for manufacturing semiconductor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117641215A (en) * | 2024-01-25 | 2024-03-01 | 镭友芯科技(苏州)有限公司 | Microphone sensor and preparation method thereof |
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| CN110113703A (en) * | 2019-05-18 | 2019-08-09 | 安徽奥飞声学科技有限公司 | A kind of preparation method of MEMS structure |
| CN110460942A (en) * | 2019-08-06 | 2019-11-15 | 安徽奥飞声学科技有限公司 | A kind of manufacturing method of MEMS structure |
| CN110896518A (en) * | 2019-12-17 | 2020-03-20 | 安徽奥飞声学科技有限公司 | Manufacturing method of MEMS structure |
| US20200098615A1 (en) * | 2018-09-21 | 2020-03-26 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| CN111620300A (en) * | 2020-06-04 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Device with back cavity structure and forming method thereof |
-
2021
- 2021-10-29 CN CN202111296963.7A patent/CN114014259A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080061309A1 (en) * | 2006-07-21 | 2008-03-13 | Young Sir Chung | Semiconductor device with under-filled heat extractor |
| US20200098615A1 (en) * | 2018-09-21 | 2020-03-26 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| CN110113703A (en) * | 2019-05-18 | 2019-08-09 | 安徽奥飞声学科技有限公司 | A kind of preparation method of MEMS structure |
| CN110460942A (en) * | 2019-08-06 | 2019-11-15 | 安徽奥飞声学科技有限公司 | A kind of manufacturing method of MEMS structure |
| CN110896518A (en) * | 2019-12-17 | 2020-03-20 | 安徽奥飞声学科技有限公司 | Manufacturing method of MEMS structure |
| CN111620300A (en) * | 2020-06-04 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Device with back cavity structure and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117641215A (en) * | 2024-01-25 | 2024-03-01 | 镭友芯科技(苏州)有限公司 | Microphone sensor and preparation method thereof |
| CN117641215B (en) * | 2024-01-25 | 2024-04-16 | 镭友芯科技(苏州)有限公司 | Microphone sensor and preparation method thereof |
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