CN113992317A - SPI communication method, device and storage medium - Google Patents
SPI communication method, device and storage medium Download PDFInfo
- Publication number
- CN113992317A CN113992317A CN202111143730.3A CN202111143730A CN113992317A CN 113992317 A CN113992317 A CN 113992317A CN 202111143730 A CN202111143730 A CN 202111143730A CN 113992317 A CN113992317 A CN 113992317A
- Authority
- CN
- China
- Prior art keywords
- spi
- message
- receiving end
- data
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1461—Suppression of signals in the return path, i.e. bidirectional control circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
Abstract
The application relates to an SPI communication method, an SPI communication device and a storage medium. The SPI sending terminal transmits information to the SPI receiving terminal by a first message with a preset data format in the application, and the first message contains: valid data and a valid data check code; the SPI sending end sends a first message and an end mark signal; when the SPI receiving end receives the first message, calculating a check value of effective data in the first message, comparing whether the check value of the effective data is the same as the check code of the effective data, if so, feeding a second message containing a response state back to the SPI sending end by the SPI receiving end through a MISO signal line, otherwise, feeding the second message containing a non-response state back to the SPI sending end by the SPI receiving end through the MISO signal line, and discarding the corresponding first message; and the SPI sending end controls data transmission between the SPI sending end and the SPI receiving end according to the content of the second message. The application realizes response, effective data inspection and SPI data transmission process control in the SPI communication process under the condition of not increasing GPIO.
Description
Technical Field
The present application relates to the field of SPI communications, and in particular, to an SPI communication method, apparatus, and storage medium.
Background
The SPI (serial peripheral interface) is a synchronous serial communication protocol, and in point-to-point communication, the SPI interface does not need to perform addressing operation, and is full-duplex communication, which is simple and efficient. The standard SPI only uses 4 pins for control and data transmission, so that the pin number of a chip is saved, and the space of the SPI on the layout of a PCB is saved.
Due to this simple and easy-to-use feature, SPI technology is now increasingly integrated on a chip. The SPI interface is mainly used between an EEPROM, a Flash, a Real Time Clock (RTC), a digital-to-analog converter (ADC), a Digital Signal Processor (DSP), and a digital signal decoder. The advantages of SPI communication are few signal lines, simple protocol, and high relative data rate, but there are also deficiencies in SPI standard protocol, including: lack of a reply mechanism to confirm whether data is received; lack of checks, lack of mechanisms to control transmission errors; there is no flow control specified. In the prior art, in order to solve the problems, many designs implement an acknowledgement mechanism by adding an ACK pin and implement flow control by adding an interrupt pin. For example, in the patent with application number cn202110302164.x, three GPIO lines for synchronizing data are added, where the three GPIO lines are an IND line, an RDY line, and an ACK line, respectively, and after the host receives a feedback signal, the host starts to transmit data, and after the slave completely receives the data transmitted from the host, the slave transmits a response signal to the host through the ACK line. The increase of the pins of the SPI control chip inevitably increases the complexity of chip hardware design and implementation, and when the SPI chip is distributed on a PCB, more pins occupy more PCB space.
Disclosure of Invention
In order to solve the technical problems described above or at least partially solve the technical problems, the present application provides an SPI communication method, apparatus and storage medium.
In a first aspect, the present application provides an SPI communication method, comprising:
the SPI sending end transmits information to the SPI receiving end through a first message in a preset data format, wherein the first message comprises: valid data and a valid data check code;
the SPI sending end sends a first message and an end mark signal;
when the SPI receiving end receives the first message, calculating a check value of effective data in the first message, comparing whether the check value of the effective data is the same as the check code of the effective data, if the check value of the effective data is the same as the check code of the effective data, feeding a second message containing a response state back to the SPI sending end through a MISO signal line by the SPI receiving end, otherwise feeding the second message containing a non-response state back to the SPI sending end through the MISO signal line by the SPI receiving end, and discarding the corresponding first message;
and the SPI sending end controls data transmission between the SPI sending end and the SPI receiving end according to the content of the second message.
Further, the content of the first message includes: the effective data length, the effective data and the effective data check code; in the preset data format of the first message, the effective data length and the effective data check code are configured with fixed digits, and the effective data length, the effective data and the effective data check code are arranged in sequence.
Furthermore, the SPI receiving end obtains valid data from the subsequent data of the first message according to the length of the valid data obtained first, and calculates the check value of the obtained valid data according to a preset check value calculation method.
Furthermore, the second packet includes a first data bit and a second data bit, and in the data format of the second packet, the first data bit and the second data bit are located at fixed positions in the second packet with fixed numbers, where the number of the first data bit represents an acknowledgement state or a non-acknowledgement state, and the number of the second data bit represents a space where the SPI receiving end FIFO buffer continues to receive the packet or the SPI receiving end FIFO buffer does not have a space where the SPI receiving end FIFO buffer receives the packet.
Further, the end-marker signal has a fixed content and form.
Furthermore, the controlling, by the SPI sending end, data transmission between the SPI sending end and the SPI receiving end according to the content of the second message includes:
when the SPI receiving end is in a response state and FIFO cache of the SPI receiving end can continuously receive the first message, the SPI sending end sends the next first message in the service;
when the SPI receiving end is in a response state and the FIFO cache of the SPI receiving end cannot continuously receive the first message, the SPI sending end monitors the FIFO cache state of the SPI receiving end, and when the FIFO cache of the SPI receiving end can receive the first message, the SPI sending end sends the next first message in the service;
when the SPI receiving end is in a non-response state and FIFO cache of the SPI receiving end can continue to receive the first message, the SPI sending end retransmits the first message corresponding to the second message containing the non-response state;
when the SPI receiving end is in a non-response state and the FIFO cache of the SPI receiving end cannot continuously receive the first message, the SPI sending end monitors the FIFO cache state of the SPI receiving end, and when the FIFO cache of the SPI receiving end can receive the first message, the first message corresponding to the second message containing the non-response state is sent again.
Further, a second message is obtained, and the first data bit and the number on the second data bit are obtained from the second message; judging whether the SPI receiving end is in a response state or not according to the number on the first data bit in the second message; and judging whether the FIFO buffer of the SPI receiving end can continuously receive the first message at present according to the number on the second data bit in the second message.
Furthermore, the SPI receiving end monitors the FIFO cache state of the SPI receiving end in real time;
the SPI receiving end stores the FIFO cache state of the SPI receiving end in a set storage position;
and when the SPI sending end needs to acquire the buffer state of the FIFO buffer of the SPI receiving end, acquiring the state of the FIFO buffer of the SPI receiving end from the set storage position.
In a second aspect, the present application provides a device for implementing an SPI communication method, including an SPI sending end and an SPI receiving end, wherein the SPI sending end includes:
the first message creating module is used for creating a first message according to a preset data format; the SPI sending end sends the first message to the SPI receiving end by using an MOSI signal line;
the data transmission control module is used for controlling data transmission between the SPI sending end and the SPI receiving end according to the content of the second message;
the SPI receiving terminal includes:
the verification module is used for carrying out integrity verification on the effective data in the first message received by the SPI receiving end;
the buffer monitoring module is used for monitoring the FIFO buffer state of the SPI receiving end in real time;
and the second message creating module is used for generating a second message according to a preset data format by using the result of the checking module and the FIFO cache state of the SPI receiving end monitored by the cache monitoring module.
In a third aspect, the present application provides a storage medium for implementing an SPI communication method, where the storage medium for implementing the SPI communication method stores at least one instruction, and reads and executes the instruction to implement the SPI communication method.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the SPI receiving terminal calculates the check value of the effective data of the first message, and the integrity of the effective data received by the SPI receiving terminal is judged by comparing the check value of the effective data with the effective data check code contained in the first message. The error checking of the effective data in the first message in the SPI communication process is realized.
And the SPI receiving end forms a second message according to the checking condition of the effective data and the state that the FIFO cache of the SPI receiving end can continuously receive the first message, and sends the second message to the SPI sending end by using the MISO signal wire. And response condition communication between the SPI sending end and the SPI receiving end is realized under the condition that an ACK (acknowledgement) line is not newly added. The structure of the device for realizing the SPI communication method and the layout on the PCB are simpler.
This application utilizes effective data length in the first message that SPI sending terminal sent, end mark signal, the second message that immediately follows first message to realize the control to data transmission between SPI sending terminal and the SPI receiving terminal. And the orderly and stable transmission of data between the SPI sending end and the SPI receiving end is ensured.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a flowchart of an SPI communication method provided in an embodiment of the present application;
fig. 2 is a schematic diagram of a first packet provided in the embodiment of the present application;
fig. 3 is a schematic diagram of a second packet provided in the embodiment of the present application;
fig. 4 is a flowchart of generating a second message according to the embodiment of the present application;
fig. 5 is a flowchart illustrating that the SPI sending end controls data transmission between the SPI sending end and the SPI receiving end according to the content of the second message according to the embodiment of the present application;
fig. 6 and fig. 7 are schematic diagrams of an apparatus for implementing an SPI communication method according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Example 1
Referring to fig. 1, an embodiment of the present application provides an SPI communication method including:
s100, the SPI sending end transmits information to the SPI receiving end through a first message in a preset data format, and the first message comprises: valid data and a valid data check code; in a specific implementation process, the SPI sending end determines whether data to be sent to the target SPI receiving end exists in the sending queue, and if so, encapsulates the data into a corresponding first message according to a preset data format of the first message. Referring to fig. 2, the content of the first message includes but is not limited to: the effective data length, the effective data and the effective data check code are configured with fixed digits in a preset data format of the first message, and the effective data length, the effective data and the effective data check code are arranged in sequence. One possible way is to set a valid data length of 8 bits and a valid data check code of 8 bits. One possible such valid data check code is a parity check code.
And S200, the SPI sending end immediately sends an end mark signal after sending the first message. Specifically, the end-marker signal has an 8-bit fixed form and content. One possible way is to merge the end-marker signal into the first message and to set it at the end of the first message. And the SPI receiving end determines that the SPI sending end finishes sending the first message according to the end mark signal.
S300, when the SPI receiving end receives the first message, the verification value of the effective data in the first message is calculated, whether the verification value of the effective data is the same as the effective data verification code in the first message or not is compared, if the verification value of the effective data is the same as the effective data verification code in the first message, S400 is executed, and if the verification value of the effective data is not the same as the effective data verification code in the first message, S500 is executed. Specifically, the SPI receiving end acquires the valid data from the subsequent data of the first message according to the length of the valid data acquired first, and calculates the check value of the acquired valid data according to a preset check value calculation method. And when the effective data received by the SPI receiving end is consistent with the effective data sent by the SPI sending end, the effective data check code is equal to the check value of the effective data obtained by calculation. And once the check value of the obtained effective data is calculated to be different from the check code of the effective data in the first message, the integrity of the effective data is damaged in the transmission process.
Referring to fig. 3, the SPI receiving end generates a second packet according to the comparison result, where the second packet includes a first data bit and a second data bit, and in the data format of the second packet, the first data bit and the second data bit are located at fixed positions in the second packet with fixed number of bits, for example, the second packet includes 8 bits in total from bit0 to bit7, the first data bit is located at the fourth bit (bit3), and the second data bit is located at the eighth bit (bit 7). The number of the first data bit represents the response state or the non-response state, and the number of the second data bit represents the space for continuously receiving the message in the FIFO cache of the SPI receiving end or the space for receiving the message in the FIFO cache of the SPI receiving end. Referring to fig. 4, the process of generating the second message includes:
s301, a comparison result of the check value of the effective data and the check code of the effective data is obtained.
S302, assigning a value to the first data bit of the second message according to the comparison result. Specifically, when the check value of the valid data is equal to the valid data check code, the first data bit of the second packet is assigned to 1, otherwise, the first data bit of the second packet is assigned to 0. The first data bit is 1, which indicates that the SPI receiving terminal is in an acknowledge state, and the first data bit is 0, which indicates that the SPI receiving terminal is in a non-acknowledge state.
And S303, the SPI receiving end monitors the FIFO cache state of the current SPI receiving end.
And S304, assigning a second data bit of the second message according to the FIFO buffer status of the SPI receiving end. Specifically, when the FIFO buffer of the SPI receiving end can continue to receive the first packet, the second data bit of the second packet is assigned to 1, otherwise the second data bit of the second packet is assigned to 0.
And S400, the SPI receiving end feeds back the second message containing the response state to the SPI sending end through the MISO signal wire.
And S500, the SPI receiving end feeds back the second message containing the non-response state to the SPI sending end through the MISO signal wire, and discards the corresponding first message.
And S600, the SPI sending end controls data transmission between the SPI sending end and the SPI receiving end according to the content of the second message.
In a specific implementation process, referring to fig. 5, the controlling, by the SPI sending end, data transmission between the SPI sending end and the SPI receiving end according to the content of the second message includes:
s601, the SPI sending end obtains the second message and analyzes the second message to obtain the state of the SPI receiving end. Specifically, the digits on the first data bit and the second data bit are obtained from the second message.
S602, judging whether the SPI receiving end is in a response state according to the number on the first data bit in the second message.
S603, determining whether the FIFO buffer of the SPI receiving end can continue to receive the first packet according to the number of the second data bit in the second packet.
When the SPI receiving end is in the reply state and the SPI receiving end FIFO buffer can continue to receive the first message, the SPI sending end sends the next first message in the service S604.
When the SPI receiving end is in the response state and the SPI receiving end FIFO buffer cannot continue to receive the first message, S605 the SPI transmitting end monitors the SPI receiving end FIFO buffer state, and when the SPI receiving end FIFO buffer can receive the first message, the SPI transmitting end transmits the next first message in the service.
When the SPI receiving end is in the non-responded state and the SPI receiving end FIFO buffer can continue to receive the first message, S606, the SPI sending end retransmits the first message corresponding to the second message containing the non-responded state.
When the SPI receiving end is in the non-responded state and the SPI receiving end FIFO buffer cannot continue to receive the first message, S607, the SPI transmitting end monitors the SPI receiving end FIFO buffer state, and retransmits the first message including the second message in the non-responded state when the SPI receiving end FIFO buffer can receive the first message.
Specifically, a feasible way for the SPI sending end to monitor the FIFO buffer status of the SPI receiving end is as follows:
and the SPI receiving end monitors the FIFO cache state of the SPI receiving end in real time.
The SPI receiving end stores the FIFO cache state of the SPI receiving end in a set storage position; specifically, the set storage location is a status register in the SPI receiving end.
And when the SPI sending end needs to acquire the buffer state of the FIFO buffer of the SPI receiving end, acquiring the state of the FIFO buffer of the SPI receiving end from the set storage position.
Example 2
Referring to fig. 6 and fig. 7 in combination, an apparatus for implementing an SPI communication method according to an embodiment of the present application includes an SPI sending end and an SPI receiving end.
The SPI transmitting end is connected with the SPI receiving end through an MOSI signal line, a MISO signal line, an SCLK clock line and an SS chip selection line. The MOSI signal line is connected with a Tx channel of the SPI sending end and an Rx channel of the SPI receiving end and transmits data sent to the SPI receiving end by the SPI sending end; the MISO signal line is connected with an Rx channel of the SPI sending end and a Tx channel of the SPI receiving end, and data sent to the SPI sending end by the SPI receiving end is transmitted. The SCLK clock line is used for transmitting a clock signal sent by the SPI sending end to the SPI receiving end, and controls data transmission between the SPI sending end and the SPI receiving end through the clock signal. And the SS chip selection line is used for the SPI sending end to send a chip selection signal, and the SPI receiving end communicated with the SPI sending end is selected through the chip selection signal.
Configuration SPI sending end FIFO buffer memory in the SPI sending end, the effect of SPI sending end FIFO buffer memory includes: a sending queue for storing data to be transmitted by an SPI sending end is formed; configuration SPI receiving terminal FIFO buffering memory in the SPI receiving terminal, the effect of SPI receiving terminal FIFO buffering memory includes: caching the received data; the SPI sending end FIFO cache and the SPI receiving end FIFO cache are connected by a shift register, and the shift register is used for moving data into or out of the SPI sending end FIFO cache or the SPI receiving end FIFO cache according to the set data bit width.
Set up the sender controller in the SPI sending terminal, set up the receiver controller in the SPI receiving terminal, sender controller and receiver controller effect include: the transmission mode of the SPI bus is configured, wherein the transmission modes are divided into four types, and are defined by a clock polarity and a clock phase, the clock polarity defines a level (including a high level and a low level) when the SCLK clock signal is idle, and the clock phase defines whether to sample at a rising edge or a falling edge of the SCLK clock.
Further, the SPI sending end further includes:
the first message creating module is used for creating a first message according to a preset data format;
and the data transmission control module is used for controlling data transmission between the SPI sending end and the SPI receiving end according to the content of the second message.
The SPI receiving terminal still includes:
and the checking module is used for calculating the checking value of the effective data in the first message, comparing whether the checking value of the effective data is the same as the checking code of the effective data in the first message or not, if the checking value of the effective data is the same as the checking code of the effective data in the first message, the integrity of the effective data in the first message is considered, and if the checking value of the effective data is not the same as the checking code of the effective data in the first message, the integrity of the effective data in the first message is damaged.
The buffer monitoring module is used for monitoring the FIFO buffer state of the SPI receiving end in real time; specifically, the buffer monitoring module obtains the state of the SPI receiving end FIFO buffer and stores the state of the SPI receiving end FIFO buffer in a designated state register.
And the second message creating module is used for generating a second message according to a preset data format by using the result of the checking module and the FIFO cache state of the SPI receiving end monitored by the cache monitoring module.
Example 3
The application provides a storage medium for realizing an SPI communication method, wherein the storage medium for realizing the SPI communication method stores at least one instruction, and the instruction is read and executed to realize the SPI communication method.
The SPI receiving terminal calculates the check value of the effective data of the first message, and the integrity of the effective data received by the SPI receiving terminal is judged by comparing the check value of the effective data with the effective data check code contained in the first message. The error checking of the effective data in the first message in the SPI communication process is realized.
And the SPI receiving end forms a second message according to the checking condition of the effective data and the state that the FIFO cache of the SPI receiving end can continuously receive the first message, and sends the second message to the SPI sending end by using the MISO signal wire. And response condition communication between the SPI sending end and the SPI receiving end is realized under the condition that an ACK (acknowledgement) line is not newly added. The structure of the device for realizing the SPI communication method and the layout on the PCB are simpler.
This application utilizes effective data length in the first message that SPI sending terminal sent, end mark signal, the second message that immediately follows first message to realize the control to data transmission between SPI sending terminal and the SPI receiving terminal. And the orderly and stable transmission of data between the SPI sending end and the SPI receiving end is ensured.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An SPI communication method, comprising:
the SPI sending end transmits information to the SPI receiving end through a first message in a preset data format, wherein the first message comprises: valid data and a valid data check code;
the SPI sending end sends a first message and an end mark signal;
when the SPI receiving end receives the first message, calculating a check value of effective data in the first message, comparing whether the check value of the effective data is the same as the check code of the effective data, if the check value of the effective data is the same as the check code of the effective data, feeding a second message containing a response state back to the SPI sending end through a MISO signal line by the SPI receiving end, otherwise feeding the second message containing a non-response state back to the SPI sending end through the MISO signal line by the SPI receiving end, and discarding the corresponding first message;
and the SPI sending end controls data transmission between the SPI sending end and the SPI receiving end according to the content of the second message.
2. The SPI communication method according to claim 1, wherein the contents of the first packet comprise: the effective data length, the effective data and the effective data check code; in the preset data format of the first message, the effective data length and the effective data check code are configured with fixed digits, and the effective data length, the effective data and the effective data check code are arranged in sequence.
3. The SPI communication method according to claim 2, wherein the SPI receiving end obtains the valid data from the subsequent data of the first message according to the length of the valid data obtained first, and the SPI receiving end calculates the check value of the obtained valid data according to a preset check value calculation method.
4. The SPI communication method according to claim 1, wherein the second packet comprises a first data bit and a second data bit, and wherein in the data format of the second packet, the first data bit and the second data bit are located at fixed positions in the second packet with fixed numbers, wherein the number of the first data bit indicates an acknowledge state or a non-acknowledge state, and the number of the second data bit indicates that the SPI receiving FIFO buffer has a space for continuing to receive the packet or the SPI receiving FIFO buffer does not have a space for receiving the packet.
5. The SPI communication method according to claim 1, wherein said end-marker signal has a fixed content and form.
6. The SPI communication method according to claim 1, wherein the controlling, by the SPI sender, data transmission between the SPI sender and the SPI receiver according to the second message content comprises:
when the SPI receiving end is in a response state and FIFO cache of the SPI receiving end can continuously receive the first message, the SPI sending end sends the next first message in the service;
when the SPI receiving end is in a response state and the FIFO cache of the SPI receiving end cannot continuously receive the first message, the SPI sending end monitors the FIFO cache state of the SPI receiving end, and when the FIFO cache of the SPI receiving end can receive the first message, the SPI sending end sends the next first message in the service;
when the SPI receiving end is in a non-response state and FIFO cache of the SPI receiving end can continue to receive the first message, the SPI sending end retransmits the first message corresponding to the second message containing the non-response state;
when the SPI receiving end is in a non-response state and the FIFO cache of the SPI receiving end cannot continuously receive the first message, the SPI sending end monitors the FIFO cache state of the SPI receiving end, and when the FIFO cache of the SPI receiving end can receive the first message, the first message corresponding to the second message containing the non-response state is sent again.
7. The SPI communication method according to claim 6, wherein a second message is obtained, and the digits on the first data bit and the second data bit are obtained from the second message; judging whether the SPI receiving end is in a response state or not according to the number on the first data bit in the second message; and judging whether the FIFO buffer of the SPI receiving end can continuously receive the first message at present according to the number on the second data bit in the second message.
8. The SPI communication method according to claim 6, wherein the SPI receiving end monitors the state of the FIFO buffer of the SPI receiving end in real time;
the SPI receiving end stores the FIFO cache state of the SPI receiving end in a set storage position;
and when the SPI sending end needs to acquire the buffer state of the FIFO buffer of the SPI receiving end, acquiring the state of the FIFO buffer of the SPI receiving end from the set storage position.
9. The utility model provides a realize device of SPI communication method, includes SPI sending terminal and SPI receiving terminal, its characterized in that, the SPI sending terminal includes:
the first message creating module is used for creating a first message according to a preset data format;
the data transmission control module is used for controlling data transmission between the SPI sending end and the SPI receiving end according to the content of the second message;
the SPI receiving terminal includes:
the checking module is used for carrying out integrity checking on the effective data in the first message;
the buffer monitoring module is used for monitoring the FIFO buffer state of the SPI receiving end in real time;
and the second message creating module is used for generating a second message according to a preset data format by using the result of the checking module and the FIFO cache state of the SPI receiving end monitored by the cache monitoring module.
10. A storage medium for implementing an SPI communication method, wherein the storage medium for implementing an SPI communication method stores at least one instruction, and reads and executes the instruction to implement the SPI communication method according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111143730.3A CN113992317A (en) | 2021-09-28 | 2021-09-28 | SPI communication method, device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111143730.3A CN113992317A (en) | 2021-09-28 | 2021-09-28 | SPI communication method, device and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113992317A true CN113992317A (en) | 2022-01-28 |
Family
ID=79737053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111143730.3A Pending CN113992317A (en) | 2021-09-28 | 2021-09-28 | SPI communication method, device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113992317A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114466045A (en) * | 2022-02-10 | 2022-05-10 | 武汉中旗生物医疗电子有限公司 | SPI communication method, monitor and medium |
| CN115118409A (en) * | 2022-06-24 | 2022-09-27 | 重庆长安新能源汽车科技有限公司 | SPI communication method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112973A (en) * | 1992-09-25 | 1994-04-22 | Matsushita Electric Works Ltd | Packet re-transmission system |
| CN103905300A (en) * | 2012-12-25 | 2014-07-02 | 华为技术有限公司 | Data message sending method, device and system |
| CN108446243A (en) * | 2018-03-20 | 2018-08-24 | 上海奉天电子股份有限公司 | A kind of two-way communication and system based on Serial Peripheral Interface (SPI) |
| CN110334046A (en) * | 2019-07-11 | 2019-10-15 | 南方电网科学研究院有限责任公司 | A kind of communication means, the apparatus and system of SPI full duplex |
| CN112230880A (en) * | 2020-10-23 | 2021-01-15 | 浪潮(北京)电子信息产业有限公司 | Data transmission control method and device, FPGA (field programmable Gate array) and medium |
-
2021
- 2021-09-28 CN CN202111143730.3A patent/CN113992317A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112973A (en) * | 1992-09-25 | 1994-04-22 | Matsushita Electric Works Ltd | Packet re-transmission system |
| CN103905300A (en) * | 2012-12-25 | 2014-07-02 | 华为技术有限公司 | Data message sending method, device and system |
| CN108446243A (en) * | 2018-03-20 | 2018-08-24 | 上海奉天电子股份有限公司 | A kind of two-way communication and system based on Serial Peripheral Interface (SPI) |
| CN110334046A (en) * | 2019-07-11 | 2019-10-15 | 南方电网科学研究院有限责任公司 | A kind of communication means, the apparatus and system of SPI full duplex |
| CN112230880A (en) * | 2020-10-23 | 2021-01-15 | 浪潮(北京)电子信息产业有限公司 | Data transmission control method and device, FPGA (field programmable Gate array) and medium |
Non-Patent Citations (1)
| Title |
|---|
| 保金桢; 龚正虎; 赵宝康; 吴纯青; 刘波: "宇航级高可靠SPI总线协议设计与实现", 《第十八届全国青年通信学术年会论文集（上册）》, pages 1 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114466045A (en) * | 2022-02-10 | 2022-05-10 | 武汉中旗生物医疗电子有限公司 | SPI communication method, monitor and medium |
| CN115118409A (en) * | 2022-06-24 | 2022-09-27 | 重庆长安新能源汽车科技有限公司 | SPI communication method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9875206B2 (en) | Methods and devices for extending USB 3.0-compliant communication | |
| US4641263A (en) | Controller system or emulating local parallel minicomputer/printer interface and transferring serial data to remote line printer | |
| CN113992317A (en) | SPI communication method, device and storage medium | |
| EP1198105A2 (en) | High speed transmission line interface | |
| US7484031B2 (en) | Bus connection device | |
| EP0496177A1 (en) | Method of transmitting data by buffer chaining between a host computer and a communication controller | |
| US9075926B2 (en) | Distributed interconnect bus apparatus | |
| WO2011046056A1 (en) | Transmission control method for packet communication and packet communication system | |
| US20040198223A1 (en) | Flow control in a bluetooth wireless communication system | |
| US6584103B1 (en) | Packet communication apparatus provided with manager means for managing packet labels | |
| US8144733B2 (en) | Partitioned medium access control implementation | |
| CN113792003A (en) | Single bus communication unit, system and method | |
| US5388109A (en) | Data communications device with resident link adapter | |
| US6934790B2 (en) | Data transmitting and receiving system with speedy retransmission of missing data and data receiving device | |
| CN114253886A (en) | Techniques for resolving conflicts in USB traffic in an extended environment | |
| KR970007257B1 (en) | Packet transmission system and method utilizing both data bus and dedicated control lines | |
| JP3148733B2 (en) | Signal processing device and signal processing system | |
| CN113196255B (en) | Data transmission method and transmission device based on internal integrated circuit protocol | |
| WO2024009733A1 (en) | Semiconductor device and communication system | |
| JP2008017175A (en) | Data processing device | |
| CN108701103B (en) | Direct memory access control device for a computing unit with a working memory | |
| JP4064626B2 (en) | Communication protocol | |
| KR100567033B1 (en) | Method for operating synchronous serial communication in which master and slave are fixed | |
| JP2000284872A (en) | Usb transmitter | |
| JP2011113351A (en) | Communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |