CN113985252B - Lamp panel jig regional testing method - Google Patents
Lamp panel jig regional testing method Download PDFInfo
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- CN113985252B CN113985252B CN202111263185.1A CN202111263185A CN113985252B CN 113985252 B CN113985252 B CN 113985252B CN 202111263185 A CN202111263185 A CN 202111263185A CN 113985252 B CN113985252 B CN 113985252B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
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Abstract
The invention discloses a lamp panel jig regional testing method, which comprises the following steps: step 1, based on the two-side measuring point patterns of the lamp panel to be tested, the C side is measured according to the following steps of 1: 1, manufacturing a jig, searching rules for the S surface according to network sequencing, taking the part with the same rules as one partition, and splitting the S surface into N partitions; and 2, respectively manufacturing test data corresponding to the N partitions, manufacturing a jig based on the test data, and respectively testing different partitions by using the jig. The lamp panel jig regional testing method can realize the testing of high-density lamp panel products, reduce the manufacturing cost of the jig and improve the testing efficiency.
Description
Technical Field
The invention relates to a lamp panel jig regional testing method.
Background
The traditional test method has three test methods:
the method comprises the following steps: the printed wiring board uses set as the unit after the shaping, according to circuit board set size 1 during tool preparation: 1, manufacturing, namely, performing needle-up test on all windowed PADs on a board surface;
the second method comprises the following steps: the printed circuit board uses set as the unit after the shaping, according to circuit board set size 1 during tool preparation: 1, manufacturing, namely, carrying out network differentiation on all windowed PADs on the board surface, manufacturing two or more sets of jigs, and respectively testing;
the third method comprises the following steps: the printed circuit board takes set as a unit after being formed, the set is composed of a plurality of pcs, the fixture is manufactured according to one or a plurality of pcs, and one set is tested for multiple times according to the combination of the pcs to complete the whole set test.
The three jig manufacturing methods can meet the requirements of most of through holes, HDI and other PCB products, but cannot meet the test requirements of high-density lamp panel products, and the analysis is as follows:
(1) the lamp panel product has the characteristics of large single PCS area, large number of PADs on the lamp bead surface and high density, and when the size of the lamp panel product is large, the lamp panel product possibly exceeds the equipment test area, so that the test cannot be performed; if the size of the lamp panel product is smaller, the density of PAD on the relative lamp bead surface is higher, so that the slope of the jig is very large and exceeds the processing capacity of equipment;
(2) although the flying probe can be used for testing, the yield is too low to meet the requirement of mass production, and the testing cost is increased; large table-board equipment or high-end equipment matching product production can be selected and purchased, but the equipment cost is high.
Disclosure of Invention
The invention aims to provide a lamp panel jig regional testing method, which can realize the test of high-density lamp panel products, reduce the manufacturing cost of the jig and improve the testing efficiency.
In order to achieve the above purpose, the solution of the invention is:
a lamp panel jig regional testing method comprises the following steps:
and 2, respectively manufacturing test data corresponding to the N subareas, summarizing and analyzing all the test data, manufacturing jig data according to an analysis result, manufacturing a test jig, and respectively testing different subareas after the jig is finished.
Before partitioning, whether blind buried holes in the S surface of the lamp panel are conducted or not and whether each test point of the S surface is communicated with the C surface or not are confirmed through network relation analysis processing software, and insulation test of the C surface is carried out.
When the insulation test of the C surface is carried out, a double-test-point mode is adopted.
In the step 1, when the region is split for the S-plane, the splitting scheme is determined according to the number of points and the density of the test points.
In the step 2, during testing, the upper die is made of the S surface, the lower die is made of the C surface, and the upper die is tested to be conducted by integrally moving the lower jig.
For a lamp panel without an independent point, a test scheme of an open circuit test is adopted; for a lamp panel without a single-side measuring point network, a one-to-many test scheme is adopted; for the network of the lamp panel lamp bead surface, for each test point 1, …, a test scheme of a lower die network head Ci-an upper die lamp bead surface network point Sj is adopted, wherein i, j is 1, …, a and i are not equal to j.
In the step 2, the jig is controlled to be adjusted to different positions according to the test data, so that different partitions of the lamp panel are tested independently, all the partitions of the lamp panel are tested to be PASS PASS boards, and if 1NG exists, corresponding defect paper is pasted and sent to a point finding and confirming.
After the scheme is adopted, the invention has the following beneficial effects:
(1) the invention can solve the problem that the area of the test equipment and the effective test points can not meet the test requirement because the test area of the equipment is exceeded when the product size is large and the number of PAD points is large;
(2) the invention can solve the problems that if the product size is smaller, the PAD concentration on the lamp bead surface is high, so that the slope of the jig is large, the equipment processing capability is exceeded, and the test jig cannot be manufactured in the prior art;
(3) the manufacturing cost of the jig is reduced, and the cost is reduced by 50-70% because the jig with the 14W point originally only needs to be manufactured into the jig with the 4.2W point after being optimized;
(4) high-cost purchase of high-end equipment is not required;
(5) the production of flying needles in small batches is promoted to the production of jigs in large batches, the productivity is improved, and the product delivery period is shortened.
Drawings
FIG. 1 is a schematic view of a measuring point on the C-plane of a lamp panel;
FIG. 2 is a schematic diagram of S-surface measuring points of the lamp panel;
FIG. 3 is a schematic diagram of S-plane splitting and typesetting of the lamp panel;
FIG. 4 is a schematic representation of the communication between the S-plane side and the C-plane;
FIG. 5 is a schematic diagram of a pass-through network test;
FIG. 6 is a schematic diagram of the use of dual test points;
FIG. 7 is a schematic diagram of regular points of PAD on the S surface;
FIG. 8 is a schematic illustration of the results of the splitting;
FIG. 9 is a schematic illustration of the detachment;
FIG. 10 is a schematic view of the upper die conduction test;
FIG. 11 is a schematic illustration of an upper die detachment test;
FIG. 12 is a schematic view of a lower die dual site insulation assurance;
FIG. 13 is a schematic diagram of importing data into the network relation analysis processing software;
FIG. 14 is a schematic view of setting parameters;
FIG. 15 is a schematic view of the setting machine;
FIG. 16 is a diagram of a device test display;
FIG. 17 is a schematic view of the connection of all measuring points on the bead surface to the other surface;
FIG. 18 is a schematic of an open circuit test;
FIG. 19 is a schematic diagram of a conduction test performed at each point in a multi-point network;
FIG. 20 is a schematic diagram of the test;
FIG. 21 is a flow chart of the present invention.
Detailed Description
The technical scheme and the beneficial effects of the invention are explained in detail in the following with the accompanying drawings.
As shown in fig. 21, the present invention provides a lamp panel jig regional test method, which mainly comprises the following steps: based on the two-side measuring point patterns of the lamp panel to be tested (such as shown in fig. 1 and fig. 2), the C side is divided into 1: 1, manufacturing a jig, searching a corresponding rule for an S surface according to network sequencing, and splitting and composing, wherein as shown in fig. 3, a lamp bead PAD of the S surface is split into 3 regions; and finally, respectively manufacturing test data of 3 subareas according to the split network, summarizing and analyzing the test data of the 3 subareas, manufacturing jig data according to an analysis result, manufacturing a test jig, and respectively testing different subareas after the jig is finished. In this embodiment, the test of whole product can be accomplished to a slice lamp plate test cubic, can improve efficiency of software testing greatly.
The test procedure of the embodiment of the present invention will be described in detail below.
1. Lamp panel specification
Size: 342mm gamma 152
And (4) counting the test points: 9800 points for C surface, 129600 points for S surface, 139400 points for total points
The method is characterized in that:
1.1, the number of single-side points of the data is more than that of a machine station and a testable point;
1.2, the length of the plate is longer;
remarking: evaluating the requirement of using a 6.5 times density tester to test in different areas according to the point number and the density condition;
2. analyzing data network characteristics
2.1, designing S-surface blind buried holes, wherein all the S-surface blind buried holes need to be tested for conduction;
2.2, each test point of the S surface is communicated with the C surface, as shown in figure 4;
2.3, the C surface can complete the insulation test without a test blind spot;
2.3.1, testing, splitting, conducting and insulating;
A. conducting network test, as shown in fig. 5;
B. the insulation network can be completed by C-plane test;
2.3.2, ensuring the insulation of the C surface;
A. in order to ensure that no blind spot exists in the insulation test, the network with the relatively independent C surface (after the point of the S surface is removed) adopts double test points to prevent the insulation leakage test caused by poor contact of a test needle, and can be matched with the method shown in the figure 6;
2.4, S-plane dot matrix has sequence regular arrangement
2.4.1, S surface PAD regular points, as shown in FIG. 7;
2.4.2, split mode, as in fig. 8;
3. test point splitting scheme
3.1, splitting test points according to a rule: analyzing the distribution rule of the test points by data processing software KM-SEE.EXE, and determining a test scheme according to the point number and the density;
3.2, 6.5 times the density can be split for 3 times of tests, the number of points is about 42200 points, and the slope is within 50mil, as shown in figure 9;
4. clamp manufacturing scheme
4.1, an upper die is made on the S surface, a lower die is made on the C surface, and a jig is used for testing the conduction of the upper die by integrally moving the lower jig, and the scheme can be matched with that shown in the figure 10;
4.2, performing upper die disassembly test, as shown in FIG. 11;
4.3, ensuring the insulation of double measuring points of the lower die, as shown in figure 12;
5. test machine operation
5.1, testing the import of multiple sets of data, as shown in FIG. 13;
5.2, setting a plurality of sets of data import as shown in FIG. 14;
5.3, mechanical position setting, as shown in FIG. 15;
5.4, starting the test after the equipment parameter setting is finished, and displaying the equipment test, as shown in FIG. 16;
6. the jig adjusts different positions according to the test data, and carries out independent test on different partitions of 1 lamp panel, if all partitions of 1 lamp panel are tested to be qualified, the PASS panel is used, and if 1NG exists, corresponding defect paper is pasted, and point finding confirmation is sent.
The principle of the test method of the present invention is illustrated below:
1. test principle of lamp panel substrate universal test machine
1.1, test rule requirements
A. All test point networks on the bead surface are required to be connected with the other surface, as shown in fig. 17;
B. requiring no isolated network for the LED surface
a. Without independent points
b. Network without single-side measuring point
C. Every point on the lamp bead surface is tested
(remark: the above points are analyzed automatically and intelligently using professional software, in this embodiment, KM _ FIXTURE.EXE (network relation analysis processing software) is used to perform automatic analysis and point selection, and KM _ GRID.EXE (jig data analysis processing software) is used to perform automatic analysis and manufacture of jig data)
2. Principle of testing according to the above rules
A. Open circuit test, fig. 18;
B. the principle of the open circuit test for the multi-point network is known as one-to-many test, that is, taking a certain point as a head, conducting test is carried out on the rest of each point, as shown in fig. 19;
C. the conduction test mode is as follows:
1，2 1，3 1，4 1，5 1，6 1，7 1，8
D. in the same principle, for a network of lamp bead surfaces, each point can be tested in the following manner;
a. lower die network head 1-upper die LED surface network points 2, 3, 4, 5, 6 … …;
b. whether the test is performed in the same time, it is only necessary to ensure that each point is tested, as shown in fig. 20;
3. insulation test
A. The insulation test principle is that a short circuit is tested between networks;
B. the concrete mode is as follows: network head of test network NET 1-network head of test network NET 2;
C. therefore, for the lamp panel, similarly, because no isolated network exists on the surface of the lamp bead, the short circuit of all networks can be tested by using the points of the lower die.
The above embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical solution according to the technical idea of the present invention fall within the protective scope of the present invention.
Claims (4)
1. A lamp panel jig regional test method is characterized by comprising the following steps:
step 1, based on the two-side measuring point patterns of the lamp panel to be tested, the C side is measured according to the following steps of 1: 1, manufacturing a jig, searching rules for the S surface according to network sequencing, taking the part with the same rules as one partition, and splitting the S surface into N partitions;
step 2, manufacturing test data corresponding to the N partitions respectively, manufacturing a jig based on the test data, and testing different partitions by using the jig respectively;
in the step 2, during testing, the upper die is taken as the surface S, the lower die is taken as the surface C, and the upper die is tested to be conducted by integrally moving the lower jig;
for a lamp panel without an independent point, adopting a test scheme of an open circuit test; for a lamp panel without a single-side measuring point network, a one-to-many test scheme is adopted; for the network of the lamp panel lamp bead surface, for each test point 1, …, a test scheme that a lower die network head Ci corresponds to an upper die LED surface network point Sj is adopted, wherein i, j =1, …, a is not equal to j;
in the step 2, the jig is controlled to be adjusted to different positions according to the test data, so that different partitions of the lamp panel are tested independently, all partitions of the lamp panel are tested to be PASS as PASS boards, and if 1NG exists, corresponding defective paper is pasted and sent to a point finding and confirming mode.
2. The lamp panel jig split-region testing method of claim 1, wherein: before the partition, whether the blind buried hole of the S surface of the lamp panel is conducted or not and whether each test point of the S surface is communicated with the C surface or not are also tested, and the insulation test of the C surface is carried out.
3. The lamp panel jig split-region testing method of claim 2, wherein: when the insulation test of the C surface is carried out, a double-test-point mode is adopted.
4. The lamp panel jig split-region testing method of claim 1, wherein: in the step 1, when the region is split on the S surface, the splitting scheme is determined according to the number and density of the test points.
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