CN113972989A

CN113972989A - Data verification method and device, storage medium and electronic equipment

Info

Publication number: CN113972989A
Application number: CN202010641808.3A
Authority: CN
Inventors: 虎跃
Original assignee: Yulong Computer Telecommunication Scientific Shenzhen Co Ltd
Current assignee: Yulong Computer Telecommunication Scientific Shenzhen Co Ltd
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2022-01-25
Anticipated expiration: 2040-07-06
Also published as: CN113972989B

Abstract

The embodiment of the application discloses a data verification method, a data verification device, a storage medium and electronic equipment, wherein the method comprises the following steps: the method comprises the steps of obtaining mirror image data transmitted by a server, obtaining a target data block in at least one data block included in the mirror image data, controlling a second processor to carry out data verification on the target data block when a first processor is in a verification state, and controlling a third processor to carry out data writing on the target data block after the target data block is verified. By adopting the embodiment of the application, the efficiency of data verification can be improved.

Description

Data verification method and device, storage medium and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data verification method and apparatus, a storage medium, and an electronic device.

Background

Data verification is particularly important along with the development of communication technology, and the data verification can ensure the integrity, correctness and safety of data and verify the input data, and is an important means for system and user data safety in the internet technology.

At present, in the process of data verification, a terminal may allocate a target processor in a processor included in the terminal and then use a serial execution mode, the target processor acquires mirror image data of the data verification, performs data verification on the mirror image data, and writes the mirror image data after the data verification, for example, when an operating system of the terminal is upgraded, the terminal may first acquire mirror image data upgraded by an operating system in a fast boot (fastboot) mode by designating one processor to use the serial execution mode, then perform data verification by the processor, and write the mirror image data after the data verification, thereby completing the whole data verification process of the mirror image data.

Disclosure of Invention

The embodiment of the application provides a data verification method, a data verification device, a storage medium and electronic equipment, and the data verification efficiency can be improved. The technical scheme of the embodiment of the application is as follows:

in a first aspect, an embodiment of the present application provides a data verification method, where the method includes:

acquiring mirror image data transmitted by a server, and acquiring a target data block in at least one data block included in the mirror image data;

when the first processor is in a checking state, controlling the second processor to carry out data checking on the target data block;

and after the target data block passes the verification, controlling a third processor to write data into the target data block.

In a second aspect, an embodiment of the present application provides a data verification apparatus, where the apparatus includes:

the target data block determining module is used for acquiring mirror image data transmitted by a server and acquiring a target data block in at least one data block included in the mirror image data;

the data checking module is used for controlling the second processor to check the data of the target data block when the first processor is in a checking state;

and the data writing module is used for controlling a third processor to write data into the target data block after the target data block passes the verification.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-mentioned method steps.

In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:

in one or more embodiments of the present application, a terminal obtains mirror image data transmitted by a server, obtains a target data block in at least one data block included in the mirror image data, controls a second processor to perform data verification on the target data block when a first processor is in a verification state, and controls a third processor to perform data writing on the target data block after the target data block passes the verification. The target data block corresponding to the mirror image data is obtained by adopting a block transmission mode for the mirror image data, a data check parallel execution mode can be adopted when a first processor for data check is in a check state, a second processor is controlled to check the target data block in parallel, and a third processor is controlled to write data into the data block after the check, so that the problem of low data check efficiency in the related technology during serial execution of data check can be solved, the efficiency in the data check process is improved, the flow of checking the mirror image data is executed in parallel through a plurality of processors (such as the first processor, the second processor and the third processor), and the time of data check is saved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic flowchart of a data verification method provided in an embodiment of the present application;

fig. 2 is a schematic flowchart of another data verification method provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a data verification apparatus according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a data checking module according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another data verification apparatus provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 7 is a schematic structural diagram of an operating system and a user space provided in an embodiment of the present application;

FIG. 8 is an architectural diagram of the android operating system of FIG. 6;

FIG. 9 is an architecture diagram of the IOS operating system of FIG. 6.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it is noted that, unless explicitly stated or limited otherwise, "including" and "having" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

In the related art, in the process of data verification, a terminal may allocate a target processor to a processor included in the terminal, obtain complete mirror image data, obtain the mirror image data of the data verification by the target processor, perform data verification on the mirror image data, and write the mirror image data after the data verification.

The present application will be described in detail with reference to specific examples.

In one embodiment, as shown in fig. 1, a data verification method is proposed, which may be implemented by means of a computer program and may run on a data verification apparatus based on the von neumann architecture. The computer program may be integrated into the application or may run as a separate tool-like application.

Specifically, the data verification method includes:

the data verification device in the embodiment of the present application may be a terminal, and the terminal may be an electronic device having a network experience state determination function, where the electronic device includes but is not limited to: wearable devices, handheld devices, personal computers, tablet computers, in-vehicle devices, smart phones, computing devices or other processing devices connected to a wireless modem, and the like. The terminal devices in different networks may be called different names, for example: user equipment, access terminal, subscriber unit, subscriber station, mobile station, remote terminal, mobile device, user terminal, wireless communication device, user agent or user equipment, cellular telephone, cordless telephone, Personal Digital Assistant (PDA), terminal equipment in a 5G network or future evolution network, and the like.

The server may be an electronic device, which may be a personal computer, a tablet computer, or the like, and may also be a server, which may be a separate server device, for example: the server device may be a hardware device with a relatively high computing power, such as a workstation, a mainframe computer, or the like, or a server cluster composed of a plurality of servers, where each server in the server cluster may be composed in a symmetric manner, where each service is functionally equivalent and functionally equivalent in a service link, and each server may provide services separately to the outside or the inside, such as a service platform for providing mirror image data, where the separate provision of services may be understood as not requiring the assistance of another server.

Step S101: the method comprises the steps of obtaining mirror image data transmitted by a server side, and obtaining a target data block in at least one data block included in the mirror image data.

The mirror image data can be understood as a form of data storage by mirror image, and in practical application, a specific series of files are usually made into a single file data according to a certain format for representing, so as to facilitate terminal downloading and use, such as an operating system, a game, an application program and the like.

In some scenarios, the mirror image data may be mirror image data of a Basic Input Output System (BIOS), and may provide a bottom layer, a direct hardware setting or a control interface for an operating system of the terminal, where the operating system of the terminal may control the hardware system through the BIOS, and taking the operating system of the terminal as an Android system (Android system) as an example, a common writing method of the BIOS mirror image data may be to write the BIOS mirror image data through a fastboot flash mode.

Specifically, the server may be a service providing device that provides a mirror image data obtaining service, the server may be a device that can generate mirror image data (such as BIOS mirror image data) or obtain mirror image data (such as mirror image data provided by BIOS), and send the mirror image data to the terminal, and the terminal may perform data writing on a target data block that the mirror image data passes through currently when receiving the mirror image data according to the verification of each data block included in the mirror image data.

In practical applications, the terminal may receive the mirrored data of the server, where the mirrored data generally includes at least one data block, and the server may push the at least one data block included in the mirrored data to the terminal in real time or periodically in the form of a "data block" stream, for example, the terminal may obtain the data block 1 of the server at a time point T1, obtain the data block 2 of the server at a time point T2, obtain the data block 3 and the data block 4 of the server at a time point T3, illustratively, obtain the mirrored data (generally, one or more data blocks transmitted in the form of a "data block" stream) transmitted by the server, and then the terminal may perform data check on a target data block in the at least one data block included in the mirrored data.

The target data block can be understood as a data block to be checked currently determined by the terminal, and the determination rule of the target data block can be that the receiving time rule of the data block is followed, that is, the data block with an earlier receiving time is determined as the target data block based on the time dimension; the determination rule of the target data block may be that the target data block is determined based on a block sequence of the data blocks, and if the server transmits a plurality of data blocks included in the mirror data, that is, determines a block sequence of each data block, the terminal may determine the target data block to be currently checked based on a fast sequence of the data blocks; the rule for determining the target data block may be based on the priority of the currently received data block, for example, the server has previously determined the priority of each data block (the priority may be determined according to the corresponding functional attribute of each data block); the determination rule of the target data block may be determined based on the memory size of the data block, for example, the terminal may perform a check first on a data block having a larger data block relative to the memory as the target data block, for example, perform a check first on a data block having a smaller data block relative to the memory as the target data block, and for example, the terminal may select a data block matching the remaining memory space as the target data block to perform a check first by combining the current remaining memory space and the memory size of each data block.

It should be noted that the number of the target data blocks may be one or multiple, that is, the terminal may determine multiple target data blocks in the above manner, and perform data verification and data writing on the multiple target data blocks at the same time.

Further, in practical applications, the terminal may be preset with a central processor (which may also be a main processor), and the central processor may be one or a cluster of processors composed of a plurality of processors, in this embodiment of the present application, the central processor is only for distinguishing from other processors (such as the first processor and the second processor) in this embodiment of the present application, and it is understood that the terms "center", "first", "second", and the like are only used for descriptive purposes and are not to be construed as indicating or implying relative importance. The central processor may also be equivalent to other processors in terms of function, performance, etc., which are determined by the implementation environment and are not specifically limited herein.

The terminal can control the central processor to acquire the mirror image data transmitted by the server, and further acquire a target data block in at least one data block included in the mirror image data. On one hand: the central processor may be controlled to determine the status of other processors (e.g., first processor, second processor), such as to determine whether the first processor is in a check state; on one hand: the central processor can be controlled to put the target data block into a check pool and wait for checking by a processor (such as a first processor) to be used for checking the data block; on one hand: when the control center processor determines that the first processor is in the verification state, the second processor may be triggered (e.g., awaken the second processor) to verify the target data block. Therefore, the efficiency of verifying the data block of the mirror image data is improved.

The communication network between the two ends can be pre-established when data communication is carried out between the server and the terminal, the communication network can be a wired network or a wireless network, the wired network can be connected with the data interface on the terminal in a manner of adopting a universal serial/parallel bus, and the data interface comprises but is not limited to a 3.5mm earphone socket, a USB interface, a Type-C interface, a Lightning interface and the like. The wireless Network may be the internet, but may be any other Network including, but not limited to, a Local Area Network (LAN), a Metropolitan Area Network (MAN), a Wide Area Network (WAN), any combination of mobile, wireline or wireless networks, private or virtual private networks.

In this embodiment, when the server and the terminal exchange data via a communication network (for example, the server sends mirror image data to the terminal), technologies and/or formats including Hyper Text Markup Language (HTML), Extensible Markup Language (XML), and the like may be used to represent the data exchanged via the network. All or some of the communication Network links may also be encrypted using conventional encryption techniques such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec), and so on. Custom and/or dedicated data communication techniques may also be used in place of or in addition to the data communication techniques described above.

Step S102: and when the first processor is in a checking state, controlling the second processor to carry out data checking on the target data block.

The first processor may be understood as a processor that the terminal is configured to perform data verification on a data block corresponding to the mirror image data.

The check state may be understood as that the first processor is performing data check on the data block, and in practical applications, on one hand: when the first processor is performing data verification on a previous data block or a historical data block corresponding to the target data block, regarding the processing capability dimension of the slave processor, it is usually difficult to perform data verification on the target data block at this time, and at this time, the terminal may determine that the first processor is in a verification state and is difficult to perform data verification on the target data block in real time; on one hand: when the resource margin of the first processor is difficult to support data verification on the target data block, the terminal can determine that the first processor is in a verification state when the processing capacity dimension of the processor is generally difficult to perform data verification on the target data block.

In a specific implementation scenario, the terminal may detect whether the first processor is performing data verification on a previous data block or a historical data block corresponding to the target data block, and when the first processor is performing data verification on the previous data block or the historical data block corresponding to the target data block, the terminal may determine that the first processor is in a verification state, and based on consideration of timeliness of the data verification, the terminal may control the second processor to perform data verification, that is, trigger the second processor to perform data verification on the target data block, thereby implementing fast verification on the target data block, and meanwhile, when the first processor of the terminal is in the verification state, a multi-processor data verification manner is adopted, so that efficiency of the data verification may be greatly improved. Further, in practical applications, when the second processor does not perform data verification on the data block, the terminal may control the second processor to be in a low power consumption state or a sleep state to save power consumption of the terminal, and when the second processor needs to be called to perform data verification, the terminal may wake up and bring online the second processor by sending a computer executable instruction to the second processor.

In a specific implementation scenario, the first processor may have a capability of performing data verification on multiple data blocks simultaneously, and at this time, the terminal may obtain a resource margin of the first processor, and then determine whether the first processor is in a verification state and cannot perform data verification processing on a target data block based on the resource margin and a requirement for processing a current target data block.

The resource surplus can be understood as the amount of resources left by a processor in meeting the resource requirement of a currently running business thread (such as a business thread processing data block data check), the resources are mainly computing resources of a processor (CPU, GPU), and the definition of the resources can be memory size, the number of I/O ports, computing units, control units and the like associated through the I/O ports. In this embodiment of the application, the terminal may obtain a preset current resource surplus amount of the first processor, and in specific implementation, a process for monitoring the current resource surplus amount of the first processor may be created in advance, and a computing resource of a resource pool is allocated to the process, so as to monitor the current resource surplus amount of the first processor in real time or periodically, and the terminal may obtain the current resource surplus amount of the first processor through the process.

Furthermore, the required amount of the target data block may be determined based on the memory size of the target data block, the terminal may preset a corresponding relationship between the memory size and the required amount, the required amount of the target data block may be determined based on the corresponding relationship, and when the current resource surplus of the first processor is greater than or equal to the required amount of the target data block, the first processor is determined to be in a non-verification state; when the current resource surplus of the first processor is smaller than the demand of the target data block, determining that the first processor is in a check state, wherein the first processor is in the check state, and data check on the target data block is usually difficult to perform at the moment from the aspect of processing capacity dimensionality of the processor; at this time, based on consideration of timeliness of data verification, the terminal can control the second processor to perform data verification, that is, trigger the second processor to perform data verification on the target data block, so that rapid verification of the target data block is realized.

Specifically, the Check of the terminal on the target data block may be implemented based on a set Check algorithm, such as a parity Check algorithm, a bcc xor Check (block Check) method, a Cyclic Redundancy Check (Cyclic Redundancy Check), an MD Check algorithm, and the like.

Taking CRC as an example, in practical applications, on the basis of mirrored data (e.g. k-bit binary code sequence) contained in a data block to be transmitted, an r-bit parity (CRC code) for checking is generated at a transmitting end (e.g. a service end) according to a rule corresponding to CRC, and is attached to the data block (e.g. the back of the included mirrored data) to form a new data block (usually at least k + r bits of binary code sequence) and then transmitted. At a receiving end (such as a terminal), check calculation is carried out according to rules followed between information codes (such as included mirror image data) and CRC codes, comparison is carried out according to check calculation results and CRC codes carried in data blocks, if the check calculation results are consistent, the received data of the data blocks are complete, and if the check calculation results are inconsistent, the data of the data blocks are in error.

In practical application, a specifically adopted data verification algorithm may be determined according to a data verification rule predetermined by a transmitting end and/or a receiving end, and may be one or more of the above mentioned fits, or an algorithm related to data verification in related technologies, where this is not specifically limited, and generally, a data block sent by a server end to a terminal includes at least an algorithm identifier and a verification value corresponding to a verifiable algorithm, so that the terminal can perform corresponding data verification in the data block received by the terminal.

Step S103: and after the target data block passes the verification, controlling a third processor to write data into the target data block.

The third processor may be understood as a processor that writes data into data block data after the data block data corresponding to the mirror image data passes verification by the terminal. It can be understood that, in the embodiment of the present application, data verification and data writing are performed by different processors, so that efficiency of data block writing and data block verification in a data verification process can be greatly improved, further, when a terminal receives multiple data blocks corresponding to mirror image data transmitted by a server at the same time, the terminal can use all the multiple data blocks as target data blocks, and parallel processing of the mirror image data, such as parallel data verification, parallel data writing and the like, is implemented by executing the method of the embodiment of the present application.

The third processor may be a processor that is determined by the terminal in advance based on the processing speeds of the plurality of processors included in the terminal, and for example, the terminal may use a specified number (e.g., 1) of processors with the fastest data writing speed as the third processor.

Specifically, the terminal acquires a target data block in at least one data block included in the mirror image data, establishes a target thread for writing the data block into the target data block after the target data block passes verification, and calls computing resources of a resource pool included in the terminal for the target thread to write the data into the target data block after the data block is verified. Further, the terminal may obtain a data writing state of a third processor, and when the data writing state meets a requirement for writing the target data block data, control the third processor to write the data into the target data block; when the data writing state does not meet the requirement for writing the target data block data, the terminal may trigger a fourth processor in an idle state to write the data into the target data block, where the fourth processor may be understood as a processor on the terminal except for the first processor and the third processor, and in some implementation scenarios, when the second processor is in the idle state (or in a sleep state), the fourth processor and the second processor may be the same processor.

Further, the data writing state of the third processor may be characterized by a resource margin of the third processor, the requirement for writing the target data block data may be characterized by a resource demand for writing the target data block data, and when the resource margin is greater than or equal to the resource demand, the terminal controls the third processor to write data into the target data block; and when the resource surplus is less than the resource demand, the terminal triggers the fourth processor in an idle state to write data into the target data block.

Specifically, the terminal controls the third processor to write data into the target data block, which may be directly writing the target data block into original data corresponding to the mirror image data, where the original data may be understood as data to be overwritten on the terminal (e.g., a file corresponding to some applications). Generally, when the terminal determines that the data verification of the target data block passes, the terminal may determine original data to be covered corresponding to mirror image data represented by the target data block (i.e., determine the original data to be covered corresponding to the target data block), and then cover the original data based on the data in the target data block.

Specifically, the terminal checks the target data block by controlling the second processor, and when it is determined that the target data block is consistent with the check value carried by the target data block based on the check result, the terminal may determine that the target data block passes the check, and at this time, the terminal may control the third processor to perform data analysis processing on the target data block, and then determine a mapping path when data in the target data block is updated, where the mapping path generally corresponds to a storage address to which original data to be covered on the terminal belongs, such as determining a file name of a directory file to be covered, and then the terminal controls the third processor to write the data in the target data block into the storage address indicated by the mapping path, so as to complete data coverage on the original data on the storage address, thereby implementing data writing on the target data block.

In the embodiment of the application, a terminal acquires mirror image data transmitted by a server, acquires a target data block in at least one data block included in the mirror image data, controls a second processor to perform data verification on the target data block when a first processor is in a verification state, and controls a third processor to perform data writing on the target data block after the target data block passes the verification. The target data block corresponding to the mirror image data is obtained by adopting a block transmission mode for the mirror image data, a data check parallel execution mode can be adopted when a first processor for data check is in a check state, a second processor is controlled to check the target data block in parallel, and a third processor is controlled to write data into the data block after the check, so that the problem of low data check efficiency in the related technology during serial execution of data check can be solved, the efficiency in the data check process is improved, the flow of checking the mirror image data is executed in parallel through a plurality of processors (such as the first processor, the second processor and the third processor), and the time of data check is saved.

Referring to fig. 2, fig. 2 is a schematic flowchart illustrating another embodiment of a data verification method according to the present application. Specifically, the method comprises the following steps:

step S201: and performing performance detection on all the included processors, and determining the processing speed corresponding to each processor.

Specifically, before data verification, the terminal may perform performance detection on all processors included in the terminal in an actual application environment, so as to detect hardware performance parameters of the terminal; the hardware performance parameters include the comprehensive operation speed of the processor, the single-thread integer operation speed, the single-thread floating-point operation speed, the multi-thread integer operation speed, the multi-thread floating-point operation speed and the like. In an actual test scene, at least one of single-thread integer arithmetic, single-thread floating-point arithmetic, multi-thread integer arithmetic and multi-thread floating-point arithmetic is adopted to respectively execute a preset test operation task, and the test operation task can be understood as a data verification task, a data writing task, a data analysis task and the like. And determining the processing speed corresponding to the processor according to the operation result and the operation completion time length respectively corresponding to each test operation task.

In practical applications, the processing speed may include processing speeds (such as data verification speed, data writing speed, data parsing speed) in multiple test operation scenarios, and an integrated processing speed, where the integrated processor speed is calculated based on the processing speed in each test operation scenario in a weighted manner to determine a speed value.

In practical applications, the processor operation speed itself is floating, i.e. the processor frequency, which can be understood as the total amount of binary computation in a single cycle. The logical operation can be understood as an integral of a large number of binary computations. The method comprises the steps of testing integer and floating point number calculation through single thread and multithreading, quantifying a test result, and testing the efficiency of a processor by calculating the time length of the processor for completing quantitative logic operation. For example, the performance of the processor can be judged according to the time length of the operation completion, and the shorter the time length, the better the performance, i.e. the faster the operation speed. Preferably, the logic operations executed by the single-thread integer arithmetic, the single-thread floating-point arithmetic, the multi-thread integer arithmetic and the multi-thread floating-point arithmetic are logic operations with the same priority.

Furthermore, by detecting the performance of all the processors included in the terminal in the above manner, the processing speed corresponding to each processor can be determined.

Step S202: among the processors, the processor with the highest processing speed is used as a third processor, and the processors with the highest processing speed except the third processor are used as the first processor.

The third processor is used for writing data into the data block in the data checking process, and the first processor is used for checking the data of the data block in the data checking process.

Specifically, the terminal may use the processor with the highest processing speed as the third processor for writing data into the data block, and then use the processor with the highest processing speed except for the third processor as the first processor for performing data verification on the data block. Further, when the number of the third processors or the first processors provided is plural, the terminal may determine the specified number of the first processors or the third processors based on the processing speed of each processor, such as the first 2 processors with the fastest processing speed as the third processors.

Optionally, the terminal may also determine the corresponding processor based on the processing type (e.g., data verification type, data write type), for example, a processor with the fastest data write is used as the third processor, and a processor with the fastest data verification speed except for the third processor is used as the first processor.

Step S203: the method comprises the steps of obtaining mirror image data transmitted by a server side, and obtaining a target data block in at least one data block included in the mirror image data.

Specifically, refer to step S101, which is not described herein again.

Step S204: acquiring a processor running log, and determining that the processor running log does not have an exception handling identifier.

The processor running log is used for recording relevant running information of at least one processor contained in the terminal in a running process, such as a target data block for recording processing at a certain time point, processor resource overhead for processing the target data block, processor slicing time, time for context switching, an exception handling identifier when the target data block is processed abnormally, and the like.

The exception handling identifier is used for characterizing records when data blocks are handled abnormally (such as data check failure and data write failure), and is generally an id or a name uniquely characterizing the data blocks when the data blocks are handled abnormally, for example, 1, 2, 3 and other numbers representing the id; the method can be used for uniquely characterizing key characters in abnormal processing of the data block, such as a, b, c and the like; the method can be used for uniquely characterizing key character strings in abnormal processing of the data blocks, such as pth _ a, pth _ b and pth _ c; and so on.

Specifically, before starting data verification on a target data block, the terminal traverses the processor running log to judge whether at least one data block corresponding to the mirror image data is processed abnormally, such as failure in verifying the data block, failure in writing the data block, and the like.

When determining that the processor running log does not have the exception handling identifier, the terminal executes the step of step S205;

when the running log is determined to have the abnormal processing identifier, the terminal can determine that the mirror image data check fails, and at the moment, the current target data block does not need to be checked.

In a specific implementation scenario, when the terminal controls the first processor (or the second processor) to fail to verify the target data block data, if a verification value of the target data block is inconsistent with a verification value carried by the target data block, that is, the data verification fails, the terminal may generate an exception handling identifier for the mirror data, record a data verification condition of this time, and then store the exception handling identifier in the processor running log. Or the like, or, alternatively,

when the terminal controls the third processor to write the target data block data in a failure condition, for example, the data block data is inconsistent with the data type supportable by the terminal, that is, the data writing fails, the terminal may generate an exception handling identifier for the mirror image data, record the data writing condition, and then store the exception handling identifier in the processor running log

Step S205: and when the first processor is in the checking state, acquiring the working state of at least one checking processor.

Step S102 may be referred to for specific determination that the first processor is in the checking state, which is not described herein again.

Specifically, when the first processor is in the checking state, the terminal may obtain an operating state of at least one included checking processor, and determine the second processor based on the operating state of each checking processor.

Wherein the operating state includes at least an idle state and a check state.

The check processor may be understood as a processor included in the terminal except for the first processor and the third processor, which may be used as a check processor, or a standby processor pre-designated by the terminal for data check.

In practical application, the terminal may determine the working state of each check processor by traversing at least one check processor included in the terminal, and in practical application, the terminal may determine the working state of each check processor by acquiring working information of the check processor based on the operation of the processor, such as a memory space type of the operation of the processor: the memory space type comprises a user space and a kernel space, whether a user process is executed or not, whether the memory space type is in a process context state or not and whether the memory space type is in a terminal context state or not; furthermore, when the process running in the kernel space and representing the idle state of the inspection processor is normally executed, the inspection processor can be judged to be in the idle state; when the checking processor runs in user space and is in process context, it executes on behalf of a process, such as: the application layer interacts with the kernel, requiring the kernel or driver layer to run specific tasks, such as writing files, etc.

Step S206: and taking the checking processor with the working state being an idle state as a second processor, and controlling the second processor to check the data of the target data block.

Specifically, after the terminal acquires the working state of at least one checking processor, the checking processor with the working state being the idle state may be used as the second processor, and further, when there are a plurality of checking processors in the idle state, the terminal may determine the second processor based on the processing speed of the checking processor, for example, the processor with the fastest processing speed and the working state being the idle state is used as the second processor.

Specifically, the step S102 may be referred to for controlling the second processor to perform data verification on the target data block, and details are not repeated here.

Step S207: and determining that the second processor completes verification of the target data block data, and controlling the second processor to enter a sleep state.

Specifically, when the terminal controls the second processor to complete the verification of the target data block data, the second processor may be controlled to enter a sleep state, so as to reduce the power consumption of the terminal.

After the terminal controls the second processor to perform data verification on the target data block, the data verification result is that the verification is passed or the verification fails, and at this time, the data verification on the target data block is usually completed.

Step S208: and after the target data block passes the verification, controlling a third processor to write data into the target data block.

Specifically, refer to step S103, which is not described herein again.

Step S209: a next data block of the target data block is obtained, and step S204 is executed with the next data block as the target data block.

Specifically, after determining that the target data block passes verification and successfully writes data into the target data block, the terminal determines a next data block of the target data block based on a "rule for determining a target data block", if a data block received after a time point corresponding to the target data block is determined as the next data block of the target data block based on a time dimension, if the data block is determined based on a block sequence of the data block, the terminal obtains the next data block indicated by the next block sequence corresponding to the target data block, and so on, after determining the next data block of the target data block, the terminal takes the next data block of the target data block as the target data block, and then step S204 is executed.

Step S210: and when the next data block does not exist, determining that the mirror image data is verified successfully.

Specifically, when the terminal determines that the target data block is the last data block corresponding to the mirror data, the next data block does not exist, and the terminal may determine that the mirror data passes the verification.

In the embodiment of the application, a terminal acquires mirror image data transmitted by a server, acquires a target data block in at least one data block included in the mirror image data, controls a second processor to perform data verification on the target data block when a first processor is in a verification state, and controls a third processor to perform data writing on the target data block after the target data block passes the verification. The target data block corresponding to the mirror image data is obtained by adopting a block transmission mode for the mirror image data, a data verification parallel execution mode can be adopted when a first processor for data verification is in a verification state, a second processor is controlled to perform verification on the target data block in parallel, and a third processor is controlled to perform data writing on the data block after verification, so that the problem of low data verification efficiency in the related technology during serial execution of data verification can be solved, the efficiency in the data verification process is improved, the flow of verifying the mirror image data is executed in parallel through a plurality of processors (such as the first processor, the second processor and the third processor), and the time of data verification is saved; and in the data verification process, when the data verification fails or the data writing fails, the abnormal processing identifier can be stored in the processor running log, so that the mechanism for verifying the mirror image data block data is optimized.

The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.

Please refer to fig. 3, which shows a schematic structural diagram of a data verification apparatus according to an exemplary embodiment of the present application. The data verification means may be implemented as all or part of the apparatus in software, hardware or a combination of both. The apparatus 1 comprises a target data block determination module 11, a data verification module 12 and a data writing module 13.

The target data block determining module 11 is configured to obtain mirror image data transmitted by a server, and obtain a target data block in at least one data block included in the mirror image data;

the data checking module 12 is configured to control the second processor to perform data checking on the target data block when the first processor is in a checking state;

and the data writing module 13 is configured to control the third processor to write data into the target data block after the target data block passes the verification.

Optionally, as shown in fig. 5, the apparatus 1 includes:

and the running log checking module 14 is configured to obtain a processor running log, determine that the processor running log does not have an exception handling identifier, and call the data checking module 12 to control the second processor to perform data checking on the target data block when the first processor is in a checking state.

Optionally, the operation log checking module 14 is specifically configured to:

and when the running log has an exception handling identifier, determining that the mirror image data fails to be checked.

Optionally, as shown in fig. 5, the apparatus 1 includes:

a next data block obtaining module 15, configured to obtain a next data block of the target data block, and perform, with the next data block as the target data block, the step of controlling the second processor to perform data verification on the target data block when the first processor is in a verification state;

the data checking module 12 is further configured to determine that the mirror data is successfully checked when the next data block does not exist.

Optionally, as shown in fig. 4, the data checking module 12 includes:

a working state obtaining unit 121, configured to obtain a working state of at least one included checking processor when the first processor is in a checking state;

a second processor determining unit 122, configured to use the check processor whose operating state is an idle state as the second processor;

and a data checking unit 123, configured to control the second processor to perform data checking on the target data block.

Optionally, the data checking module 12 is specifically configured to:

and determining that the second processor completes the inspection of the target data block data, and controlling the second processor to enter a sleep state.

Optionally, as shown in fig. 5, the apparatus 1 includes:

a processing speed determining module 16, configured to perform performance detection on all processors included in the system, and determine a processing speed corresponding to each processor;

and a processor determining module 17, configured to, in each of the processors, use the processor with the highest processing speed as a third processor, and use the processor with the highest processing speed except the third processor as the first processor.

Optionally, the apparatus 1 is specifically configured to:

and when the data verification of the target data block fails or the data writing fails, generating an exception handling identifier aiming at the mirror image data, and storing the exception handling identifier into the running log of the processor.

It should be noted that, when the data verification apparatus provided in the foregoing embodiment executes the data verification method, only the division of the functional modules is illustrated, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the data verification apparatus and the data verification method provided in the above embodiments belong to the same concept, and details of implementation processes thereof are referred to in the method embodiments and are not described herein again.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

In this embodiment, a terminal acquires mirror image data transmitted by a server, acquires a target data block in at least one data block included in the mirror image data, controls a second processor to perform data verification on the target data block when a first processor is in a verification state, and controls a third processor to perform data writing on the target data block after the target data block is verified. The target data block corresponding to the mirror image data is obtained by adopting a block transmission mode for the mirror image data, a data verification parallel execution mode can be adopted when a first processor for data verification is in a verification state, a second processor is controlled to perform verification on the target data block in parallel, and a third processor is controlled to perform data writing on the data block after verification, so that the problem of low data verification efficiency in the related technology during serial execution of data verification can be solved, the efficiency in the data verification process is improved, the flow of verifying the mirror image data is executed in parallel through a plurality of processors (such as the first processor, the second processor and the third processor), and the time of data verification is saved; and in the data verification process, when the data verification fails or the data writing fails, the abnormal processing identifier can be stored in the processor running log, so that the mechanism for verifying the mirror image data block data is optimized.

An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are suitable for being loaded by a processor and executing the data verification method according to the embodiments shown in fig. 1 to fig. 2, and a specific execution process may refer to specific descriptions of the embodiments shown in fig. 1 to fig. 2, which is not described herein again.

The present application further provides a computer program product, where at least one instruction is stored, and the at least one instruction is loaded by the processor and executes the data verification method according to the embodiment shown in fig. 1 to fig. 2, where a specific execution process may refer to specific descriptions of the embodiment shown in fig. 1 to fig. 2, and is not described herein again.

Referring to fig. 6, a block diagram of an electronic device according to an exemplary embodiment of the present application is shown. The electronic device in the present application may comprise one or more of the following components: a processor 110, a memory 120, an input device 130, an output device 140, and a bus 150. The processor 110, memory 120, input device 130, and output device 140 may be connected by a bus 150.

Processor 110 may include one or more processing cores. The processor 110 connects various parts within the overall electronic device using various interfaces and lines, and performs various functions of the electronic device 100 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 120 and calling data stored in the memory 120. Alternatively, the processor 110 may be implemented in hardware using at least one of Digital Signal Processing (DSP), field-programmable gate Array (FPGA), and Programmable Logic Array (PLA). The processor 110 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 110, but may be implemented by a communication chip.

The Memory 120 may include a Random Access Memory (RAM) or a read-only Memory (ROM). Optionally, the memory 120 includes a non-transitory computer-readable medium. The memory 120 may be used to store instructions, programs, code sets, or instruction sets. The memory 120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like, and the operating system may be an Android (Android) system, including a system based on Android system depth development, an IOS system developed by apple, including a system based on IOS system depth development, or other systems. The data storage area may also store data created by the electronic device during use, such as phone books, audio and video data, chat log data, and the like.

Referring to fig. 7, the memory 120 may be divided into an operating system space, in which an operating system runs, and a user space, in which native and third-party applications run. In order to ensure that different third-party application programs can achieve a better operation effect, the operating system allocates corresponding system resources for the different third-party application programs. However, the requirements of different application scenarios in the same third-party application program on system resources are different, for example, in a local resource loading scenario, the third-party application program has a higher requirement on the disk reading speed; in the animation rendering scene, the third-party application program has a high requirement on the performance of the GPU. The operating system and the third-party application program are independent from each other, and the operating system cannot sense the current application scene of the third-party application program in time, so that the operating system cannot perform targeted system resource adaptation according to the specific application scene of the third-party application program.

In order to enable the operating system to distinguish a specific application scenario of the third-party application program, data communication between the third-party application program and the operating system needs to be opened, so that the operating system can acquire current scenario information of the third-party application program at any time, and further perform targeted system resource adaptation based on the current scenario.

Taking an operating system as an Android system as an example, programs and data stored in the memory 120 are as shown in fig. 8, and a Linux kernel layer 320, a system runtime library layer 340, an application framework layer 360, and an application layer 380 may be stored in the memory 120, where the Linux kernel layer 320, the system runtime library layer 340, and the application framework layer 360 belong to an operating system space, and the application layer 380 belongs to a user space. The Linux kernel layer 320 provides underlying drivers for various hardware of the electronic device, such as a display driver, an audio driver, a camera driver, a bluetooth driver, a Wi-Fi driver, power management, and the like. The system runtime library layer 340 provides a main feature support for the Android system through some C/C + + libraries. For example, the SQLite library provides support for a database, the OpenGL/ES library provides support for 3D drawing, the Webkit library provides support for a browser kernel, and the like. Also provided in the system runtime library layer 340 is an Android runtime library (Android runtime), which mainly provides some core libraries that can allow developers to write Android applications using the Java language. The application framework layer 360 provides various APIs that may be used in building an application, and developers may build their own applications by using these APIs, such as activity management, window management, view management, notification management, content provider, package management, session management, resource management, and data verification management. At least one application program runs in the application layer 380, and the application programs may be native application programs carried by the operating system, such as a contact program, a short message program, a clock program, a camera application, and the like; or a third-party application developed by a third-party developer, such as a game application, an instant messaging program, a photo beautification program, a data verification program, and the like.

Taking an operating system as an IOS system as an example, programs and data stored in the memory 120 are shown in fig. 9, and the IOS system includes: a Core operating system Layer 420(Core OS Layer), a Core Services Layer 440(Core Services Layer), a Media Layer 460(Media Layer), and a touchable Layer 480(Cocoa Touch Layer). The kernel operating system layer 420 includes an operating system kernel, drivers, and underlying program frameworks that provide functionality closer to hardware for use by program frameworks located in the core services layer 440. The core services layer 440 provides system services and/or program frameworks, such as a Foundation framework, an account framework, an advertisement framework, a data storage framework, a network connection framework, a geographic location framework, a motion framework, and so forth, as required by the application. The media layer 460 provides audiovisual related interfaces for applications, such as graphics image related interfaces, audio technology related interfaces, video technology related interfaces, audio video transmission technology wireless playback (AirPlay) interfaces, and the like. Touchable layer 480 provides various common interface-related frameworks for application development, and touchable layer 480 is responsible for user touch interaction operations on the electronic device. Such as a local notification service, a remote push service, an advertising framework, a game tool framework, a messaging User Interface (UI) framework, a User Interface UIKit framework, a map framework, and so forth.

In the framework illustrated in FIG. 9, the framework associated with most applications includes, but is not limited to: a base framework in the core services layer 440 and a UIKit framework in the touchable layer 480. The base framework provides many basic object classes and data types, provides the most basic system services for all applications, and is UI independent. While the class provided by the UIKit framework is a basic library of UI classes for creating touch-based user interfaces, iOS applications can provide UIs based on the UIKit framework, so it provides an infrastructure for applications for building user interfaces, drawing, processing and user interaction events, responding to gestures, and the like.

The Android system can be referred to as a mode and a principle for realizing data communication between the third-party application program and the operating system in the IOS system, and details are not repeated herein.

The input device 130 is used for receiving input instructions or data, and the input device 130 includes, but is not limited to, a keyboard, a mouse, a camera, a microphone, or a touch device. The output device 140 is used for outputting instructions or data, and the output device 140 includes, but is not limited to, a display device, a speaker, and the like. In one example, the input device 130 and the output device 140 may be combined, and the input device 130 and the output device 140 are touch display screens for receiving touch operations of a user on or near the touch display screens by using any suitable object such as a finger, a touch pen, and the like, and displaying user interfaces of various applications. Touch displays are typically provided on the front panel of an electronic device. The touch display screen may be designed as a full-face screen, a curved screen, or a profiled screen. The touch display screen can also be designed to be a combination of a full-face screen and a curved-face screen, and a combination of a special-shaped screen and a curved-face screen, which is not limited in the embodiment of the present application.

In addition, those skilled in the art will appreciate that the configurations of the electronic devices illustrated in the above-described figures do not constitute limitations on the electronic devices, which may include more or fewer components than illustrated, or some components may be combined, or a different arrangement of components. For example, the electronic device further includes a radio frequency circuit, an input unit, a sensor, an audio circuit, a wireless fidelity (WiFi) module, a power supply, a bluetooth module, and other components, which are not described herein again.

In the embodiment of the present application, the main body of execution of each step may be the electronic device described above. Optionally, the execution subject of each step is an operating system of the electronic device. The operating system may be an android system, an IOS system, or another operating system, which is not limited in this embodiment of the present application.

The electronic device of the embodiment of the application can also be provided with a display device, and the display device can be various devices capable of realizing a display function, for example: a cathode ray tube display (CR), a light-emitting diode display (LED), an electronic ink panel, a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), and the like. A user may utilize a display device on the electronic device 101 to view information such as displayed text, images, video, and the like. The electronic device may be a smartphone, a tablet computer, a gaming device, an AR (Augmented Reality) device, an automobile, a data storage device, an audio playback device, a video playback device, a notebook, a desktop computing device, a wearable device such as an electronic watch, an electronic glasses, an electronic helmet, an electronic bracelet, an electronic necklace, an electronic garment, or the like.

In the electronic device shown in fig. 6, where the electronic device may be a terminal, the processor 110 may be configured to call the data verification application stored in the memory 120, and specifically perform the following operations:

In one embodiment, the processor 110, after executing the obtaining of the target data block of the at least one data block included in the mirror data, further performs the following operations:

acquiring a processor running log;

and when the processor running log does not have the exception handling identification, executing the step of controlling the second processor to carry out data checking on the target data block when the first processor is in the checking state.

In one embodiment, the processor 110, after executing the get processor execution log, further performs the following:

acquiring a next data block of the target data block, and performing data verification on the target data block by controlling a second processor when the first processor is in a verification state by taking the next data block as the target data block;

and when the next data block does not exist, determining that the mirror image data is verified successfully.

In an embodiment, when the processor 110 executes the data verification performed on the target data block by the second processor when the first processor is in the verification state, the following operations are specifically performed:

when the first processor is in a checking state, acquiring the working state of at least one checking processor;

and taking the checking processor with the working state being an idle state as a second processor, and controlling the second processor to check the data of the target data block.

In one embodiment, the processor 110, when executing the data verification method, further performs the following operations:

performing performance detection on all processors contained in the system, and determining the processing speed corresponding to each processor;

among the processors, the processor with the highest processing speed is used as a third processor, and the processors with the highest processing speed except the third processor are used as the first processor.

It is clear to a person skilled in the art that the solution of the present application can be implemented by means of software and/or hardware. The "unit" and "module" in this specification refer to software and/or hardware that can perform a specific function independently or in cooperation with other components, where the hardware may be, for example, a Field-ProgrammaBLE Gate Array (FPGA), an Integrated Circuit (IC), or the like.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some service interfaces, devices or units, and may be an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program, which is stored in a computer-readable memory, and the memory may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The above description is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure should not be limited thereby. That is, all equivalent changes and modifications made in accordance with the teachings of the present disclosure are intended to be included within the scope of the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method for data verification, the method comprising:

2. The method of claim 1, wherein after obtaining the target data block of the at least one data block included in the mirrored data, further comprising:

acquiring a processor running log;

and determining that the processor running log does not have an exception handling identifier, and executing the step of controlling the second processor to carry out data checking on the target data block when the first processor is in a checking state.

3. The method of claim 2, wherein after obtaining the processor execution log, further comprising:

4. The method of claim 1, wherein after controlling the third processor to write data to the target data block, further comprising:

5. The method of claim 1, wherein controlling the second processor to perform data verification on the target data block when the first processor is in the verification state comprises:

6. The method of claim 5, further comprising:

and determining that the second processor completes verification of the target data block data, and controlling the second processor to enter a sleep state.

7. The method according to claim 1, wherein before acquiring the mirror data transmitted by the server, the method further comprises:

8. The method of claim 2, further comprising:

9. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to carry out the method steps according to any one of claims 1 to 8.

10. An electronic device, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 8.