CN113946277A - Data reading method and device in host efficiency acceleration mode - Google Patents
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Abstract
The invention relates to a data reading method and device in a host efficiency acceleration mode, wherein the method is executed by a host end and comprises the following steps: obtaining the value of an expansion device special data register in a flash memory controller from the flash memory controller; and when the value of the special data register of the expansion device comprises the information supporting the host performance acceleration function, allocating space in the system memory as a host performance acceleration buffer, and storing a plurality of logical physical comparison records acquired from the flash memory controller in the host performance acceleration buffer. The host terminal and the flash memory controller communicate with each other using an embedded multimedia card communication protocol, and each logical physical control records information that data storing logical addresses are actually stored at physical addresses. The invention can enable the host end to send the reading command with the logical-physical comparison record to the flash memory controller through the arrangement of the host efficiency acceleration buffer, and is used for reducing the time consumed by the flash memory controller and the logical-physical comparison conversion of the operation resources.
Description
Technical Field
The present invention relates to a storage device, and more particularly, to a data reading method and apparatus in a host performance acceleration mode.
Background
Flash memories are generally classified into NOR flash memories and NAND flash memories. NOR flash is a random access device and a central processing unit (Host) may provide any address on an address pin to access NOR flash and obtain data stored at the address from a data pin of NOR flash in a timely manner. In contrast, NAND flash memory is not random access, but serial access. NAND flash does not have access to any random address, as NOR flash does cpu need to write serial byte (Bytes) values to NAND flash for defining the type of Command (Command) (e.g., read, write, erase, etc.) and the address used on the Command. The address may point to one page (the smallest data block for a write operation in flash memory) or one block (the smallest data block for an erase operation in flash memory).
In order to improve the data writing and reading efficiency of the flash memory module, the device side performs data writing and reading in parallel by using a plurality of channels. For the purpose of parallel processing, a continuous piece of data is stored dispersedly in flash memory units connected to multiple channels, and a Logical-to-physical (L2P Mapping Table) is used to record the correspondence between the Logical address (managed by the host) and the physical address (managed by the flash memory controller) of the user data. However, in the storage device of the embedded multimedia card (e.mmc), as the device capacity increases rapidly, the length of the logical-physical mapping table also grows by multiple, which makes the traditional management method executed on the device side hard to bear. Even though the use of hierarchical sub-regions to manage logical-physical mapping tables can improve the performance of logical-physical mapping translation, the time spent on logical-physical mapping translation is much longer than the time (tR) to transfer data from the flash memory array of the flash memory module to the data register of the flash memory controller. Therefore, the present invention provides a data reading method and device in a host performance acceleration mode, which are used for improving the data reading performance of a storage device of an embedded multimedia card.
Disclosure of Invention
In view of the above, it is a problem to be solved how to alleviate or eliminate the above-mentioned drawbacks of the related art.
The invention relates to a data reading method of a host efficiency acceleration mode, which is executed by a host end and comprises the following steps: obtaining the value of an expansion device special data register in a flash memory controller from the flash memory controller; and when the value of the special data register of the expansion device comprises the information supporting the host performance acceleration function, allocating space in the system memory as a host performance acceleration buffer, and storing a plurality of logical physical comparison records acquired from the flash memory controller in the host performance acceleration buffer.
The invention also relates to a data reading method of the host efficiency acceleration mode, which is executed by the flash memory controller and comprises the following steps: in the process of initializing the storage device, the reserved bit of the expansion device special data register in the flash memory controller is set for indicating that the storage device supports the host performance acceleration function, so that the host can allocate space in the system memory as a host performance acceleration buffer according to the information of the reserved bit of the expansion device special data register, and a plurality of logical and physical comparison records obtained from the flash memory controller are stored in the host performance acceleration buffer.
The present invention further relates to a device for reading data in a host performance acceleration mode, comprising: extending device-specific data registers; a host interface; and a processing unit. The processing unit sets a reserved bit of the special data register of the expansion device in the process of device initialization, and is used for indicating that the device supports the host performance acceleration function, so that the host end can configure a space in the system memory as a host performance acceleration buffer area according to the information of the reserved bit of the special data register of the expansion device, and a plurality of logical and physical comparison records acquired from the device through a host interface are stored in the host performance acceleration buffer area.
The host terminal and the flash memory controller communicate with each other using an embedded multimedia card communication protocol, and each logical physical reference records information of a physical address where data for storing a logical address is actually stored.
One of the advantages of the above embodiments is that the host performance acceleration buffer can be configured to enable the host to send a read command with a logical-physical mapping record to the flash memory controller, so as to reduce the time consumption and computational resources of the flash memory controller for performing the logical-physical mapping conversion.
Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.
Fig. 1 is a system architecture diagram of an electronic device according to an embodiment of the invention.
FIG. 2 is a diagram of a flash memory device according to an embodiment of the invention.
FIG. 3 is a diagram illustrating an association between a high level lookup table and a logical-physical lookup sub-table according to an embodiment of the invention.
FIG. 4 is a diagram illustrating an association between a logical-physical table and a physical page according to an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating establishment and operation of a Host Performance Acceleration (HPA) cache according to an embodiment of the present invention.
Fig. 6 is an operation sequence diagram for HPA buffer initialization according to an embodiment of the present invention.
Fig. 7 and 8 are operation sequence diagrams of HPA reads, according to embodiments of the present invention.
Fig. 9 is an operation sequence diagram of HPA buffer update according to an embodiment of the present invention.
FIG. 10 is a flowchart illustrating a method for executing a handover command according to an embodiment of the invention.
FIG. 11 is a flowchart illustrating a method for executing a write multi-block command according to an embodiment of the present invention.
Wherein the symbols in the drawings are briefly described as follows:
10: an electronic device; 110: a host end; 130: a flash memory controller; 131: a host interface; 132: a bus; 134: a processing unit; 135: a read-only memory; 136: a random access memory; 137: a register; 139: a flash memory interface; 150: a flash memory device; 151: an interface; 153#0 to 153# 15: a NAND flash memory cell; CH # 0 to CH # 3: a channel; CE # 0 to CE # 3: a start signal; 310: a high-order comparison table; 330#0 to 330# 15: L2P reference; 400: L2P control record; 410: information of logical block addresses; 430: information of physical block addresses; 430-0: a logical unit number and a physical block number; 430-1: numbering physical pages; 440: a physical block; 450: a physical page; 450# 2: a physical section; 500: HPA caching; 610 to 655, 711 to 755, 835 to 839, 915, 931, 955: operating; s1010 to S1060, S1110 to S1147: the method comprises the following steps.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of further features, integers, steps, operations, elements, components, and/or groups thereof.
The use of words such as "first," "second," "third," etc. in this disclosure is intended to modify a component in a claim and is not intended to imply a priority order, precedence relationship, or order between components or steps in a method.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar manner, e.g., "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.
Refer to fig. 1. The electronic Device 10 includes a host Device (also referred to as a host Side) 110, a flash memory controller 130 and a flash memory Device 150, and the flash memory controller 130 and the flash memory Device 150 may be collectively referred to as a Device Side (Device Side). The electronic device 10 may be implemented in a personal computer, a notebook computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, and other electronic products. The Host Interface (Host Interface)131 of the Host device 110 and the flash memory Controller 130 may communicate with each other in an embedded Multi-Media Controller (e.mmc/eMMC) communication protocol. Flash Interface 139 of Flash controller 130 and Flash device 150 may communicate with each other in a Double Data Rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), Double Data Rate switch (DDR Toggle) or other communication protocol. Flash controller 130 includes a processing unit 134, which may be implemented in a variety of ways, such as using general purpose hardware (e.g., a micro control unit, a central processing unit, a multi-processor with parallel processing capability, a graphics processor, or other processor with computing capability), and providing the functionality described hereinafter when executing software and/or firmware instructions. The processing unit 134 receives eMMC commands through the host interface 131 and executes the commands. The flash Memory controller 130 includes a Random Access Memory (RAM) 136, which may be implemented as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or a combination thereof, for configuring a space as a data buffer. The random access memory 136 may additionally store data, such as variables, data tables, etc., that is needed during execution. The flash Memory controller 130 includes a Read Only Memory (ROM) 135 for storing program codes to be executed when booting. The Flash interface 139 includes a NAND Flash Controller (NFC) and provides functions required for accessing the Flash device 150, such as a Command serializer (Command), a Low Density Parity Check (LDPC), and the like.
A Bus Architecture (Bus Architecture)132 may be configured in the flash controller 130 for coupling components including a host interface 131, a processing unit 134, a ROM 135, a RAM136, a register 137, a flash memory interface 139, etc. to each other to transfer data, addresses, control signals, etc. In some embodiments, host interface 131, processing unit 134, ROM 135, RAM136, registers 137, and flash interface 139 may be coupled to each other by a single bus. In other embodiments, the flash controller 130 may be configured with a high-speed bus for coupling the processing unit 134, the ROM 135, the RAM136 and the register 137 to each other, and a low-speed bus for coupling the processing unit 134, the host interface 131 and the flash interface 139 to each other. The bus comprises parallel physical lines connecting more than two components of the flash controller 130.
The flash memory device 150 provides a large amount of storage space, typically hundreds of Gigabytes (GB), or even Terabytes (TB), for storing large amounts of user data, such as high resolution pictures, movies, and the like. The flash memory device 150 includes a control circuit and a memory array, and the memory Cells in the memory array may be configured as Single Level Cells (SLCs), multi-Level Cells (MLCs), Triple Level Cells (TLCs), Quad-Level Cells (QLCs), or any combination thereof. Processing unit 134 writes user data to a specified address (destination address) in flash device 150 via flash interface 139 and reads the user data from the specified address (source address) in flash device 150 and a specified portion of the L2P lookup table. Flash interface 139 uses a plurality of electronic signals to coordinate the Data and command transmission between flash controller 130 and flash device 150, including Data Line (Data Line), Clock Signal (Clock Signal) and Control Signal (Control Signal). The data lines can be used for transmitting commands, addresses, read-out and written-in data; the control signal line may be used to transmit control signals such as Chip Enable (CE), Address fetch Enable (ALE), Command fetch Enable (CLE), Write Enable (WE), and the like.
Referring to fig. 2, the interface 151 of the flash memory device 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH # 0 to CH # 3, each of which is connected to four NAND flash memory units, for example, channel CH # 0 is connected to NAND flash memory units 153#0, 153#4, 153#8 and 153# 12. Each NAND flash memory cell may be packaged as a separate chip (die). The flash interface 139 may activate the NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals CE # 0 to CE # 3 through the interface 151, and then read user data from the activated NAND flash memory cells in parallel, or write user data to the activated NAND flash memory cells.
Since data of a continuous segment (i.e., a continuous segment of Logical Block Addresses, LBAs) is stored dispersedly to NAND flash memory units connected to a plurality of channels, the flash controller 130 records a correspondence relationship between a Logical address (managed by the host device 110) and a Physical address (managed by the flash controller 130) of user data using a Logical-Block-address to Physical-Block-address (L2P Mapping Table). The L2P lookup table contains a plurality of records, storing information in the order of logical addresses at which physical addresses the user data for each logical address is actually stored. Data for a continuous piece of LBA may be split into multiple parts (Regions), identified by part numbers, and each part may be split into multiple Sub-Regions, identified by Sub-region numbers. For example, 128GB of data addressed using LBAs may be split into 16 8GB portions, and each 8GB portion may be further split into 256 32MB sub-regions. In the eMMC specification, each LBA is associated with (or points to) 512 Bytes (Bytes) of data. However, since the RAM136 cannot provide enough space to store the entire L2P lookup table for the processing unit 134 to quickly search in future data reading operation, the entire L2P lookup table may be divided into a plurality of sub-tables according to the division of local and sub-regions, and stored in different physical addresses of the non-volatile flash memory device 150, so that only the corresponding sub-table is read from the flash memory device 150 to the RAM136 in future data reading operation. Referring to FIG. 3, the entire L2P lookup table can be divided into sub-tables 330# 0-330 # 15. The processing unit 134 further maintains a High-level Mapping Table (High-level Mapping Table)310, which includes a plurality of records, and stores the physical address information of the sub-Table associated with each LBA run in the order of logical addresses. For example, the associated sub-table 330#0 for 0 th to 4095 th LBAs stores the 0 th physical page in a particular physical block (the letter "Z" may represent the Number of LUN and physical block) of a particular Logical Unit Number (LUN), the associated sub-table 330#1 for 4096 th to 8191 th LBAs stores the 1 st physical page in a particular physical block of a particular LUN, and so on. Although fig. 3 only includes 16 sub-tables, those skilled in the art can set more sub-tables according to the capacity of the flash memory device 150, and the invention is not limited thereto.
To accommodate the Physical configuration of flash memory device 150, flash controller 130 may associate (or point to) a Physical Block Address (PBA) with 4KB, 8KB, or 16KB of data that is greater than the length of data associated with a LBA of the eMMC specification (512B). Because the LBA is not consistent with the data length associated with the PBA, each record in each sub-table contains information for a logical address and a physical address for accurately indicating the address in flash device 150. Referring to fig. 4, the sub-table 330#0 sequentially stores Addressing Information (Addressing Information) from LBA # 0 to LBA # 4095. The addressing information can be represented in eight bytes: four bytes represent LBA; the other four bytes represent the PBA. For example, record 400 in sub-table 330#0 associated with LBA # 2 stores information for LBA 410 and PBA 430. Two bytes 430-0 in the PBA 430 record a logical unit Number and a Physical Block Number (Physical Block Number); the other two bytes 430-1 record a Physical Page Number (Physical Page Number). Therefore, the physical address information 400 corresponding to LBA # 2 may point to a particular Sector (Sector)450#2 in the physical page 450 of the physical block 440.
To solve the problem of flash controller 130 spending too much time on logical-to-physical translation, the embodiment of the present invention adds a new function of HPA on the basis of Host-Device communication Architecture (Host-Device communication Architecture) of the current eMMC specification. HPA enables the host 110 to perform time-consuming logical-physical mapping of the workload originally implemented by the flash controller 130 to improve the random access performance for short-length data, which may be 512B to 32KB in length. Referring to fig. 5, the host 110 configures a space in its System Memory (System Memory) as an HPA cache 500 for temporarily storing information of the L2P lookup table maintained and managed by the device. HPA cache 500 stores a plurality of L2P Mapping Records (L2P Mapping Records) received from the device side, each L2P Mapping record corresponding to addressing information for one LBA. Then, the host 110 can issue a command carrying the L2P mapping record to the device for obtaining the user data with the specified LBA. Flash controller 130 may drive flash interface 139 to read the user data at the specified LBA from flash device 150 directly according to the information in the L2P reference record without the need to spend time and computational resources reading the corresponding sub-tables from flash device 150 and performing logical-to-physical address translation to read the user data at the specified LBA from flash device 150 as before. The establishment and operation of HPA cache 500 can be divided into three phases:
stage I (HPA initialization): the host 110 reads the value of the register 137 in the flash controller 130 and checks whether the eMMC storage device (or device side, including at least the flash controller 130 and the flash memory device 150) supports HPA functionality. If so, the host 110 allocates space in the system memory as the HPA L2P lookup table region.
Stage II (HPA lookup table management): if the eMMC storage device supports HPA functionality, host terminal 110 issues a series of commands requesting flash controller 130 to read the L2P lookup table. In response to the series of commands, the flash controller 130 transmits all or a portion of the L2P LUT to the host 110, so that the host 110 stores the obtained LUT in the HPA L2P LUT (this may be called mirror L2P LUT, Mirrored L2P Mapping Table). When the actual L2P lookup table corresponding to the mirror image L2P lookup table is changed by Data writing, Data Trimming (Data Trimming), Garbage Collection (GC), Wear Leveling (Wear Leveling), and other procedures, the flash controller 130 notifies the host 110 that all or a corresponding portion of the L2P lookup table in the system memory of the host 110 needs to be updated.
Stage III (HPA read): the host side 110 issues a series of commands to the eMMC storage device with the L2P collation record to request that data for a particular LBA (particularly small chunk length discontinuity data, such as 512B to 32KB discontinuity data) be retrieved, wherein the L2P collation record is searched from the mirror L2P collation table. Then, the flash controller 130 reads the data of the designated LBA from the PBA of the flash memory device 150 according to the contents of the L2P collation record, and replies the read data to the host 110, so that the eMMC storage device can save the time for reading and searching the L2P collation table for the logical-physical collation conversion.
In the eMMC specification, Ext _ CSD [160] (also known as PARTITIONING _ SUPPORT [160]) defines Supported Partition Features (Supported Partition Features), where Bits [7:3] are reserved for free use by the eMMC memory device manufacturer. The 3 rd Bit of the 160 th byte of the Ext _ CSD register (Ext _ CSD [160], Bit [3]) may be used to define whether the eMMC memory device supports HPA functionality, set to "1" if supported, and set to "0" if shut down. During initialization of the eMMC storage device, the processing unit 134 may set Ext _ CSD [160], Bit [3] in the register 137 to "1". Although embodiments of the present invention describe a solution where the eMMC memory device is defined by Ext _ CSD [160] and Bit [3] to support HPA functionality, those skilled in the art may modify the design to use other reserved bits in the Ext _ CSD register, such as Ext _ CSD [511:506], Ext _ CSD [485:309], Ext _ CSD [306], Ext _ CSD [233], Ext _ CSD [227], Ext _ CSD [204], Ext _ CSD [195], Ext _ CSD [193], Ext _ CSD [190], Ext _ CSD [188], Ext _ CSD [186], Ext _ CSD [184], Ext _ CSD [182], Ext _ CSD [180], Ext _ CSD [176], Ext _ CSD [172], Ext _ CSD [170], Ext _ CSD [135], Ext _ CSD [129: 128: 127 ], Ext _ CSD [64] Ext _ CSD [28, etc., and thus the present invention is not limited to the invention.
In addition, the flash controller 130 may use a pair of Ext _ CSD registers to record the information specifying the local and sub-regions to be updated in the L2P lookup table cached by the host 110. For example, the 64 th byte (Ext _ CSD [64]) and the 66 th byte (Ext _ CSD [66]) of the Ext _ CSD register are a pair for indicating the 0 th local (Region #0) and the 160 th sub-area (subregions #160), respectively. The 65 th byte (Ext _ CSD [65]) and the 67 th byte (Ext _ CSD [67]) of the Ext _ CSD register are another pair to indicate the 0 th local (Region #0) and 18 th sub-Region (subregions #18), respectively.
In the eMMC specification, a switch command (CMD6) is issued by the host terminal 110 for switching the operating mode of a selected device or modifying the value of an Ext _ CSD register, while Bits 26 through 31 (Bits [31:26]) of the parameter are reserved Bits. Host 110 can set the 26 th Bit (CMD6, Bit [26]) of CMD6 to indicate whether the HPA function is activated, and set it to "1" if activated and "0" if deactivated. Although the embodiment of the present invention describes the technical solution of defining whether to enable the HPA function with CMD6, Bit [26], those skilled in the art may change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereto. Host 110 can set the 27 th Bit (CMD6, Bit [27]) of CMD6 to indicate whether the L2P lookup table capture function is enabled, set to "1" if enabled, and set to "0" if disabled. Although the embodiment of the present invention describes the technical solution of defining whether to enable the obtaining function of the L2P look-up table by CMD6, Bit [27], those skilled in the art may change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereto.
In the eMMC specification, a set block number command (CMD23) is issued by the host terminal 110 to indicate the number of blocks of a following packed write command, or the number of blocks of a Header (Header) of a following packed read command. When CMD23 is associated with the following packed write command, the 30 th Bit (Bit [30]) in the parameter is set to "0 b 1", and the 0 th to 15 th Bits (Bits [15:0]) in the parameter of CMD23 are used to indicate the number of blocks. When CMD23 is associated with a subsequent packed write command or packed read command, the 30 th Bit (Bit [30]) in the parameter is set to "0 b 1". Bits 0 to 15 (Bits [15:0]) in the parameters of CMD23 are used to indicate the number of blocks.
In the eMMC specification, a write multi-block Command (CMD25) is issued by the host 110 for writing data blocks to the eMMC storage device until a STOP TRANSMISSION Command (CMD 12) is issued or the requested number of data blocks has been written. The host 110 may send information specifying the local and sub-regions in the L2P lookup table through CMD23 and CMD25, requesting the flash controller 130 to prepare an L2P lookup record specifying the local and sub-regions. In addition, host 110 can send L2P parity records through CMD23 and CMD25, requesting flash controller 130 to prepare data for future reading. The 0 th to 31 th Bits (Bits [31:0]) in the parameters of CMD25 represent data addresses.
In the eMMC specification, a read multi-block Command (CMD18) is issued by the host terminal 110 to continue reading data blocks from the eMMC storage device until the requested number of data blocks have been read or interrupted by a Stop Command (Stop Command). That is, CMD18 requests the eMMC storage device to transfer the previously indicated number of data blocks to host side 110. The 0 th to 31 th Bits (Bits [31:0]) in the parameters of CMD18 represent data addresses. Host side 110 can request flash controller 130 through CMD23 and CMD18 to transfer an L2P collation record that specifies local and sub-regions (defined in previous CMD 25). Referring to the example shown in fig. 4, each L2P collation record is 8B in length, so that each data block can carry up to 32L 2P collation records. In addition, host 110 can request flash controller 130 through CMD23 and CMD18 to transfer data corresponding to the L2P collation record (defined in the previous CMD 25).
In the eMMC specification, a Normal Response Command (R1) is issued by the flash controller 130 to inform the host 110 of specific information. The length of R1 is 48 Bits, of which Bits 40 to 45 (Bits [45:40]) record the index of the command to reply, and Bits 8 to 39 (Bits [39:8]) record the Device Status. When the 31 st Bit (Bit [31]) OF R1 is set to "0 b 1", it represents that the ADDRESS exceeds the RANGE (ADDRESS _ OUT _ OF _ RANGE). When the 30 th Bit (Bit [30]) of R1 is set to "0 b 1", it represents ADDRESS _ mismatch. When the HPA function is enabled but the L2P lookup table fetch function is not enabled, if a part of PBAs in the L2P lookup record carried in CMD25 fails, the flash controller 130 may set both the 31 st Bit (Bit [31]) and the 30 th Bit (Bit [30]) of R1 for CMD18 after recovery to "0 b 1" for indicating that the L2P lookup record cached in the host 110 needs to be updated.
For the setup of HPA L2P lookup table (also referred to as HPA buffer) in stages I and II, after eMMC storage device initialization, host side 110 reads L2P lookup table from device side for the first time and stores it to HPA buffer. Table 1 describes example command sequence details for initializing HPA buffers:
TABLE 1
Referring to the operation sequence diagram for HPA buffer initialization as shown in fig. 6, the following is explained in detail:
operation 611: host terminal 110 issues a command to flash controller 130 requesting flash controller 130 to obtain the value of the Ext _ CSD register.
Operation 613: in response to a register read command received through the host interface 131, the processing unit 134 obtains the value of the Ext _ CSD register in the register 137 and replies to the host 110 through the host interface 131.
In operation 615: the host side 110 may check the value of the Ext _ CSD register (e.g., Ext _ CSD [160], Bit [3]) to determine whether the eMMC memory device supports HPA functionality. If so, processing continues with operation 617. If not, no HPA function is enabled.
Operation 617: host 110 issues a switch command (CMD6) to flash controller 130 to enable HPA functionality and L2P look-up table retrieval functionality. For example, referring to the second row of table 1, the host 110 may set the parameters of CMD6 to "0 x0C 000000", i.e., including Bit [26] ═ 0b1 "and Bit [27] ═ 0b 1", for instructing the flash controller 130 to enable both functions.
Operation 619: when flash controller 130 receives the switch command as described above, it enters HPA Mapping table READ state (HPA _ Mapping _ READ state) for preparing to transmit a part of L2P Mapping table to host 110.
Operation 631: the host 110 allocates space in system memory to the HPA buffer and determines the local and sub-partitioned L2P mapping records to be retrieved from the eMMC storage device based on the needs of the operating system, drivers, applications, etc.
Operation 633: host terminal 110 issues a set block count command (CMD23) to flash controller 130 to inform flash controller 130 how many data blocks will be transferred. For example, referring to the third row of table 1, the host 110 may set the parameters of CMD23 to "0 x 40000001", i.e., including Bit [30] ═ 0b1 "and Bits [15:0] ═ 0x 0001", indicating that a block of data is to be written to the flash controller 130 later. Next, host 110 issues a write multi-block command (CMD25) to flash controller 130 for writing data blocks to flash controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of Table 1, the host 110 may set the parameter CMD25 to "0 x01E2A3E 0", representing a particular data address. Each data block may be divided into 32 Packets (Packets), with each packet being 16B in length. The 2 bytes in each packet may indicate the number of a particular part, while the remaining 14 bytes may indicate the number of a plurality of particular sub-regions. For example, when a packet contains information of { Region # 0, subregions # 1, subregions # 2, subregions #3}, the designated portion of the representative L2P lookup table is associated with the 0 th to 3 rd subregions in the 0 th part. Next, the host 110 issues a set block count command (CMD23) to the flash controller 130 to inform the flash controller 130 how many data blocks will be received. For example, referring to the fourth row of table 1, the host 110 may set the parameters of CMD23 to "0 x 40000020", i.e., including Bit [30] ═ 0b1 "and Bits [15:0] ═ 0x 0020", indicating that 32 data blocks, i.e., up to 1024L 2P parity records, are to be read from the flash controller 130. Next, host 110 issues a read multi-block command (CMD18) to flash controller 130 for reading data blocks from flash controller 130 until the requested number of data blocks have been read. For example, referring to the fifth row of table 1, the host 110 may set the parameter CMD18 to "0 x01E2A3E 0", representing a specific data address.
Operation 635: since the HPA lookup table read state has been entered, when flash controller 130 receives the data block corresponding to CMD25 from host 110, it knows that each packet therein carries information of the designated portion of the L2P lookup table, and can accordingly read the requested L2P lookup record from flash device 150. In addition, when flash controller 130 receives CMD18 from host side 110, it knows that it can start transferring the L2P cross-reference record of the specified portion to host side 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transferred by flash controller 130 is a L2P parity record of the specified portion read from flash device 150 according to the contents in the data block previously written by CMD 25.
Operation 651: flash controller 130 organizes the requested L2P into multiple packets in a specified number of data blocks against the record.
Operation 653: the flash controller 130 continues to transfer the organized blocks of data to the host 110 until the specified number of blocks of data have been transferred. Then, when the information that the packed read is complete is received from the host side 110, the HPA lookup table read State is exited and the Transfer State (Transfer State) of the eMMC specification is entered.
Operation 655: the host side 110 receives the L2P contrast record carried in each packet and stores it in the HPA buffer. After storing the L2P mapping record carried in the last packet, the host 110 issues a SEND _ STATUS command (CMD13) to the flash controller 130, which includes the information of the completion of the packed read.
For stage III data reads, Table 2 describes example command sequence details for reading data using the HPA function:
TABLE 2
Referring to the operation sequence diagram for HPA read as shown in fig. 7, the following is explained in detail:
operation 711: the host side 110 finds that random reading of short length data is about to occur.
Operation 713: host terminal 110 issues a switch command (CMD6) to flash controller 130 to initiate HPA functions. For example, referring to the second row of table 2, the host 110 may set the parameters of CMD6 to "0 x 04000000", i.e., Bit [26] ═ 0b1 "and Bit [27] ═ 0b 0", which are used to instruct the flash controller 130 to enable only HPA functions.
Operation 715: when flash controller 130 receives the switch command as described above, it enters the HPA READ state (HPA _ READ state).
Operation 731: the host side 110 searches the mirror L2P lookup table in the HPA buffer to obtain L2P lookup records corresponding to multiple LBAs.
In operation 733: host terminal 110 issues a set block count command (CMD23) to flash controller 130 to inform flash controller 130 how many data blocks will be transferred. For example, referring to the third row of table 2, the host 110 may set the parameters of CMD23 to "0 x 40000001", i.e., including Bit [30] ═ 0b1 "and Bits [15:0] ═ 0x 0001", indicating that a block of data is to be written to the flash controller 130 later. Next, host 110 issues a write multi-block command (CMD25) to flash controller 130 for writing data blocks to flash controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of table 2, the host 110 may set the parameter CMD25 to "0 x 01521182" representing a particular data address. Each data block may be divided into 32 Packets (Packets), with each packet being 16B in length. Each packet is associated with a pair of LBA and PBA information, 8 bytes of which may indicate a particular LBA and the remaining 8 bytes may indicate a particular PBA. Next, the host 110 issues a set block count command (CMD23) to the flash controller 130 to inform the flash controller 130 how many data blocks will be received. For example, referring to the fifth row of table 2, the host 110 may set the parameters of CMD23 to "0 x 40000020", i.e., including Bit [30] ═ 0b1 "and Bits [15:0] ═ 0x 0020", indicating that 32 data blocks, i.e., data of up to 1024 LBAs, are to be read from the flash controller 130. Next, host 110 issues a read multi-block command (CMD18) to flash controller 130 for reading data blocks from flash controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of table 2, the host 110 may set the parameter CMD18 to "0 x 01521182" representing a specific data address.
Operation 735: since the HPA read state has been entered, when flash controller 130 receives the block of data corresponding to CMD25 from host 110, it knows that each packet therein carries the information of the pair of LBA and PBA read for one data, and can accordingly read the requested data from flash device 150. In addition, when flash controller 130 receives CMD18 from host side 110, it knows that it can begin transmitting the specified data to host side 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transferred by flash controller 130 is the data of the specified LBA read from flash memory device 150 according to the contents in the data block previously written by CMD 25.
Operation 751: flash controller 130 organizes the requested data into a plurality of packets in a specified number of data blocks.
Operation 753: the flash controller 130 continues to transfer the organized blocks of data to the host 110 until the specified number of blocks of data have been transferred. Then, when the information that the packed read is complete is received from the host side 110, the HPA read state is exited and the transmit state of the eMMC specification is entered.
Operation 755: the host side 110 receives the data carried in each packet and stores it in a data buffer in system memory. After storing the data carried in the last packet, the host 110 issues a transfer status command (CMD13) to the flash controller 130, which includes the information that the read in the packet is complete.
For the update of the HPA buffer in phase II, during the device operation, the host 110 may request the flash controller 130 to perform Data write, Data trim (Data Trims), Block erase (Block Erases), etc., and the flash controller 130 may actively perform Garbage Collection (GC), Wear Leveling (WL), etc., to cause part of the contents of the L2P lookup table to be changed. Therefore, the contents of the HPA buffer (i.e., the mirror L2P look-up table) need to be updated in accordance with the changed contents of the L2P look-up table. Referring to the operation sequence diagram of HPA read as shown in fig. 8, the technical solution of operations 711 to 733 and 751 to 753 is the same as that of fig. 7, and the rest of the operations are described in detail as follows:
operation 835: since the HPA read state has been entered, when flash controller 130 receives the data block corresponding to CMD25 from host 110, it knows that each packet therein carries information for the pair of LBA and PBA read for one data, and checks whether the LBA comparison record for the LBA data to be read is changed (i.e., invalid). If so, the flash controller 130 ignores the information carried in the data block and instead reads data from the flash memory device 150 according to the changed corresponding LBA reference record. When flash controller 130 receives CMD18 from host side 110, it knows that it can begin transmitting the specified data to host side 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transferred by flash controller 130 is the data of the designated LBA read from flash memory device 150 according to the content in the data block previously written by CMD25 or according to the content in the corresponding LBA reference record after the change. In addition, when the LBA comparison record of the LBA data to be read is invalid, the flash controller 130 sets the relevant Ext _ CSD register to store the information of the local and sub-areas of the HPA buffer of the host 110 that need to be updated.
Operation 837: the flash controller 130 issues R1 for recovering CMD18, in which the 31 st Bit (Bit [31]) and the 30 th Bit (Bit [30]) are both set to "0 b 1" to indicate that the mirror L2P lookup table at the host 110 needs to be updated.
After the host 110 receives the information that the mirror L2P lookup table needs to be updated from the device, the host 110 obtains the information of the local part and the sub-area that need to be updated from the device, and accordingly reads the L2P lookup record of the designated part in the L2P lookup table from the device, and updates the corresponding content in the HPA buffer. Table 3 describes example command order details for updating HPA buffers:
TABLE 3
Referring to the operation sequence diagram for HPA buffer update shown in fig. 9, the technical solutions of operations 611, 613, 617, 619, 633, 635, 651 and 653 therein are the same as those of fig. 6, and the rest of the operations are described in detail as follows:
operation 915: the host side 110 obtains the information of the local and sub-regions that need to be updated from the value of the Ext _ CSD register (e.g., Ext _ CSD [67:64 ]).
Operation 931: the host 110 determines the L2P match record for the local and sub-regions to be retrieved from the eMMC storage device based on information retrieved from the flash controller 130.
Operation 955: the host side 110 receives the L2P contrast record carried in each packet and updates the corresponding portion of the contents in the HPA buffer. After updating the L2P mapping record carried in the last packet, the host 110 sends CMD13 to the flash controller 130, which includes the information that the read is completed in a packet.
Details regarding the execution of CMD6 in command processing operations 619, 715 may be found in a method flowchart as shown in fig. 10, which is implemented by processing unit 134 when loading and executing the relevant software or firmware program code, as further described below:
step S1010: a switch command is received from the host side 110 through the host interface 131 (CMD 6).
Step S1020: it is determined whether the reserved bits of CMD6 contain information for starting the HPA function and the fetch function of the L2P lookup table. If so, the flow proceeds to the processing of step S1030. Otherwise, the flow continues the processing of step S1040.
Step S1030: RAM136 stores information to enter the HPA lookup table read state for use in determining the current device state when CMD25 is later received.
Step S1040: it is determined whether the reserved bits of CMD6 contain information to activate the HPA function. If so, the flow proceeds to the processing of step S1050. Otherwise, the flow proceeds to the processing of step S1060.
Step S1050: RAM136 stores information to enter the HPA read state for later receipt of CMD25 as a basis for determining the current device state.
Step S1060: a conventional handover procedure is performed. For example, switching the operation mode of the device side, modifying the value of the Ext _ CSD register, and the like.
Details regarding the execution of CMD25 in command processing operations 635, 735, and 835 can be found in the method flowchart shown in fig. 11, which is implemented by processing unit 134 when loading and executing the relevant software or firmware program code, and are further described below:
step S1110: a write multi-block command (CMD25) is received from host side 110 through host interface 131, along with the following data blocks.
Step S1121: whether to enter an HPA look-up table read state or an HPA read state is determined based on information stored in the RAM 136. If so, the flow proceeds to the further determination of step S1131. Otherwise, the flow proceeds to the processing of step S1123.
Step S1123: a conventional Packed Write Procedure (Packed Write Procedure) is executed for driving the flash interface 139 to Write multiple packets of data to the flash memory device 150.
Step S1131: whether to enter the HPA look-up table reading state is judged according to the information stored in the RAM 136. If so, the flow proceeds to the processing of step S1133. Otherwise (i.e., enter HPA read state), the flow proceeds to step S1141.
Step S1133: the drive flash interface 139 reads the L2P parity record for the specified portion of the L2P parity table from the flash device 150 based on the information carried in the data block (i.e., the information for the particular local and particular sub-regions).
Step S1135: storing the L2P collation record in the multi-packet format as described above to the RAM136 enables the L2P collation record to be transmitted in the multi-packet format to the host side 110 in the future after receiving the CMD 18.
Step S1141: it is determined whether the LBA comparison record associated with the LBA data to be read has been changed. If so, the flow proceeds to the process of step S1145. Otherwise, the flow proceeds to the process of step S1143.
Step S1143: drive flash interface 139 reads the data for the specified LBA from flash device 150 according to the information carried in the data block (i.e., the information recorded against L2P).
Step S1145: the drive flash interface 139 reads the data of the designated LBA from the flash memory device 150 according to the changed corresponding LBA comparison record.
Step S1147: storing the data specifying the LBA in a multi-packet format as described above to RAM136 enables the data specifying the LBA to be transferred in a multi-packet format to host side 110 in the future after CMD18 is received.
All or part of the steps of the method of the present invention may be implemented by a computer program, such as a Firmware Translation Layer (FTL) in a storage device, a driver of specific hardware, or a software program. In addition, other types of programs as shown above may also be implemented. Those skilled in the art can write the method of the embodiments of the present invention as program code, and will not be described again for the sake of brevity. The computer program implemented according to the embodiments of the present invention can be stored in a suitable computer readable storage medium, such as a DVD, a CD-ROM, a usb disk, a hard disk, or can be disposed in a network server accessible via a network (e.g., the internet, or other suitable medium).
Although the above-described elements are included in fig. 1-2, it is not excluded that more additional elements may be used to achieve better technical results without departing from the spirit of the present invention. Further, although the flowcharts of fig. 10 and 11 are executed in the order specified, a person skilled in the art can modify the order between these steps without departing from the spirit of the invention to achieve the same effect, and therefore, the invention is not limited to use of only the order described above. In addition, a person skilled in the art may also integrate several steps into one step, or perform more steps in sequence or in parallel besides these steps, and the present invention should not be limited thereby.
The above description is only for the preferred embodiment of the present invention, and it is not intended to limit the scope of the present invention, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present invention, therefore, the scope of the present invention should be determined by the claims of the present application.
Claims (14)
1. A data reading method of a host performance acceleration mode is executed by a host, and is characterized by comprising the following steps:
obtaining a first value of an expansion device-specific data register in a flash memory controller from the flash memory controller, wherein the host terminal and the flash memory controller communicate with each other using an embedded multimedia card communication protocol; and
when the first value of the extended device-specific data register contains information supporting a host performance acceleration function, allocating space in a system memory as a host performance acceleration buffer, and storing a plurality of first logical-physical comparison records obtained from the flash memory controller in the host performance acceleration buffer, wherein each of the first logical-physical comparison records is used for storing information of a physical address at which data of a logical address is actually stored.
2. The method of claim 1, wherein each of the first logical-to-physical comparison records comprises a logical block address and a physical block address, the logical block address is associated with data of a first length, the physical block address is associated with data of a second length, and the second length is greater than the first length.
3. The method as claimed in claim 2, wherein the first length is 512 bytes.
4. The method of claim 1, further comprising:
searching the host performance acceleration buffer to obtain a second logical-physical comparison record associated with a logical block address; and
issuing a series of commands to the flash memory controller using the second logical-to-physical mapping record for retrieving the data of the logical block address from the flash memory controller.
5. The method of claim 4, further comprising:
receiving a normal reply command from the flash memory controller corresponding to one of the series of commands indicating that the contents of the host performance acceleration buffer need to be updated;
after receiving the normal reply command, obtaining a second value of the expansion device-specific data register in the flash memory controller from the flash memory controller;
obtaining information of a portion of the host performance acceleration buffer that needs to be updated from the second value of the extended device-specific data register;
acquiring a plurality of third logical physical comparison records of the part needing to be updated in a logical physical comparison table from the flash memory controller; and
updating a corresponding portion of the contents of the host performance acceleration buffer to the third logical-to-physical comparison record.
6. The method as claimed in claim 5, wherein the portion to be updated is represented by a local number and a sub-area number, and the data of a segment of consecutive logical block addresses is divided into a plurality of local portions, each of the local portions being divided into a plurality of sub-areas.
7. A data reading method of a host performance acceleration mode is executed by a flash memory controller, and is characterized by comprising the following steps:
during the initialization process of the storage device, setting the reserved bit of the expansion device-specific data register in the flash memory controller for indicating that the storage device supports the host performance acceleration function, so that the host can allocate space in the system memory as a host performance acceleration buffer according to the information of the reserved bit of the expansion device-specific data register, and store a plurality of first logical physical comparison records obtained from the flash memory controller in the host performance acceleration buffer,
wherein, each of the first logical-physical comparisons records information of a physical address where data for storing a logical address is actually stored, and the host terminal and the flash memory controller communicate with each other using an embedded multimedia card communication protocol.
8. The method as claimed in claim 7, wherein the extended device specific data register comprises an attribute field and a mode field, the attribute field defines device attributes and cannot be changed by the host, and the mode field defines settings currently running on the device and allows the host to be changed by a switch command.
9. The method of claim 7, further comprising:
receiving a series of commands with a second logical-physical reference record from the host side for requesting data of a logical block address;
when the second logic physical comparison record is checked to be invalid, setting a reserved byte of the special data register of the expansion device for storing information of a part needing to be updated in the host efficiency acceleration buffer; and
sending a normal reply command corresponding to one of the commands to the host, indicating that the contents of the host performance acceleration buffer need to be updated, for driving the host to update the designated contents of the host performance acceleration buffer according to the information of the reserved bytes of the extended device-specific data register.
10. A data reading apparatus in a host performance acceleration mode, comprising:
extending device-specific data registers;
the host interface is coupled with the host end; and
a processing unit, coupled to the expansion device specific data register and the host interface, for setting a reserved bit of the expansion device specific data register during initialization of the device, for indicating that the device supports a host performance acceleration function, so that the host can allocate a space in a system memory as a host performance acceleration buffer according to information of the reserved bit of the expansion device specific data register, and store a plurality of first logical-physical comparison records obtained from the device through the host interface in the host performance acceleration buffer,
wherein, each of the first logical-physical comparisons records information of a physical address where data for storing a logical address is actually stored, and the host terminal and the device communicate with each other through the host interface using an embedded multimedia card communication protocol.
11. The apparatus of claim 10, wherein each of the first logical-to-physical comparison records comprises a logical block address and a physical block address, the logical block address is associated with data of a first length, the physical block address is associated with data of a second length, and the second length is greater than the first length.
12. The apparatus of claim 11, wherein the first length is 512 bytes.
13. The device according to claim 10, wherein the extended device-specific data register comprises an attribute field and a mode field, the attribute field defining device attributes and being not modifiable by the host, and the mode field defining settings currently running on the device and allowing modification by the host via a switch command.
14. The apparatus as claimed in claim 10, wherein the processing unit receives a series of commands with a second logical-physical mapping record from the host through the host interface for requesting data of logical block addresses; when the second logic physical comparison record is checked to be invalid, setting a reserved byte of the special data register of the expansion device for storing information of a part needing to be updated in the host efficiency acceleration buffer; and sending a normal reply command corresponding to one of the commands to the host, indicating that the contents of the host performance acceleration buffer need to be updated, for driving the host to update the designated contents of the host performance acceleration buffer according to the information of the reserved bytes of the extended device-specific data register.
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915208A (en) * | 2011-08-01 | 2013-02-06 | 株式会社东芝 | Information processing apparatus, semiconductor memory device and control method for the semiconductor memory device |
| US9547447B2 (en) * | 2014-01-03 | 2017-01-17 | Advanced Micro Devices, Inc. | Dedicated interface for coupling flash memory and dynamic random access memory |
| US20190235762A1 (en) * | 2018-01-29 | 2019-08-01 | Toshiba Memory Corporation | Memory system controlling nonvolatile memory |
| WO2019209707A1 (en) * | 2018-04-23 | 2019-10-31 | Micron Technology, Inc. | Host logical-to-physical information refresh |
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| TW202205098A (en) | 2022-02-01 |
| TWI761983B (en) | 2022-04-21 |
| CN113946279A (en) | 2022-01-18 |
| TW202205099A (en) | 2022-02-01 |
| TWI795680B (en) | 2023-03-11 |
| TW202205097A (en) | 2022-02-01 |
| CN113946278A (en) | 2022-01-18 |
| TWI760884B (en) | 2022-04-11 |
| TW202225979A (en) | 2022-07-01 |
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